JP2013030498A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2013030498A
JP2013030498A JP2009259240A JP2009259240A JP2013030498A JP 2013030498 A JP2013030498 A JP 2013030498A JP 2009259240 A JP2009259240 A JP 2009259240A JP 2009259240 A JP2009259240 A JP 2009259240A JP 2013030498 A JP2013030498 A JP 2013030498A
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JP
Japan
Prior art keywords
insulating film
electrode pad
opening
semiconductor device
ubm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009259240A
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Japanese (ja)
Inventor
Hiroshige Hirano
博茂 平野
Fumito Ito
史人 伊藤
Kiyomi Hagiwara
清己 萩原
Teppei Iwase
鉄平 岩瀬
Yukitoshi Ota
行俊 太田
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Panasonic Corp
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Panasonic Corp
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Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to JP2009259240A priority Critical patent/JP2013030498A/en
Priority to PCT/JP2010/004262 priority patent/WO2011058680A1/en
Publication of JP2013030498A publication Critical patent/JP2013030498A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a pad electrode structure, capable of relaxing stress concentration caused by under barrier metal, for suppressing fluctuation in characteristics of a transistor.SOLUTION: The semiconductor device includes an electrode pad 6 formed on a semiconductor substrate 1, a first insulting film 7 which contains a first opening where a part of the electrode pad 6 is exposed, a second insulating film 8 which is formed on the first insulating film and contains a second opening where at least a part in the first opening is exposed, and an under barrier metal 10 formed on the second insulating film 8 and the electrode pad 6. The under-barrier metal 10 is separated from a third region which is sandwiched between a first region, which is the outside of the second opening on the surface of the second insulating film 8, and a second region, which is the inside of the second opening on the surface of the electrode pad 6.

Description

本発明は、半導体装置に関し、特に、半田バンプの下に形成されるアンダーバリアメタル（Under Barrier Metal：ＵＢＭ）を備える半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an under barrier metal (UBM) formed under a solder bump.

半導体装置をフリップ実装するためには、一般に、電極パッドの上にバンプを設けたバンプ電極構造を採用する。例えば、特許文献１に開示されている技術を従来技術として挙げることができる。図１６を参照しながら、特許文献１に記載されている内容について説明する。   In order to flip-mount a semiconductor device, a bump electrode structure in which bumps are provided on electrode pads is generally employed. For example, the technique disclosed in Patent Document 1 can be cited as a conventional technique. The contents described in Patent Document 1 will be described with reference to FIG.

図１６に示すように、アルミパッド１１４の上には、アルミパッド１１４を露出する開口部を有するパッシベーション膜１１３が形成されている。この開口部には、密着金属層１１５ａとバリア金属層１１５ｂとが順次形成され、その上に、金属メッキバンプ１１６が形成されている。金属メッキバンプ１１６の上には、半田バンプ１２０が形成されている。ここで、特許文献１では、図１６に示すように、開口部の全面を覆い、且つ、パッシベーション膜１１３の上面に達するまで連続的に密着金属層１１５ａとバリア金属層１１５ｂを形成している。また、他にも関連する文献として、特許文献２〜９がある。   As shown in FIG. 16, a passivation film 113 having an opening exposing the aluminum pad 114 is formed on the aluminum pad 114. An adhesion metal layer 115a and a barrier metal layer 115b are sequentially formed in the opening, and a metal plating bump 116 is formed thereon. Solder bumps 120 are formed on the metal plating bumps 116. Here, in Patent Document 1, as shown in FIG. 16, the adhesion metal layer 115a and the barrier metal layer 115b are continuously formed until the entire surface of the opening is covered and the upper surface of the passivation film 113 is reached. Other related documents include Patent Documents 2 to 9.

特開２０００−１００８５２号公報JP 2000-1000085 A 特開平１１−０４０６２４号公報JP-A-11-040624 特開２００４−１６０６５４号公報JP 2004-160654 A 特開２００９−１２４０９９号公報Japanese Unexamined Patent Publication No. 2009-124099 特開２００９−０６４８４８号公報JP 2009-064848 A 特開２００７−０１２８２６号公報JP 2007-012826 A 特開２００６−０１９５５０号公報JP 2006-019550 A 特開２００４−２２８４４６号公報JP 2004-228446 A 特開平１１−２４３２０８号公報Japanese Patent Laid-Open No. 11-243208

前記従来の技術においては、開口部の全面を覆い、且つ、パッシベーション膜の上面に達するまで連続的にＵＢＭを形成し、その上に半田バンプを形成している。このようにすると、パッシベーション膜の開口部に形成される段差部（開口部におけるパッシベーション膜の表面からアルミパッドに向かう部分）にまでＵＢＭが形成されることとなる。   In the conventional technique, the UBM is continuously formed so as to cover the entire surface of the opening and reach the upper surface of the passivation film, and solder bumps are formed thereon. In this way, the UBM is formed up to the stepped portion formed in the opening of the passivation film (portion from the surface of the passivation film toward the aluminum pad in the opening).

しかし、このようなバンプ電極構造において、段差部の段差が大きいと、段差部においてＵＢＭの応力が大きくなり、半導体装置に形成されたトランジスタの特性が変動してしまう。   However, in such a bump electrode structure, if the level difference of the stepped portion is large, the stress of the UBM becomes large in the stepped portion, and the characteristics of the transistor formed in the semiconductor device will fluctuate.

また、最近の微細プロセスでは、電気特性の向上のために、配線が形成される層間絶縁膜に抵誘電率のｌｏｗ−ｋ材料等を用いることが多く、これらの材料は、従来よりも脆弱で且つ密着性が悪い。このため、半導体装置を組み立てる際に、ＵＢＭ及びその上の半田バンプから応力を受けると、層間絶縁膜において密着力の低下等が引き起こされるおそれがある。   In recent fine processes, a low-k material having a dielectric constant is often used for an interlayer insulating film on which wiring is formed in order to improve electrical characteristics, and these materials are more fragile than conventional ones. In addition, the adhesion is poor. For this reason, when assembling a semiconductor device, if stress is received from the UBM and the solder bumps thereon, there is a risk of causing a decrease in the adhesion of the interlayer insulating film.

本発明は、前記従来の問題に鑑み、その目的は、ＵＢＭに起因する応力集中を緩和し、トランジスタの特性の変動を抑制することができるパッド電極構造を備える半導体装置を得られるようにすることにある。   The present invention has been made in view of the above-described conventional problems, and an object thereof is to obtain a semiconductor device having a pad electrode structure that can relieve stress concentration caused by UBM and suppress fluctuations in transistor characteristics. It is in.

前記の目的を達成するために、本発明に係る第１の半導体装置は、基板の上に形成された電極パッドと、電極パッドの上に形成され、且つ、電極パッドの一部が露出するような第１開口部を有する第１絶縁膜と、第１絶縁膜の上に形成され、且つ、第１開口部における少なくとも一部が露出するような第２開口部を有する第２絶縁膜と、第２絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、アンダーバリアメタルは、第２絶縁膜の表面における第２開口部の外側である第１領域と電極パッドの表面における第２開口部の内側である第２領域とにより挟まれる第３領域によって分離されていることを特徴とする。   To achieve the above object, a first semiconductor device according to the present invention is formed on an electrode pad formed on a substrate, on the electrode pad, and a part of the electrode pad is exposed. A first insulating film having a first opening, a second insulating film formed on the first insulating film and having a second opening so that at least a part of the first opening is exposed; An under-barrier metal formed on the second insulating film and the electrode pad, the under-barrier metal being a first region outside the second opening on the surface of the second insulating film and the first barrier on the surface of the electrode pad. It is characterized by being separated by a third region sandwiched between a second region inside the two openings.

本発明に係る第１の半導体装置は、アンダーバリアメタルの上に半田バンプが形成されていることが好ましい。   In the first semiconductor device according to the present invention, it is preferable that solder bumps are formed on the under barrier metal.

この場合、第３領域において、半田バンプは、第２絶縁膜又は電極パッドとの間に空隙を形成していてもよい。   In this case, in the third region, the solder bump may form a gap between the second insulating film or the electrode pad.

本発明に係る第１の半導体装置は、第２領域において、アンダーバリアメタルは、第１絶縁膜と接触していてもよい。   In the first semiconductor device according to the present invention, the under barrier metal may be in contact with the first insulating film in the second region.

本発明に係る第１の半導体装置は、第１領域において、アンダーバリアメタルは、複数に分割されていることが好ましい。   In the first semiconductor device according to the present invention, the under barrier metal is preferably divided into a plurality of parts in the first region.

本発明に係る第１の半導体装置は、第２領域において、アンダーバリアメタルは、複数に分割されていることが好ましい。   In the first semiconductor device according to the present invention, the under barrier metal is preferably divided into a plurality of parts in the second region.

本発明に係る第２の半導体装置は、基板の上に形成された電極パッドと、電極パッドの上に形成され、且つ、電極パッドの一部が露出するような第１開口部を有する第１絶縁膜と、第１絶縁膜の上に形成され、且つ、第１開口部における少なくとも一部が露出するような第２開口部を有する第２絶縁膜と、第２絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、第２絶縁膜は、第２絶縁膜の表面から電極パッドに向かう傾斜部を有し、傾斜部における基板の平面方向に対する傾斜角は４５度以下であることを特徴とする。   A second semiconductor device according to the present invention includes an electrode pad formed on a substrate, and a first opening formed on the electrode pad and having a first opening that exposes a part of the electrode pad. An insulating film, a second insulating film formed on the first insulating film and having a second opening so that at least a part of the first opening is exposed, and on the second insulating film and the electrode pad The second insulating film has an inclined portion directed from the surface of the second insulating film to the electrode pad, and an inclination angle of the inclined portion with respect to the planar direction of the substrate is 45 degrees or less. It is characterized by that.

本発明に係る第２の半導体装置において、第１絶縁膜は、複数の段差を有し、アンダーバリアメタルは、複数の段差を含む第１絶縁膜の上にも形成されることが好ましい。   In the second semiconductor device according to the present invention, it is preferable that the first insulating film has a plurality of steps, and the under barrier metal is also formed on the first insulating film including the plurality of steps.

本発明に係る第２の半導体装置において、傾斜部及び複数の段差における基板の平面方向に対する傾斜角の平均値は、４５度以下であることが好ましい。   In the second semiconductor device according to the present invention, it is preferable that the average value of the inclination angle with respect to the planar direction of the substrate at the inclined portion and the plurality of steps is 45 degrees or less.

本発明に係る第３の半導体装置は、基板の上に形成された電極パッドと、電極パッドの上に形成され、且つ、電極パッドの一部が露出するような第１開口部を有する第１絶縁膜と、第１絶縁膜の上に形成され、且つ、第１開口部における少なくとも一部が露出するような第２開口部を有する第２絶縁膜と、第１絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、第１絶縁膜は、複数の段差を有し、アンダーバリアメタルは、複数の段差を含む第１絶縁膜の上に形成されることを特徴とする。   A third semiconductor device according to the present invention includes an electrode pad formed on a substrate, and a first opening formed on the electrode pad and having a first opening that exposes part of the electrode pad. An insulating film, a second insulating film formed on the first insulating film and having a second opening that exposes at least a part of the first opening, and on the first insulating film and the electrode pad And the under barrier metal is formed on the first insulating film including the plurality of steps. The under barrier metal is formed on the first insulating film including the plurality of steps.

本発明に係る第３の半導体装置において、複数の段差における基板の平面方向に対する傾斜角の平均値は、４５度以下であることが好ましい。   In the third semiconductor device according to the present invention, the average value of the inclination angles with respect to the planar direction of the substrate at the plurality of steps is preferably 45 degrees or less.

本発明に係る第２の半導体装置及び第３の半導体装置は、アンダーバリアメタルの上に半田バンプが形成されていることが好ましい。   In the second semiconductor device and the third semiconductor device according to the present invention, it is preferable that solder bumps are formed on the under barrier metal.

本発明に係る第１の半導体装置、第２の半導体装置及び第３の半導体装置において、第１絶縁膜は、窒化シリコン、窒素含有酸化シリコン又は酸化シリコンからなる無機材料膜を含むことが好ましい。   In the first semiconductor device, the second semiconductor device, and the third semiconductor device according to the present invention, the first insulating film preferably includes an inorganic material film made of silicon nitride, nitrogen-containing silicon oxide, or silicon oxide.

本発明に係る第１の半導体装置、第２の半導体装置及び第３の半導体装置において、第２絶縁膜は、ポリイミド、ベンゾシクロブテン又はフッ素樹脂からなる有機材料膜を含むことが好ましい。   In the first semiconductor device, the second semiconductor device, and the third semiconductor device according to the present invention, the second insulating film preferably includes an organic material film made of polyimide, benzocyclobutene, or a fluororesin.

本発明に係る半導体装置によると、電極パッドの上に形成されるＵＢＭに起因する応力集中を十分に緩和することが可能となる。そのため、半導体装置に形成されたトランジスタの特性変動を抑制することができ、回路動作マージンを確保でき、安定した動作を可能とする。   According to the semiconductor device of the present invention, it is possible to sufficiently relax the stress concentration caused by the UBM formed on the electrode pad. Therefore, characteristic variation of the transistor formed in the semiconductor device can be suppressed, a circuit operation margin can be secured, and stable operation can be performed.

本発明の第１の実施形態に係る半導体装置を示す断面図である。1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施形態に係る半導体装置を示す平面図である。1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. （ａ）〜（ｃ）は本発明の第１の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。(A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. （ａ）及び（ｂ）は本発明の第１の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。(A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. （ａ）及び（ｂ）は本発明の第１の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。(A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. （ａ）及び（ｂ）は本発明の第１の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。(A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. 本発明の第１の実施形態の第１の変形例に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on the 1st modification of the 1st Embodiment of this invention. 本発明の第１の実施形態の第２の変形例に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on the 2nd modification of the 1st Embodiment of this invention. 本発明の第１の実施形態の第２の変形例に係る半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on the 2nd modification of the 1st Embodiment of this invention. 本発明の第１の実施形態の第３の変形例に係る半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on the 3rd modification of the 1st Embodiment of this invention. 本発明の第１の実施形態の第４の変形例に係る半導体装置を示す平面図である。It is a top view which shows the semiconductor device which concerns on the 4th modification of the 1st Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る半導体装置において、第２絶縁膜のテーパー角度と第２開口部に加わる応力との関係を示すグラフである。6 is a graph showing a relationship between a taper angle of a second insulating film and a stress applied to a second opening in a semiconductor device according to a second embodiment of the present invention. 本発明の第３の実施形態に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on the 3rd Embodiment of this invention. 本発明の第４の実施形態に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on the 4th Embodiment of this invention. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device.

本発明の半導体装置の実施形態について図面を参照しながら説明する。また、以下に示す各図、種々の構成要素の形状、材料及び寸法等はいずれも望ましい例を挙げるものであり、示した内容には限定されない。発明の趣旨を逸脱しない範囲であれば、記載内容に限定されることなく適宜変更可能である。また、他の実施形態および変形例に記載の内容を矛盾の無い範囲で適宜組み合わせることも可能である。   Embodiments of a semiconductor device of the present invention will be described with reference to the drawings. Further, each of the following drawings and shapes, materials, dimensions, and the like of various components are preferable examples, and are not limited to the contents shown. As long as it does not deviate from the gist of the invention, it can be appropriately changed without being limited to the description. Moreover, it is also possible to combine suitably the content as described in other embodiment and modification in the range without a contradiction.

（第１の実施形態）
本発明の第１の実施形態に係る半導体装置ついて図１及び図２を用いて説明する。なお、図２は、半田バンプ１１を省略している。 (First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. In FIG. 2, the solder bumps 11 are omitted.

図１に示すように、トランジスタ等の回路素子２を有する半導体基板１の上には、複数の配線からなる第１配線層３が形成され、その上には、複数の配線からなる複数の第２配線層４が形成されている。最上層配線の上に形成された第３絶縁膜５には電極パッド６が形成されている（最上層配線と電極パッド６とは接続している）。第３絶縁膜５を含む電極パッド６の上には、電極パッド６の一部が露出するような第１開口部を有する第１絶縁膜７が形成されている。第１絶縁膜７の上には、第１開口部の少なくとも一部を含むような（第１開口部の少なくとも一部を露出するような）、第２開口部を有する第２絶縁膜８が形成されている。第２絶縁膜８及び電極パッド６の上には、アンダーバリアメタル（ＵＢＭ）の一部であるシード層９及びＵＢＭ層１０が形成されている。ＵＢＭ層１０の上には、半田バンプ１１が形成されている。   As shown in FIG. 1, a first wiring layer 3 composed of a plurality of wirings is formed on a semiconductor substrate 1 having circuit elements 2 such as transistors, and a plurality of first wiring layers composed of a plurality of wirings are formed thereon. Two wiring layers 4 are formed. An electrode pad 6 is formed on the third insulating film 5 formed on the uppermost layer wiring (the uppermost layer wiring and the electrode pad 6 are connected). On the electrode pad 6 including the third insulating film 5, a first insulating film 7 having a first opening is formed so that a part of the electrode pad 6 is exposed. A second insulating film 8 having a second opening is provided on the first insulating film 7 so as to include at least a part of the first opening (exposing at least a part of the first opening). Is formed. On the second insulating film 8 and the electrode pad 6, a seed layer 9 and a UBM layer 10 which are a part of an under barrier metal (UBM) are formed. Solder bumps 11 are formed on the UBM layer 10.

ここで、シード層９及びＵＢＭ層１０からなるＵＢＭは、第２絶縁膜８の表面における第２開口部の外側である第１領域と、電極パッド６の表面における第２開口部の内側である第２領域とで挟まれる第３領域により分離されている。言い換えれば、第２絶縁膜８の第２開口部に形成される段差部（第２開口部における、第２絶縁膜８の表面から電極パッド６に向かう部分）には、ＵＢＭが形成されていない。   Here, the UBM composed of the seed layer 9 and the UBM layer 10 is inside the first region outside the second opening on the surface of the second insulating film 8 and inside the second opening on the surface of the electrode pad 6. It is separated by a third region sandwiched between the second region. In other words, no UBM is formed in the step portion formed in the second opening of the second insulating film 8 (the portion of the second opening that faces the electrode pad 6 from the surface of the second insulating film 8). .

次に、段差部の近傍におけるＵＢＭの構造について図２を参照しながら説明する。   Next, the structure of the UBM in the vicinity of the step portion will be described with reference to FIG.

図２に示すように、第２絶縁膜８の第２開口部の近傍に形成されるＵＢＭ層１０は、第２開口部の縁部１３よりも外側である第１領域と、電極パッド６の表面における第２開口部の縁部１３よりも内側である第２領域に形成されている。一方、第１領域と第２領域とにより挟まれる第３領域においては、ＵＢＭ層１０が形成されていない。このように、第２絶縁膜８の第２開口部に形成される段差部には、ＵＢＭが形成されていない。   As shown in FIG. 2, the UBM layer 10 formed in the vicinity of the second opening of the second insulating film 8 includes a first region outside the edge 13 of the second opening, and the electrode pad 6. It is formed in the 2nd field which is inside the edge 13 of the 2nd opening in the surface. On the other hand, the UBM layer 10 is not formed in the third region sandwiched between the first region and the second region. Thus, the UBM is not formed in the step portion formed in the second opening of the second insulating film 8.

本実施形態に係る半導体装置によると、第２絶縁膜８の段差部にＵＢＭを形成しないことにより、ＵＢＭに段差部が無い構造（応力緩和構造）とすることができ、第２絶縁膜８の段差部において、ＵＢＭに起因する応力集中を緩和することができる効果がある。   According to the semiconductor device according to the present embodiment, by not forming the UBM at the stepped portion of the second insulating film 8, it is possible to obtain a structure (stress relaxation structure) without the stepped portion in the UBM. There is an effect that stress concentration caused by UBM can be relaxed in the stepped portion.

従来は、第３領域においてもＵＢＭを形成していた。言い換えれば、第２開口部の全てを含むようにして、段差部を被覆するようにＵＢＭを形成していた。しかし、従来の構造では、第２絶縁膜８の段差部にＵＢＭからの応力が集中することになる。一方、本実施形態に係る半導体装置によると、第２絶縁膜８の段差部にＵＢＭを形成しないので、ＵＢＭに起因する応力が段差部に集中するのを抑制することが可能となる。   Conventionally, the UBM is also formed in the third region. In other words, the UBM is formed so as to cover the stepped portion so as to include all of the second opening. However, in the conventional structure, the stress from the UBM concentrates on the step portion of the second insulating film 8. On the other hand, according to the semiconductor device according to the present embodiment, since the UBM is not formed in the step portion of the second insulating film 8, it is possible to suppress the stress caused by the UBM from concentrating on the step portion.

なお、第３領域の幅は、５μｍ〜１０μｍ程度であることが好ましい。言い換えれば、ＵＢＭ層１０が形成されていない部分の幅が５μｍ〜１０μｍ程度であることが好ましい。さらに言い換えれば、内側のＵＢＭ層１０と外側のＵＢＭ層１０との間の距離が５μｍ〜１０μｍ程度であることが好ましい。   The width of the third region is preferably about 5 μm to 10 μm. In other words, the width of the portion where the UBM layer 10 is not formed is preferably about 5 μm to 10 μm. Furthermore, in other words, the distance between the inner UBM layer 10 and the outer UBM layer 10 is preferably about 5 μm to 10 μm.

また、ＵＢＭとは、アルミニウム等が形成されている層（第３絶縁膜５が形成される層）と半田バンプ１１との密着性を確保するために形成される。   UBM is formed in order to ensure adhesion between a layer in which aluminum or the like is formed (layer in which the third insulating film 5 is formed) and the solder bump 11.

また、ＵＢＭは、中央部と中央部を囲むリング部とにより構成されることとなるが、半田バンプ１１によって、両者が電気的に接続されていることとなる。   The UBM is composed of a central portion and a ring portion surrounding the central portion, and both are electrically connected by the solder bump 11.

また、本実施形態では、段差部全てにＵＢＭがない構造としている。しかし、部分的には第２絶縁膜８における段差部又は第３領域に、ＵＢＭが形成されていても構わない。段差部における応力集中を緩和できる程度に、段差部にＵＢＭが形成されていれば構わない。   Moreover, in this embodiment, it is set as the structure without UBM in all the level | step-difference parts. However, the UBM may be partially formed in the stepped portion or the third region in the second insulating film 8. It suffices that the UBM is formed in the step portion to such an extent that the stress concentration in the step portion can be relaxed.

また、本実施形態では、パッドの開口部の形状を円形としているが、八角形等の形状としても構わない。   In the present embodiment, the shape of the opening of the pad is circular, but it may be an octagon or the like.

次に、本発明の第１の実施形態に係る半導体装置の製造方法ついて図３〜図６を参照しながら説明する。なお、図３及び図４を用いて、ＵＢＭを形成するまでの製造方法を説明し、図５及び図６を用いて、ＵＢＭの上に半田を形成する方法について説明する。なお、図５及び図６においては、半田めっきを行う方法について説明しているが、半田印刷法等の他の方法を用いても構わない。   Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. A manufacturing method until the UBM is formed will be described with reference to FIGS. 3 and 4, and a method of forming solder on the UBM will be described with reference to FIGS. 5 and 6. 5 and 6, the method for performing solder plating is described, but other methods such as a solder printing method may be used.

まず、図３（ａ）に示すように、半導体基板１にトランジスタ等を構成する回路素子２を形成する。次に、配線層のうち最下層に位置し且つ複数の配線からなる第１配線層３、及びその上に位置する複数の第２配線層４を有する層間絶縁膜を形成する。なお、この層間絶縁膜は、複数の絶縁膜から構成されている。次に、層間絶縁膜の上に第３絶縁膜５を形成し、第３絶縁膜５内に電極パッド６を形成する。次に、電極パッド６及び第３絶縁膜５の上に、第１絶縁膜７を形成し、電極パッド６の一部が露出するような第１開口部を形成する。次に、第１絶縁膜７の上に第２絶縁膜８を形成し、第１開口部の少なくとも一部を含むような第２開口部を形成する。   First, as shown in FIG. 3A, a circuit element 2 constituting a transistor or the like is formed on a semiconductor substrate 1. Next, an interlayer insulating film having a first wiring layer 3 that is located in the lowermost layer of the wiring layers and includes a plurality of wirings, and a plurality of second wiring layers 4 that are located thereon is formed. The interlayer insulating film is composed of a plurality of insulating films. Next, a third insulating film 5 is formed on the interlayer insulating film, and an electrode pad 6 is formed in the third insulating film 5. Next, a first insulating film 7 is formed on the electrode pad 6 and the third insulating film 5, and a first opening is formed so that a part of the electrode pad 6 is exposed. Next, a second insulating film 8 is formed on the first insulating film 7, and a second opening including at least a part of the first opening is formed.

ここで、第１絶縁膜７は、窒化シリコン（ＳｉＮｘ）、窒素含有酸化シリコン（ＳｉＯＮ）又は酸化シリコン（ＳｉＯ２）からなる無機材料膜等により形成され、例えば０．５μｍ〜１μｍ程度の厚さとなるように形成することが好ましい。また、第２絶縁膜８は、ポリイミド、ベンゾシクロブテン（ＢＣＢ）又はフッ素樹脂からなる有機材料膜等により形成され、例えば３μｍ〜１０μｍ程度の厚さとなるように形成することが好ましい。有機絶縁膜のような柔らかい膜を使用することにより、後の工程において形成される半田バンプの横方向の応力を抑制すると共に、縦方向の応力も緩和できる構造となる。また、第２開口部の開口径は、第１開口部の開口径よりも小さいことが好ましい。第２開口部が形成される第２絶縁膜８の上には、ＵＢＭを介して半田バンプが形成されることとなる。その際の応力緩和の効果を鑑みると、第２開口部の開口径は、第１開口部の開口径よりも小さいことが好ましく、例えば、６０μｍ程度であることが好ましい。 Here, the first insulating film 7 is formed of an inorganic material film made of silicon nitride (SiN x ), nitrogen-containing silicon oxide (SiON), or silicon oxide (SiO 2 ), and has a thickness of about 0.5 μm to 1 μm, for example. It is preferable to form such that The second insulating film 8 is formed of an organic material film made of polyimide, benzocyclobutene (BCB), or a fluororesin, and preferably has a thickness of about 3 μm to 10 μm, for example. By using a soft film such as an organic insulating film, it is possible to suppress the stress in the lateral direction of the solder bump formed in a later process and to relax the stress in the vertical direction. Moreover, it is preferable that the opening diameter of a 2nd opening part is smaller than the opening diameter of a 1st opening part. On the second insulating film 8 where the second opening is formed, solder bumps are formed via the UBM. In view of the effect of stress relaxation at that time, the opening diameter of the second opening is preferably smaller than the opening diameter of the first opening, for example, about 60 μm.

次に、図３（ｂ）に示すように、第２開口部を含む第２絶縁膜８の上の全面に、シード層９を形成する。その後、ＵＢＭを形成する領域がパターニングされたレジスト膜１２を形成する。   Next, as shown in FIG. 3B, a seed layer 9 is formed on the entire surface of the second insulating film 8 including the second opening. Thereafter, a resist film 12 in which a region for forming the UBM is patterned is formed.

次に、図３（ｃ）に示すように、電解めっき法を用いることによって、例えばニッケル（Ｎｉ）等によりシード層９の上にＵＢＭ層１０を形成する。なお、ＵＢＭ層１０の最上面には金（Ａｕ）等がめっきされる。   Next, as shown in FIG. 3C, the UBM layer 10 is formed on the seed layer 9 by using, for example, nickel (Ni) by using an electrolytic plating method. Note that gold (Au) or the like is plated on the uppermost surface of the UBM layer 10.

次に、図４（ａ）に示すように、レジスト膜１２を除去する。   Next, as shown in FIG. 4A, the resist film 12 is removed.

次に、半田バンプを形成するが、ここでは、半田ボールの搭載又は半田印刷法によりＵＢＭの上に半田バンプを形成する方法について説明する。図４（ｂ）に示すように、形成されたＵＢＭ層１０をマスクとして用い、ＵＢＭ層１０が形成されていない部分に存在するシード層９を除去する。その後、半田ボールの搭載又は半田印刷法によりＵＢＭの上に半田バンプを形成する（図示せず）。このようにして、本実施形態に係る半導体装置を形成することができる。   Next, solder bumps are formed. Here, a method for forming solder bumps on the UBM by mounting solder balls or by solder printing will be described. As shown in FIG. 4B, the formed UBM layer 10 is used as a mask, and the seed layer 9 existing in the portion where the UBM layer 10 is not formed is removed. Thereafter, solder bumps are formed on the UBM by solder ball mounting or solder printing (not shown). In this way, the semiconductor device according to this embodiment can be formed.

また、半田めっき法によって半田バンプを形成する方法について、図５及び図６を参照しながら説明する。   A method for forming solder bumps by solder plating will be described with reference to FIGS.

図４（ａ）のような状態の半導体装置の上に、図５（ａ）に示すように、レジスト膜１２を形成する。ここで、ＵＢＭ層１０が形成されている部分にはレジストが形成されないようにパターニングされたレジスト膜１２を用意する。又は、図３（ｂ）において形成するレジスト膜１２の厚さを厚くすることにより、図５（ａ）のようなレジスト膜１２を用意しても構わない。   As shown in FIG. 5A, a resist film 12 is formed on the semiconductor device in the state as shown in FIG. Here, a resist film 12 patterned so that a resist is not formed on the portion where the UBM layer 10 is formed is prepared. Alternatively, the resist film 12 as shown in FIG. 5A may be prepared by increasing the thickness of the resist film 12 formed in FIG.

次に、図５（ｂ）に示すように、めっき法を用いて、ＵＢＭ層１０の上に半田めっき膜１１Ａを形成する。   Next, as shown in FIG. 5B, a solder plating film 11A is formed on the UBM layer 10 by using a plating method.

次に、図６（ａ）に示すように、レジスト膜１２を除去する。その後、形成されているＵＢＭ層１０をマスクとして使用して、ＵＢＭ層１０が形成されていない部分に存在するシード層９を除去する。   Next, as shown in FIG. 6A, the resist film 12 is removed. Thereafter, the formed UBM layer 10 is used as a mask to remove the seed layer 9 existing in a portion where the UBM layer 10 is not formed.

次に、図６（ｂ）に示すように、リフローを行うことにより、ボール形状の半田バンプ１１がＵＢＭの上に形成されることとなる。ここで、ＵＢＭの厚さは５μｍ〜１０μｍ程度となり、半田バンプ１１を上から見た径は、８０μｍ〜１００μｍ程度となる。   Next, as shown in FIG. 6B, by performing reflow, the ball-shaped solder bumps 11 are formed on the UBM. Here, the thickness of the UBM is about 5 μm to 10 μm, and the diameter of the solder bump 11 viewed from above is about 80 μm to 100 μm.

（第１の実施形態の第１の変形例）
本発明の第１の実施形態の第１の変形例に係る半導体装置ついて図７を参照しながら説明する。 (First modification of the first embodiment)
A semiconductor device according to a first modification of the first embodiment of the present invention will be described with reference to FIG.

第１の実施形態においては、図１に示すように、半田バンプ１１が第３領域にも埋め込まれる構造を説明した。しかしながら、本変形例においては、図７に示すように、半田バンプ１１が第３領域において埋め込まれない構造としても構わない。他の言い方をすると、半田バンプと第２絶縁膜８又は電極パッド６との間に空隙を形成していても構わない。   In the first embodiment, as shown in FIG. 1, the structure in which the solder bumps 11 are embedded in the third region has been described. However, in this modification, as shown in FIG. 7, a structure in which the solder bumps 11 are not embedded in the third region may be used. In other words, a gap may be formed between the solder bump and the second insulating film 8 or the electrode pad 6.

本変形例によると、半田バンプ１１と第２絶縁膜８又は電極パッド６との間に空隙を形成する構造とすることによって、より応力を緩和する構造とすることができる効果がある。   According to the present modification, by forming a gap between the solder bump 11 and the second insulating film 8 or the electrode pad 6, there is an effect that the structure can further reduce the stress.

（第１の実施形態の第２の変形例）
本発明の第１の実施形態の第２の変形例に係る半導体装置ついて図８及び図９を参照しながら説明する。なお、図９は半田バンプ１１を省略している。 (Second modification of the first embodiment)
A semiconductor device according to a second modification of the first embodiment of the present invention will be described with reference to FIGS. In FIG. 9, the solder bumps 11 are omitted.

第１の実施形態においては、図１及び図２に示すように、第１絶縁膜７に形成される第１開口部に、第２絶縁膜８に形成される第２開口部が完全に含まれていた。言い換えれば、第２開口部の内側には第１絶縁膜７は形成されていなかった。しかし、図８に示すように、第１絶縁膜７に形成される第１開口部の全てが、第２絶縁膜８に形成される第２開口部の内側に配置されるようにしても構わない。言い換えれば、第２開口部の内側にまで第１絶縁膜７が形成されるようにしても構わない。   In the first embodiment, as shown in FIGS. 1 and 2, the first opening formed in the first insulating film 7 completely includes the second opening formed in the second insulating film 8. It was. In other words, the first insulating film 7 was not formed inside the second opening. However, as shown in FIG. 8, all of the first openings formed in the first insulating film 7 may be disposed inside the second openings formed in the second insulating film 8. Absent. In other words, the first insulating film 7 may be formed even inside the second opening.

上記構成とすると、図９に示すように、ＵＢＭの中央部とその周囲を取り囲むように形成されるリング形状部との間に、第１絶縁膜７と第２絶縁膜８とが積層されて配置されることとなる。   With the above configuration, as shown in FIG. 9, the first insulating film 7 and the second insulating film 8 are laminated between the central portion of the UBM and the ring-shaped portion formed so as to surround the periphery thereof. Will be placed.

第１の実施形態においては、ＵＢＭをめっきした後の工程において、ＵＢＭが形成されていない領域に存在するシード層９の直下に電極パッド６が形成されていることがある。このシード層９を除去する際に、シード層９の直下の電極パッド６もエッチングされてしまう可能性がある。それに対して、本変形例においては、ＵＢＭの中央部とその周囲を取り囲むように形成されるリング形上部との間に、第１絶縁膜７と第２絶縁膜８とが積層されて配置されることとなる。そのため、ＵＢＭをめっきした後の工程において、ＵＢＭが形成されていない領域に存在するシード層９の直下には、第１絶縁膜７又は第２絶縁膜８が形成されることとなる。そのため、シード層９をエッチングする際に、電極パッド６のエッチングを抑制することができ、安定したプロセスとすることができる効果がある。   In the first embodiment, in the step after plating the UBM, the electrode pad 6 may be formed immediately below the seed layer 9 existing in the region where the UBM is not formed. When the seed layer 9 is removed, the electrode pad 6 immediately below the seed layer 9 may also be etched. On the other hand, in this modification, the first insulating film 7 and the second insulating film 8 are laminated and disposed between the central portion of the UBM and the ring-shaped upper portion formed so as to surround the periphery. The Rukoto. Therefore, in the process after plating the UBM, the first insulating film 7 or the second insulating film 8 is formed immediately below the seed layer 9 existing in the region where the UBM is not formed. Therefore, when the seed layer 9 is etched, the etching of the electrode pad 6 can be suppressed, and there is an effect that a stable process can be achieved.

（第１の実施形態の第３の変形例）
本発明の第１の実施形態の第３の変形例に係る半導体装置ついて図１０を参照しながら説明する。なお、図１０は半田バンプ１１を省略している。 (Third Modification of First Embodiment)
A semiconductor device according to a third modification of the first embodiment of the present invention will be described with reference to FIG. In FIG. 10, the solder bumps 11 are omitted.

第１の実施形態においては、図２に示すように、ＵＢＭ層１０の中央部の周囲を取り囲むように形成されるリング形状部は、中央部を連続的に取り囲むように形成されていた。しかし、本変形例に係る半導体装置においては、図１０に示すように、ＵＢＭ層１０におけるリング形状部は、中央部を不連続に取り囲むように形成されている。他の言い方をすれば、第２絶縁膜８の上の、第２開口部の外側である第１領域において、ＵＢＭは、複数に分割されて形成されている。このように、ＵＢＭにおけるリング形状部を複数に分割することによって、ＵＢＭによる応力をさらに緩和することができる効果がある。   In the first embodiment, as shown in FIG. 2, the ring-shaped portion formed so as to surround the central portion of the UBM layer 10 is formed so as to continuously surround the central portion. However, in the semiconductor device according to this modification, as shown in FIG. 10, the ring-shaped portion in the UBM layer 10 is formed so as to discontinuously surround the central portion. In other words, the UBM is divided into a plurality of parts in the first region on the second insulating film 8 and outside the second opening. Thus, there is an effect that the stress caused by the UBM can be further relaxed by dividing the ring-shaped portion of the UBM into a plurality of parts.

なお、図１０においては、ＵＢＭにおけるリング形状部を４分割した形状を示しているが、分割数を多くしても、少なくしても構わない。   In FIG. 10, the ring shape portion in the UBM is divided into four parts, but the number of divisions may be increased or decreased.

（第１の実施形態の第４の変形例）
本発明の第１の実施形態の第４の変形例に係る半導体装置ついて図１１を参照しながら説明する。なお、図１１は半田バンプ１１を省略している。 (Fourth modification of the first embodiment)
A semiconductor device according to a fourth modification of the first embodiment of the present invention will be described with reference to FIG. In FIG. 11, the solder bumps 11 are omitted.

図１１に示すように、本変形例は、第１の実施形態の第３の変形例と比較して、ＵＢＭ層１０の中央部がさらに複数に分割されて形成されている。他の言い方をすれば、電極パッド６の上の第２開口部の内側である第２領域において、ＵＢＭは、複数に分割されて形成されている。このように、ＵＢＭにおける内側部分を複数に分割することによって、ＵＢＭによる応力をさらに緩和することができる効果がある。   As shown in FIG. 11, in the present modification, the central portion of the UBM layer 10 is further divided into a plurality of parts, as compared with the third modification of the first embodiment. In other words, the UBM is divided into a plurality of parts in the second region inside the second opening on the electrode pad 6. Thus, there is an effect that the stress caused by the UBM can be further relaxed by dividing the inner portion of the UBM into a plurality of parts.

なお、図１１においては、ＵＢＭにおける内側部を４分割した形状を示しているが、分割数を多くしても、少なくしても構わない。   In addition, in FIG. 11, although the shape which divided the inner part in UBM into 4 is shown, you may increase or decrease the number of divisions.

（第２の実施形態）
本発明の第２の実施形態について図１２及び図１３を参照しながら説明する。 (Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS.

図１２に示すように、本実施形態では、第１の実施形態と比較して、第２絶縁膜８の段差部に形成されるＵＢＭに違いがある。具体的には、第１の実施形態に係る半導体装置の第２絶縁膜８は、第２開口部における、電極パッド６から第２絶縁膜８の表面に向かう部分の電極パッド６の表面に対する傾斜角が９０度である。一方、本実施形態では、図１２に示すように、電極パッド６から第２絶縁膜８の表面に向かう部分がゆるやかな傾斜となっており、第２絶縁膜８はゆるやかな段差部を有している。電極パッド６の表面に対する段差部の傾斜角が４５度以下となっている。また、シード層９及びＵＢＭ層１０からなるＵＢＭが、この傾斜部を含む第２絶縁膜８の上及び電極パッド６の上に、連続的に形成されている。   As shown in FIG. 12, the present embodiment is different from the first embodiment in the UBM formed in the step portion of the second insulating film 8. Specifically, the second insulating film 8 of the semiconductor device according to the first embodiment is inclined with respect to the surface of the electrode pad 6 at a portion of the second opening from the electrode pad 6 toward the surface of the second insulating film 8. The angle is 90 degrees. On the other hand, in the present embodiment, as shown in FIG. 12, the portion from the electrode pad 6 toward the surface of the second insulating film 8 has a gentle slope, and the second insulating film 8 has a gentle step portion. ing. The inclination angle of the step with respect to the surface of the electrode pad 6 is 45 degrees or less. Further, a UBM composed of the seed layer 9 and the UBM layer 10 is continuously formed on the second insulating film 8 and the electrode pad 6 including the inclined portion.

本実施形態に係る半導体装置によると、第２絶縁膜８の段差部がゆるやかな構造となっているために、ＵＢＭが段差部に形成されたとしてもＵＢＭに大きな段差が生じることが無くなる。そのため、段差部への応力集中を低減することができ、ＵＢＭに起因する応力集中を抑制することができる効果がある。   According to the semiconductor device according to the present embodiment, since the step portion of the second insulating film 8 has a gradual structure, even if the UBM is formed in the step portion, a large step does not occur in the UBM. Therefore, the stress concentration on the step portion can be reduced, and the stress concentration due to the UBM can be suppressed.

図１３は、段差部の傾斜角（電極パッド６の表面に対する段差部の傾斜角）を横軸に取り、それぞれの傾斜角に応じた、第２開口部の近傍に加わる応力（相対値）を縦軸に取ったグラフである。図１３に示すように、段差部の傾斜角が４５度を超えると、第２開口部の近傍に加わる応力が急激に増大する。従って、ＵＢＭに起因する応力集中を抑制するためにも、傾斜角を４５度以下とすることが好ましい。   FIG. 13 shows the inclination angle of the step portion (inclination angle of the step portion with respect to the surface of the electrode pad 6) on the horizontal axis, and shows the stress (relative value) applied to the vicinity of the second opening according to each inclination angle. It is the graph taken on the vertical axis. As shown in FIG. 13, when the inclination angle of the stepped portion exceeds 45 degrees, the stress applied in the vicinity of the second opening portion rapidly increases. Therefore, in order to suppress stress concentration caused by UBM, it is preferable to set the inclination angle to 45 degrees or less.

（第３の実施形態）
本発明の第３の実施形態について図１４を参照しながら説明する。 (Third embodiment)
A third embodiment of the present invention will be described with reference to FIG.

図１４に示すように、本実施形態では、第２の実施形態と比較して、第１絶縁膜７が、第２開口部の内側にまで形成されている点が異なる。そのため、シード層９及びＵＢＭ層１０からなるＵＢＭが、第２開口部の内側の第１絶縁膜７の上にまで形成されている。このような形態とすることにより、第２絶縁膜８の表面から電極パッド６に向かって（第１絶縁膜７における第２開口部の内側部分に向かって）、第１段差部が形成されることに加えて、第１絶縁膜７における第２開口部の内側部分に電極パッド６方向に向かう第２段差部が形成され、第１絶縁膜７における第１開口部の内側部分に電極パッド６方向に向かう第３段差部が形成されることとなる。また、第１段差部、第２段差部及び第３段差部を含む第１絶縁膜７、第２絶縁膜８及び電極パッド６の上の全体にＵＢＭが形成されることとなる。   As shown in FIG. 14, the present embodiment is different from the second embodiment in that the first insulating film 7 is formed even inside the second opening. Therefore, the UBM composed of the seed layer 9 and the UBM layer 10 is formed even on the first insulating film 7 inside the second opening. With this configuration, the first step portion is formed from the surface of the second insulating film 8 toward the electrode pad 6 (toward the inner portion of the second opening in the first insulating film 7). In addition, a second stepped portion is formed in the inner portion of the first opening in the first insulating film 7 in the direction of the electrode pad 6, and the electrode pad 6 is formed in the inner portion of the first opening in the first insulating film 7. The 3rd level | step-difference part which goes to a direction will be formed. Further, the UBM is formed over the first insulating film 7, the second insulating film 8, and the electrode pad 6 including the first step portion, the second step portion, and the third step portion.

本実施形態においては、第１絶縁膜７が第２絶縁膜８よりも薄いために、第１絶縁膜７における第２段差部又は第３段差部が、第２絶縁膜８における第１段差部よりも急な角度であったとしても、第１段差部がゆるやかであるならば、第２開口部の近傍に加わる応力集中を抑制することが可能となる。   In the present embodiment, since the first insulating film 7 is thinner than the second insulating film 8, the second step portion or the third step portion in the first insulating film 7 is the first step portion in the second insulating film 8. Even if the angle is steeper than that, if the first step portion is gentle, the stress concentration applied to the vicinity of the second opening can be suppressed.

なお、第１段差部の電極パッド６の表面に対する第１傾斜角と、第２段差部の電極パッド６の表面に対する第２傾斜角と、第３段差部の電極パッド６の表面に対する第３傾斜角との平均傾斜角が４５度以下であることが好ましい。このように、第２開口部の近傍において複数の段差部を有する場合においても、段差部の傾斜角の平均傾斜角を４５度以下とすることにより、第２開口部の近傍に加わる応力集中をより抑制することが可能となる。   In addition, the 1st inclination angle with respect to the surface of the electrode pad 6 of a 1st step part, the 2nd inclination angle with respect to the surface of the electrode pad 6 of a 2nd step part, and the 3rd inclination with respect to the surface of the electrode pad 6 of a 3rd step part It is preferable that the average inclination angle with respect to the angle is 45 degrees or less. Thus, even when there are a plurality of step portions in the vicinity of the second opening, the stress concentration applied to the vicinity of the second opening can be reduced by setting the average inclination angle of the step portion to 45 degrees or less. It becomes possible to suppress more.

（第４の実施形態）
本発明の第４の実施形態について図１５を参照しながら説明する。 (Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG.

図１５に示すように、本実施形態では、第３の実施形態と比較して、第２開口部の開口径が大きく形成されている。そのため、シード層９及びＵＢＭ層１０からなるＵＢＭは、第２絶縁膜８の上には形成されず、第２絶縁膜８よりも薄い第１絶縁膜７及び電極パッド６の上にのみ形成されることとなる。第１絶縁膜７は、第３の実施形態と同様に複数の段差部を有しているが、第２絶縁膜８よりも十分に薄いために、ＵＢＭに起因する応力集中を十分に緩和することが可能となる。   As shown in FIG. 15, in this embodiment, the opening diameter of the second opening is formed larger than that of the third embodiment. Therefore, the UBM composed of the seed layer 9 and the UBM layer 10 is not formed on the second insulating film 8 but is formed only on the first insulating film 7 and the electrode pad 6 that are thinner than the second insulating film 8. The Rukoto. The first insulating film 7 has a plurality of stepped portions as in the third embodiment, but is sufficiently thinner than the second insulating film 8, and therefore sufficiently reduces stress concentration caused by UBM. It becomes possible.

また、本実施形態においては、第１絶縁膜７に形成される複数の段差部の電極パッド６の表面に対する角度の平均値を４５度以下とすることが好ましい。   In the present embodiment, it is preferable that the average value of the angles of the plurality of step portions formed in the first insulating film 7 with respect to the surface of the electrode pad 6 is 45 degrees or less.

本発明に係る半導体装置は、電極パッドの上に形成されるＵＢＭに起因する応力集中を十分に緩和することができるため、半導体装置に形成されたトランジスタの特性変動を抑制することができ、特に、半田バンプの下に形成されるＵＢＭを備える半導体装置等に有用である。   Since the semiconductor device according to the present invention can sufficiently relieve stress concentration caused by the UBM formed on the electrode pad, the characteristic variation of the transistor formed in the semiconductor device can be suppressed. This is useful for a semiconductor device including a UBM formed under a solder bump.

１ 半導体基板
２ 回路素子
３ 第１配線層
４ 第２配線層
５ 第３絶縁膜
６ 電極パッド
７ 第１絶縁膜
８ 第２絶縁膜
９ シード層（アンダーバリアメタルの一部）
１０ アンダーバリアメタル（ＵＢＭ）層
１１Ａ 半田めっき膜
１１ 半田バンプ
１２ レジスト膜
１３ 第２開口部の縁部 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Circuit element 3 1st wiring layer 4 2nd wiring layer 5 3rd insulating film 6 Electrode pad 7 1st insulating film 8 2nd insulating film 9 Seed layer (a part of under barrier metal)
10 Under barrier metal (UBM) layer 11A Solder plating film 11 Solder bump 12 Resist film 13 Edge of second opening

Claims (14)

基板の上に形成された電極パッドと、
前記電極パッドの上に形成され、且つ、前記電極パッドの一部が露出するような第１開口部を有する第１絶縁膜と、
前記第１絶縁膜の上に形成され、且つ、前記第１開口部における少なくとも一部が露出するような第２開口部を有する第２絶縁膜と、
前記第２絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、
前記アンダーバリアメタルは、前記第２絶縁膜の表面における前記第２開口部の外側である第１領域と前記電極パッドの表面における前記第２開口部の内側である第２領域とにより挟まれる第３領域によって分離されていることを特徴とする半導体装置。 An electrode pad formed on the substrate;
A first insulating film formed on the electrode pad and having a first opening that exposes a portion of the electrode pad;
A second insulating film formed on the first insulating film and having a second opening such that at least a part of the first opening is exposed;
An under barrier metal formed on the second insulating film and the electrode pad,
The under barrier metal is sandwiched between a first region outside the second opening on the surface of the second insulating film and a second region inside the second opening on the surface of the electrode pad. A semiconductor device characterized by being separated by three regions. 前記アンダーバリアメタルの上に半田バンプが形成されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein solder bumps are formed on the under barrier metal. 前記第３領域において、前記半田バンプは、前記第２絶縁膜又は電極パッドとの間に空隙を形成することを特徴とする請求項２に記載の半導体装置。   3. The semiconductor device according to claim 2, wherein in the third region, the solder bump forms a gap between the second insulating film and the electrode pad. 前記第２領域において、前記アンダーバリアメタルは、前記第１絶縁膜と接触していることを特徴とする請求項１〜３のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the under barrier metal is in contact with the first insulating film in the second region. 前記第１領域において、前記アンダーバリアメタルは、複数に分割されていることを特徴とする請求項１〜４のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the under barrier metal is divided into a plurality of parts in the first region. 前記第２領域において、前記アンダーバリアメタルは、複数に分割されていることを特徴とする請求項１〜５のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the under barrier metal is divided into a plurality of parts in the second region. 基板の上に形成された電極パッドと、
前記電極パッドの上に形成され、且つ、前記電極パッドの一部が露出するような第１開口部を有する第１絶縁膜と、
前記第１絶縁膜の上に形成され、且つ、前記第１開口部における少なくとも一部が露出するような第２開口部を有する第２絶縁膜と、
前記第２絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、
前記第２絶縁膜は、前記第２絶縁膜の表面から前記電極パッドに向かう傾斜部を有し、
前記傾斜部における前記基板の平面方向に対する傾斜角は４５度以下であることを特徴とする半導体装置。 An electrode pad formed on the substrate;
A first insulating film formed on the electrode pad and having a first opening that exposes a portion of the electrode pad;
A second insulating film formed on the first insulating film and having a second opening such that at least a part of the first opening is exposed;
An under barrier metal formed on the second insulating film and the electrode pad,
The second insulating film has an inclined portion from the surface of the second insulating film toward the electrode pad,
A tilt angle of the tilted portion with respect to a planar direction of the substrate is 45 degrees or less. 前記第１絶縁膜は、複数の段差を有し、
前記アンダーバリアメタルは、前記複数の段差を含む前記第１絶縁膜の上にも形成されることを特徴とする請求項７記載の半導体装置。 The first insulating film has a plurality of steps.
The semiconductor device according to claim 7, wherein the under barrier metal is also formed on the first insulating film including the plurality of steps. 前記傾斜部及び複数の段差における前記基板の平面方向に対する傾斜角の平均値は、４５度以下であることを特徴とする請求項８に記載の半導体装置。   The semiconductor device according to claim 8, wherein an average value of an inclination angle with respect to a planar direction of the substrate at the inclined portion and the plurality of steps is 45 degrees or less. 基板の上に形成された電極パッドと、
前記電極パッドの上に形成され、且つ、前記電極パッドの一部が露出するような第１開口部を有する第１絶縁膜と、
前記第１絶縁膜の上に形成され、且つ、前記第１開口部における少なくとも一部が露出するような第２開口部を有する第２絶縁膜と、
前記第１絶縁膜及び電極パッドの上に形成されたアンダーバリアメタルとを備え、
前記第１絶縁膜は、複数の段差を有し、
前記アンダーバリアメタルは、前記複数の段差を含む前記第１絶縁膜の上に形成されることを特徴とする半導体装置。 An electrode pad formed on the substrate;
A first insulating film formed on the electrode pad and having a first opening that exposes a portion of the electrode pad;
A second insulating film formed on the first insulating film and having a second opening such that at least a part of the first opening is exposed;
An under barrier metal formed on the first insulating film and the electrode pad,
The first insulating film has a plurality of steps.
The under barrier metal is formed on the first insulating film including the plurality of steps. 前記複数の段差における前記基板の平面方向に対する傾斜角の平均値は、４５度以下であることを特徴とする請求項１０に記載の半導体装置。   The semiconductor device according to claim 10, wherein an average value of inclination angles with respect to a planar direction of the substrate at the plurality of steps is 45 degrees or less. 前記アンダーバリアメタルの上に半田バンプが形成されていることを特徴とする請求項７〜１１のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 7, wherein solder bumps are formed on the under barrier metal. 前記第１絶縁膜は、窒化シリコン、窒素含有酸化シリコン又は酸化シリコンからなる無機材料膜を含むことを特徴とする請求項１〜１２のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first insulating film includes an inorganic material film made of silicon nitride, nitrogen-containing silicon oxide, or silicon oxide. 前記第２絶縁膜は、ポリイミド、ベンゾシクロブテン又はフッ素樹脂からなる有機材料膜を含むことを特徴とする請求項１〜１３のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the second insulating film includes an organic material film made of polyimide, benzocyclobutene, or a fluororesin.
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