JP2013016599A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of removing foreign matter adhering to an upper surface of a wafer, without involving increase in manufacturing costs.SOLUTION: According to an embodiment, there is provided a method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device comprises a contraction layer forming step, a crack forming step, and a removing step. In the contraction layer forming step, a contraction layer having a contraction rate higher than those of materials forming the semiconductor device is formed on an upper surface of the wafer on which the materials forming the semiconductor device are stacked. In the crack forming step, a crack is formed in the contraction layer by letting the contraction layer to contract. In the removing step, the contraction layer, in which the crack has been formed, is removed from the upper surface of the wafer.

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  Conventionally, a semiconductor device has been manufactured by laminating a plurality of constituent materials that have been subjected to fine patterning, and when a foreign object adheres to the upper surface of a wafer that is in the process of being laminated, the semiconductor device does not operate normally. there is a possibility.

  Such foreign matter includes foreign matter simply accumulated on the upper surface of the wafer and foreign matter fixed on the upper surface of the wafer. Among these, the foreign matter accumulated on the upper surface of the wafer was removed by cleaning with a chemical solution or air blowing.

  On the other hand, foreign substances fixed on the upper surface of the wafer are difficult to remove sufficiently with chemicals or air blow. For example, a resist is applied to the upper surface of the wafer and cured, and adhesive tape or the like is applied to the resist for peeling. The entire resist was removed by an apparatus that performs the process.

  However, separately providing a device for attaching and peeling an adhesive tape or the like in order to remove the foreign matter adhered to the upper surface of the wafer has a problem that the manufacturing cost increases.

Japanese Patent Laid-Open No. 7-74137

  An object of one embodiment of the present invention is to provide a method of manufacturing a semiconductor device capable of removing foreign matters fixed on the upper surface of a wafer without increasing the manufacturing cost.

  According to the embodiment, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes a shrinkage layer forming step, a crack forming step, and a removing step. In the contraction layer forming step, a contraction layer having a contraction rate higher than that of the constituent material is formed on the upper surface of the wafer on which the constituent materials of the semiconductor device are stacked. In the crack forming step, the contraction layer is contracted to form a crack in the contraction layer. In the removing step, the shrink layer in which the crack is formed is removed from the upper surface of the wafer.

FIG. 5 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a schematic plan view showing a manufacturing process of the semiconductor device according to the first embodiment. 1 is a block diagram showing a semiconductor device manufacturing system according to a first embodiment. The cross-sectional schematic diagram which shows the shrinkage | contraction aspect of the shrinkable layer which concerns on 2nd Embodiment. The cross-sectional schematic diagram which shows the contraction aspect of the contraction layer which concerns on 3rd Embodiment. Sectional schematic diagram which shows the manufacturing process of the semiconductor device which concerns on 4th Embodiment.

  A semiconductor device manufacturing method and a semiconductor device manufacturing system according to embodiments will be described below in detail with reference to the accompanying drawings. In addition, this invention is not limited by embodiment shown below.

  In the following, the material stacked on the semiconductor substrate and finally left on the semiconductor substrate as a component of the semiconductor device is referred to as a constituent material, and a structure in which the constituent materials are sequentially stacked on the semiconductor substrate is referred to as a wafer. Called. In the following, a manufacturing process for removing foreign matter that has adhered to the upper surface of a wafer during manufacturing of a semiconductor device will be described.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment, and FIG. 2 is a schematic plan view showing the manufacturing process of the semiconductor device according to the first embodiment.

  As shown in FIG. 1A, when a semiconductor device is manufactured, foreign matter 5 may adhere to the upper surface of the wafer 1 during the manufacturing process. For example, when the silicon layer 3 and the metal wiring layer 4 which are constituent materials of the semiconductor device are sequentially laminated on the upper surface of the semiconductor substrate 2, foreign matter 5 such as silicon fine particles generated when the silicon layer 3 is laminated is metal wiring. During the formation of the layer 4, it may adhere to the upper surface of the metal wiring layer 4.

  At this time, the foreign material 5 may be covered with a metal film such as copper, which is a material of the metal wiring layer 4, and may adhere to the upper surface of the wafer 1. As described above, the foreign matter 5 adhered to the upper surface of the wafer 1 is difficult to remove by cleaning with a chemical solution or air blowing.

  Therefore, in the present embodiment, when the foreign matter 5 is fixed on the upper surface of the wafer 1 in the process of manufacturing the semiconductor device (see FIG. 1A), as shown in FIG. A contraction layer forming step for forming a contraction layer 6 having a contraction rate higher than that of the constituent material (here, the metal wiring layer 4) constituting the uppermost layer of the wafer 1 is performed.

  In the shrink layer forming process, for example, a shrink layer 6 is formed on the wafer 1 by spin coating in which a resist such as a photosensitive polymer used in a general lithography process is applied and the wafer 1 is rotated.

  Thus, in this embodiment, the shrinkable layer 6 can be formed by an existing apparatus that performs spin coating using a resist material used in the lithography process. For this reason, according to this embodiment, since it is not necessary to prepare a special material and apparatus separately in order to form the contraction layer 6, the contraction layer 6 can be formed without increasing manufacturing cost.

  At this time, the contraction layer 6 is formed so as to enclose the foreign material 5. Here, as the material of the shrink layer 6, for example, a material having light shrinkage and translucency (light transmission) that shrink and harden as the intensity of irradiated light is higher is used.

  Note that in the contraction layer forming step, the contraction layer can be formed of a resist having semi-translucency. This point will be described later with reference to FIG. In the contraction layer forming step, the contraction layer can be formed of a resist having a heat shrinkability that contracts and hardens when heat is applied. This point will be described later with reference to FIG.

  The shrink layer 6 is not limited to a resist, and may be formed of any material having a higher shrinkage than the constituent material provided on the surface of the wafer 1. For example, the shrink layer 6 may be formed of a polymer or the like having a drying shrinkage that shrinks by heat treatment or freeze-drying treatment.

  Although the case where the single shrink layer 6 is formed will be described here, a multiple shrink layer can be formed in the shrink layer forming step. This will be described later with reference to FIG.

  Then, in this embodiment, as shown in FIG.1 (c), the crack formation process which shrinks and hardens the contraction layer 6 and forms the crack 7 in the contraction layer 6 is performed. Specifically, in the crack formation step, the shrink layer 6 is shrunk and cured by irradiating the upper surface of the shrink layer 6 with light.

  In such a crack forming process, a resist curing device used in the lithography process is used. Thereby, in this embodiment, since it is not necessary to prepare a special apparatus separately in order to perform a crack formation process, the crack 7 can be formed in the contraction layer 6 without increasing manufacturing cost.

  Here, the shrinkage layer 6 has a higher optical shrinkage rate than the metal wiring layer 4 constituting the upper surface of the wafer 1 as described above. For this reason, as shown in FIG. 2, cracks 7 are formed in the entire shrinkage layer 6.

  In this crack formation step, as shown in FIG. 1C, light irradiation is performed until a crack 7 reaching from the upper surface to the lower surface of the shrink layer 6 is formed. At this time, each piece of the contraction layer 6 divided by the crack 7 is curved so as to protrude downward, and the peripheral edge is peeled off from the surface of the metal wiring layer 4.

  Thereby, the metal film covering the foreign material 5 is separated from the surface of the metal wiring layer 4 by the shrinkage force and the peeling force of the shrinkage layer 6. At this time, even if each piece of the contraction layer 6 is curved so as to protrude upward, the metal film covering the foreign material 5 is formed on the metal wiring layer 4 by the contraction force and peeling force of the contraction layer 6. Separated from the surface.

  Subsequently, in the present embodiment, as shown in FIG. 1D, a removal step of removing the foreign material 5 from the wafer 1 together with the shrink layer 6 by peeling the shrink layer 6 using a resist peeling device used in the lithography process. Do.

  At this time, the metal film covering the foreign material 5 is already separated from the metal wiring layer 4 by the above-described crack formation process. Therefore, the shrink layer 6 is easily removed together with the foreign matter 5 by an existing resist stripping apparatus.

  In addition, as the resist stripping apparatus, the resist formed in the lithography process is cleaned and removed by a predetermined chemical solution, the resist is removed by air blow, the resist is heated and burned to be converted into an inorganic compound (ashed), and removed. An ashing device or the like is used.

  Thus, in this embodiment, the foreign material 5 can be removed from the wafer 1 together with the shrink layer 6 using an existing resist stripping apparatus used in the lithography process. Therefore, according to the present embodiment, it is not necessary to separately prepare a special chemical or apparatus in order to remove the shrinkable layer 6 and the foreign matter 5, so that the foreign matter 5 is removed from the wafer 1 without increasing the manufacturing cost. be able to.

  In the present embodiment, the silicon layer 3 and the metal wiring layer 4 are exemplified as the constituent materials of the semiconductor device, but the constituent materials are not limited to these. That is, the constituent material of the semiconductor device may be any material used for manufacturing the semiconductor device, such as a silicon oxide film, a silicon nitride film, and gold, copper, titanium, tungsten, and aluminum used for the wiring material. .

  Next, the semiconductor device manufacturing system according to the present embodiment will be described with reference to FIG. FIG. 3 is a block diagram showing the semiconductor device manufacturing system 10 according to the first embodiment. In FIG. 3, constituent elements related to the removal of the foreign matter 5 attached on the wafer 1 are selectively illustrated, and other general constituent elements are not illustrated.

  As shown in FIG. 3, the semiconductor device manufacturing system 10 includes a manufacturing apparatus 20 and a control apparatus 30. The manufacturing apparatus 20 includes a contraction layer forming unit 21, a crack forming unit 22, and a removing unit 23.

  Here, the contraction layer forming unit 21 is a device that applies a resist to the wafer 1 and spin coats it in a lithography process. The crack forming unit 22 is a resist curing device that cures the resist in the lithography process. The removing unit 23 is a resist stripping device that strips the resist from the wafer 1 in the lithography process.

  The control device 30 includes a control unit 31 and a storage unit 32. The storage unit 32 stores information such as a program necessary for manufacturing a semiconductor device such as the foreign substance removal program 34 and various parameters. Here, the foreign matter removal program 34 describes a procedure of the manufacturing process (see FIG. 1) for removing the foreign matter described above, processing conditions in the crack formation step and the removal step, and the like.

  The processing conditions are, for example, the coating amount of the material for the shrink layer 6 to be applied to the wafer 1, the rotational speed of the spin coat, the light intensity and irradiation time necessary for forming the crack 7 in the shrink layer 6, and the foreign material 5 For example, the processing time required to remove the material.

  Such processing conditions are optimum conditions calculated by conducting a test in advance. For example, when determining the light intensity and irradiation time for forming the crack 7 in the shrinkable layer 6, the shrinkable layer 6 is formed on the test wafer 1, and the test is performed by changing the light intensity and irradiation time. And the cross section of each shrinkage | contraction layer 6 after a test is observed with an electron microscope etc., and the intensity | strength and irradiation time when the crack 7 which reaches the lower surface from the upper surface of the shrinkage layer 6 are formed are determined as processing conditions.

  The control unit 31 is a processing unit that performs overall control of the entire semiconductor device manufacturing system 10, and includes a foreign matter removal instruction unit 33. The foreign matter removal instructing unit 33 executes the foreign matter removal program 34 and outputs a predetermined control signal to the manufacturing apparatus 20 each time a constituent material is deposited on the wafer 1, for example. Then, the crack forming unit 22 and the removing unit 23 are operated to perform the removing operation of the foreign matter 5.

  As described above, in the semiconductor device manufacturing system 10, the existing various devices used in the lithography process are diverted, and the foreign material 5 is removed from the upper surface of the wafer 1 by operating each device according to the control by the control device 30. Therefore, according to the semiconductor device manufacturing system 10, it is possible to remove the foreign matter 5 adhered to the upper surface of the wafer 1 without increasing the manufacturing cost.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a schematic cross-sectional view showing a contraction mode of the contraction layer 6a according to the second embodiment. In FIG. 4, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

  As shown in FIG. 4A, in this embodiment, a shrink layer 6a laminated on the upper surface of the metal wiring layer 4 in order to remove the foreign material 5 is different from the shrink layer 6 in the first embodiment. Specifically, in the first embodiment, a resist having translucency is used as the contraction layer 6, but in this embodiment, a resist having semi-translucency is used as the contraction layer 6a.

  That is, the shrink layer 6a of the present embodiment is formed using a polymer or the like having a lower light transmission than the shrink layer 6 of the first embodiment. Therefore, as shown in FIG. 4A, when the light α is irradiated onto the contraction layer 6a from above, the intensity of the light α decreases in the contraction layer 6a from the upper surface to the lower surface. In FIG. 4A, the larger the size of the arrow indicating the light α is, the higher the intensity of the light α is.

  The shrink layer 6a is formed on the metal wiring layer 4 by spin coating. Note that the shrinkable layer 6a of the present embodiment also has a higher optical shrinkage than the constituent material (here, the metal wiring layer 4) on the upper surface of the wafer 1.

  As a result, when the contraction layer 6a is irradiated with light α from above, the upper surface side is irradiated with light α having higher intensity than the lower surface side, and therefore, as shown in FIG. Shrinks at a higher shrinkage rate than the lower surface side. That is, the fragments of the shrink layer 6a that had a width L before being irradiated with the light α shrink the bottom surface width to M and the top surface width to N. Here, the magnitude relationship between L, M, and N is L> M> N.

  As described above, the shrink layer 6a of the present embodiment shrinks at a shrinkage rate higher on the upper surface than on the lower surface when the light α is irradiated. Therefore, when the light α is irradiated to the contraction layer 6a until the crack 7 (see FIG. 1) is formed, in the fragments of the contraction layer 6a, the peripheral portion of the lower surface is forcibly pulled upward by the contraction force of the upper surface. .

  As described above, in the present embodiment, the shrinkable layer 6a can be displaced from the upper surface of the metal wiring layer 4 to a state where it can be more easily peeled off, so that the processing time required for removing the foreign matter 5 can be shortened. .

  In the present embodiment, the case where the entire shrink layer 6a has a uniform semi-translucency has been described. However, even if the shrink layer is formed so that the translucency of the lower layer side is lower than the upper layer side. The contraction layer can be contracted in the contraction mode shown in FIG.

  In such a case, for example, after the lower layer side of the shrinkage layer is formed with a polymer mixed with fine particles serving as an anti-transmission material that suppresses light transmission, the amount of fine particles serving as the anti-transmission material is gradually reduced while the shrink layer is mixed. The upper layer side is formed. Thereby, the translucency (transparency) of a contraction layer can be reduced, so that it goes to the lower layer of a contraction layer.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a schematic cross-sectional view showing a contraction mode of the contraction layer 6b according to the third embodiment. In FIG. 5, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

  As shown in FIG. 5A, in this embodiment, a shrink layer 6b laminated on the upper surface of the metal wiring layer 4 in order to remove the foreign material 5 is different from the shrink layer 6 in the first embodiment. Specifically, in the first embodiment, a resist having a photoshrink property is used as the shrink layer 6, but in this embodiment, a resist having a heat shrink property is used as the shrink layer 6 b.

  That is, the shrink layer 6b is formed using a polymer or the like that shrinks at a higher shrinkage rate as the temperature becomes higher due to heat treatment or the like. Note that the shrink layer 6b of the present embodiment has higher thermal shrinkage than the constituent material (here, the metal wiring layer 4) on the upper surface of the wafer 1.

  The contraction layer 6b is formed on the metal wiring layer 4 by spin coating. In the present embodiment, the shrink layer 6b is heat-treated so that the upper layer is at a higher temperature than the lower layer of the shrink layer 6b. For example, as shown in FIG. 5B, ions 8 are implanted (implanted) from the upper surface of the contraction layer 6b to a predetermined depth.

  At this time, the vicinity of the upper surface of the contraction layer 6b is selectively heated by the collision between the ions 8 and the contraction layer 6b, becomes higher than the lower surface portion, and contracts and hardens. At this time, the heat of the upper surface portion of the shrink layer 6b is also transmitted in the lower surface direction, so that the vicinity of the lower surface also contracts.

  Thus, in the contraction layer 6b, when the ions 8 are implanted into the upper layer portion, the upper layer side becomes hotter than the lower layer side, so that the upper layer side is higher than the lower layer side as shown in FIG. Shrink with high shrinkage. That is, the fragments of the contraction layer 6b whose width was P before the ions 8 were implanted contract the lower surface width to Q and the upper surface width to R. Here, the magnitude relationship of P, Q, and R is P> Q> R.

  Therefore, when the ions 8 are implanted until the crack 7 (see FIG. 1) is formed, in the fragments of the contraction layer 6b, the peripheral portion of the lower surface is forcibly pulled upward by the contraction force of the upper surface.

  As described above, in the present embodiment, the contraction layer 6b can be displaced from the upper surface of the metal wiring layer 4 so as to be more easily peeled off, so that the processing time required for removing the foreign matter 5 can be shortened. .

  Note that the method of heat treatment performed on the shrink layer 6b is not limited to the implantation of ions 8. For example, a method of heating by causing plasma to collide with the upper surface of the shrink layer 6b, or a method of heating by providing a heater on the upper surface side of the shrink layer 6b may be used.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment. In FIG. 6, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

  In the present embodiment, in the contraction layer forming step, a plurality of contraction layers (here, the first contraction layer 6 c and the second contraction layer 6 d) whose contraction rate increases from the lower layer to the upper layer are stacked on the upper surface of the wafer 1.

  Specifically, in this embodiment, as shown in FIG. 6A, when the foreign material 5 adheres to the metal wiring layer 4 constituting the uppermost surface of the wafer 1, as shown in FIG. A first contraction layer 6 c is formed on the upper surface of the metal wiring layer 4.

  The first shrink layer 6 c is formed by spin-coating a material having higher shrinkage than the upper surface of the wafer 1 on the upper surface of the wafer 1. Then, in this embodiment, as shown in FIG.6 (c), the 2nd contraction layer 6d is formed in the upper surface of the 1st contraction layer 6c.

  The second contraction layer 6d is formed by spin-coating a material having higher contractibility than the first contraction layer 6c on the upper surface of the first contraction layer 6c. Here, for example, resists having translucency used in the lithography process and different in photocontractability are formed as the first contraction layer 6c and the second contraction layer 6d.

  Subsequently, as shown in FIG. 6 (d), in the present embodiment, the first shrink layer 6c and the second shrink layer 6d are shrunk and cured by irradiating light on the upper surface of the second shrink layer 6d. A crack forming step for forming cracks 7 in the first shrink layer 6c and the second shrink layer 6d is performed.

  At this time, since the second shrinkable layer 6d has higher photoshrinkability than the first shrinkable layer 6c, it shrinks at a high shrinkage rate. Here, the first shrinkable layer 6c and the second shrinkable layer 6d are formed of the same kind of polymer or the like only with different photoshrinkability. For this reason, the adhesive force between the first shrink layer 6c and the second shrink layer 6d is higher than the adhesive force between the first shrink layer 6c and the wafer 1 (metal wiring layer 4).

  Therefore, the second contraction layer 6 d can turn up the peripheral portion of the fragment of the first contraction layer 6 c from the upper surface of the wafer 1 without peeling from the first contraction layer 6 c. Thus, in this embodiment, since the peripheral part of the fragment of the 1st contraction layer 6c is forcibly pulled up by the contraction force of the 2nd contraction layer 6d, the 1st contraction layer 6c and the 2nd contraction layer 6d can be displaced from the upper surface of the metal wiring layer 4 to a state where it can be more easily peeled off.

  Subsequently, in the present embodiment, as shown in FIG. 1E, the first shrink layer 6c and the second shrink layer 6d together with the foreign matter 5 are peeled off from the wafer 1 and removed using a resist stripping apparatus used in the lithography process. A removing step is performed.

  At this time, the metal film covering the foreign material 5 is already separated from the metal wiring layer 4 by the above-described crack formation process. Accordingly, the first shrink layer 6c and the second shrink layer 6d are easily removed together with the foreign matter 5 by the existing resist stripping apparatus.

  As described above, in the present embodiment, in the contraction layer forming step, the plurality of contraction layers (here, the first contraction layer 6c and the second contraction layer 6d) whose contraction rate is higher from the lower layer toward the upper layer are disposed on the surface. Are stacked on the upper surface of the wafer 1 to which the is adhered, and a crack 7 is generated by a crack forming process.

  Thereby, in this embodiment, the peripheral part of the fragment of the 1st contraction layer 6c divided by the crack 7 with a low contraction rate is reliably made from the upper surface of the wafer 1 by the contraction force of the 2nd contraction layer 6d with a high contraction rate. Can be turned up.

  Therefore, according to the present embodiment, the foreign matter 5 can be easily and reliably removed from the upper surface of the wafer 1 together with the first shrink layer 6c and the second shrink layer 6d. In the contraction layer forming step of the present embodiment, three or more contraction layers having a higher contraction rate from the lower layer toward the upper layer can be formed.

  In the present embodiment, both the first shrink layer 6c and the second shrink layer 6d are made of a resist. However, if at least the first shrink layer 6c is made of a resist, the first shrink layer is formed by an existing resist peeling apparatus. 6c and the second shrink layer 6d can be peeled off. In such a case, the second shrinkable layer 6d is formed using a material having a higher adhesive force to the first shrinkable layer 6c than the adhesive force between the first shrinkable layer 6c and the constituent material constituting the uppermost layer of the wafer 1.

  In the embodiment described above, the shrinkage layer is shrunk by light irradiation or heat treatment to form the crack 7 in the shrinkage layer. However, the upper layer side of the shrinkage layer is selectively altered using a predetermined chemical agent to lower the lower layer. The crack 7 may be formed by contracting the upper layer side with a higher contraction rate than the side.

  In the above-described embodiment, the contraction layer is formed exclusively for removing the foreign material 5, but a resist formed for patterning the constituent material of the semiconductor device can also be used as the contraction layer for removing the foreign material 5.

  For example, a resist forming process performed for patterning a constituent material formed on the wafer 1 is also used as a shrinking layer forming process. Then, after the constituent material of the semiconductor device is patterned by etching using the resist as a mask, a crack forming step for forming a crack 7 in the resist is performed. Thereafter, the resist peeling process used for patterning is also used as the removing process for removing the foreign matter 5.

  As a result, the foreign matter 5 fixed on the portion of the wafer 1 not covered with the resist mask is removed by etching, and the foreign matter 5 fixed on the portion covered with the resist mask is cracked 7. Is removed by peeling off the formed resist.

  As described above, by using the resist formed for patterning the constituent material of the semiconductor device as the shrink layer for removing the foreign material 5, it is possible to reduce the resist used exclusively for removing the foreign material 5. The manufacturing cost can be further reduced.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 Wafer, 2 Semiconductor substrate, 3 Silicon layer, 4 Metal wiring layer, 5 Foreign material, 6, 6a, 6b, 6c, 6d Contraction layer, 7 Crack, 8 Ion 10 Semiconductor device manufacturing system, 20 Manufacturing apparatus, 21 Contraction layer formation Part, 22 crack formation part, 23 removal part, 30 control device, 31 control part, 32 storage part, 33 foreign matter removal instruction part, 34 foreign matter removal program, α light

Claims (5)

A contraction layer forming step of forming a contraction layer having a contraction rate higher than that of the constituent material on the upper surface of the wafer on which the constituent materials of the semiconductor device are laminated;
A crack forming step of shrinking the shrink layer to form a crack in the shrink layer;
And a removing step of removing the shrink layer in which the crack is formed from the upper surface of the wafer. The shrink layer is
The method for manufacturing a semiconductor device according to claim 1, wherein the method is a resist used in a lithography process. The shrink layer is
The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device has light contractility and semi-translucency. The shrink layer is
With heat shrinkage,
In the crack formation step,
The method for manufacturing a semiconductor device according to claim 1, wherein a heat treatment is performed on the shrink layer so that an upper layer is higher in temperature than a lower layer of the shrink layer. The shrinkage layer forming step includes
5. The method of manufacturing a semiconductor device according to claim 1, wherein a plurality of the shrink layers having a higher shrinkage rate from the lower layer toward the upper layer are stacked on the upper surface of the wafer.

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