JP2001284209A - Method of forming multilayered resist pattern and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming a multilayered resist pattern, by which the coating step in a multilayered resist process can be simplified and a method of manufacturing a semiconductor device. SOLUTION: In the method of forming a multilayered resist pattern, a material having low solubility against the solvent of an SOG film material is used for a lower-layer resist and its solution is applied to a substrate 10 to be worked. Before baking the film 3' of the solution, an applied film is formed on the film 3' by dripping an SOG solution 7 onto the film 3'. It is also possible to drip the SOG solution after the film 3' is dried by means of a spin dryer, etc. Then the SOG solution 7 is dried and the film 3' and the film of the solution 7 are collectively baked (heat-treated) on a hot plate 5. In addition, after the solution for an upper-layer resist is applied to the SOG film 7, the upper-layer resist is formed by baking the solution. Consequently, the solution applying and baking steps performed every time at the time of forming the films 3' and film 7 in the conventional example can be carried out at the same time. Namely, one baking step can be omitted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lithography step in a method for manufacturing a semiconductor device, and more particularly to a method for forming a multilayer coating film in a multilayer resist process for laminating coating films.

[0002]

2. Description of the Related Art FIGS. 13 to 15 are sectional views showing a process for forming a conventional multilayer resist pattern. First, a spin chuck 101 capable of rotating a wafer 100
Supported by Next, the wafer 100 is rotated by the rotation of the spin chuck 101, and the lower resist solution 103 is supplied to the main surface of the rotating wafer 100 from the lower resist solution supply nozzle 102 (FIG. 13).
(A)). By rotating the wafer 100, the lower resist solution 103 is uniformly applied to the main surface. Thereafter, the film of the lower resist 103 applied on the main surface is dried (FIG. 13B). Next, the wafer 100 is mounted on a hot plate 105 and baked to form a lower resist 104 (FIG. 13C). Next, the SOG solution supply nozzle 106 applies the SOG solution 10 to the main surface of the wafer 100.
7 is supplied (FIG. 14A). Due to the rotation of the wafer 100, the SOG solution 107 is uniformly dispersed in the lower resist 10.
4 is applied. Thereafter, the film of the SOG solution film 107 applied on the lower resist 104 is dried (FIG. 14B).

Next, the wafer 100 is mounted on a hot plate 105 and baked to form an SOG film 1 as an intermediate layer.
08 is formed (FIG. 14C). Next, wafer 1
The upper resist solution supply nozzle 109 supplies an upper resist solution 110 to the main surface of the substrate 00 (FIG. 15A).
By rotating the wafer 100, the upper resist solution 110
Is uniformly applied on the SOG film 108. Then, S
The film of the upper resist solution 110 applied on the OG film 108 is dried (FIG. 15B). Next, wafer 1
00 is mounted on a hot plate 105 and baked to form an upper resist 111. In this manner, a multilayer resist film including the lower resist 104, the SOG film 108 as an intermediate layer, and the upper resist 111 is formed on the wafer 100 (FIG. 15C). This SOG film is a silicon oxide film (SiO ₂ ). It is formed by spin-coating a glass solution dissolved in an organic solvent on a wafer and performing heat treatment.

This multilayer resist film is formed on a metal film (processed film) such as aluminum formed on a wafer. Next, a step of patterning the upper layer resist,
SOG using the patterned upper resist as a mask
Through a step of patterning the film by etching, a step of patterning the lower resist by etching using the patterned SOG film as a mask, and a step of etching a metal film such as aluminum using the patterned lower resist as a mask, The metal film is patterned to form a metal wiring.

[0005]

In the conventional method, the multilayer resist pattern is composed of upper resist / SOG / lower resist. The step of forming these multilayer films usually includes a step of first applying and baking a lower resist on a substrate to be processed, then applying and baking an SOG film, and further applying and baking an upper resist. Therefore, there is a problem that the process becomes very complicated. The present invention has been made under such circumstances, and provides a method of forming a multilayer resist pattern capable of simplifying a coating step in a multilayer resist process, and a method of manufacturing a semiconductor device using the method.

[0006]

The present invention has been made to solve the above-mentioned problems. As a first method, a material having low solubility in a solvent of an SOG film material is used as a lower resist, and this is coated. An SOG solution is dropped on this film to form a coating film before baking the lower layer resist. At this time, the SOG solution may be dropped after the applied lower layer resist is dried by a method such as spin drying or reduced pressure drying. Thereafter, the SOG solution is dried, and the lower layer resist and the film of the SOG solution are baked (heat treated) at a time. Next, after applying an upper resist solution on the SOG film, baking is performed to form an upper resist. By using the method of the present invention, the coating and baking process for forming the lower resist and the SOG film, which has been repeatedly performed each time a conventional film is formed, can be performed once. Therefore, only two bake revisions are required, and one bake revision can be omitted.

Further, the present invention is applicable not only to the upper layer resist / SOG film / lower layer resist, which is the film configuration in the multilayer resist process, but also to a multilayer resist film having a film configuration of upper layer resist / lower layer resist. is there. After patterning the upper resist, which is a film configuration of the multilayer resist film, SOG serving as a mask material for the lower resist is applied, the SOG film is etched back, and the SOG film is buried in the portion of the upper resist that has been removed by etching. The upper layer resist is removed and the embedded SOG is removed.
Even in a process in which the lower resist is etched using the film as a mask, the solvent of the upper resist is SO
Since the composition is close to that of the solvent of the G solution, it can be applied in the same manner as the method of simultaneously heating the film structure of the SOG / lower-layer resist. A second method of the present invention is a method of applying a mixed solution of a lower resist material and SOG on a substrate to be processed, and forming a laminated coating film by utilizing phase separation between the two. In a solution in which two or more polymer materials having different polarities are mixed, phase separation occurs when the concentration of the polymer material in the solution reaches a certain value. Thereafter, the substrate to be processed is baked. In this case, since the surface energy is stabilized thermodynamically on the surface of the coating film, a component having a small polarity is likely to be collected.

In consideration of such characteristics, a material having a polar group such as a hydroxyl group such as a phenol novolak resin or polyhydroxystyrene is preferable as the lower resist. Examples of the solvent include acetone, methyl ethyl ketone, methyl isobutyl ketone, ketone solvents such as cyclohexanone, cellosolve solvents such as methyl cellosolve, methyl cellosolve acetate, ethyl cellosolve acetate, ethyl lactate, ethyl acetate, butyl acetate, and isoamyl acetate. Examples include ester solvents, alcohol solvents such as methanol, ethanol, and isopropanil (above, polar solvents), and annealing, toluene, xylene, and naphtha (above, nonpolar solvents). As the SOG material, a material having a small hydroxyl group content such as a methylsiloxane polymer is desirable. In addition, as an intermediate layer material other than SOG, dimethylpolysilane, diphenylpolysilane, methylphenylpolysilane, or a copolymer of these having no polar group may be used. As the solvent, SO
When G is mixed with the above-mentioned polar solvent such as alcohols or polysilane, the above-mentioned non-polar solvent is desirable. In that case, the number of polar groups contained in the lower resist may be small.

That is, the method for forming a multilayer resist pattern of the present invention comprises the steps of:
Forming a multi-layered coating film comprising an intermediate layer and an upper-layer resist as a mask for the lower-layer resist, and pattern-transferring the multi-layered coating film by sequential etching, wherein the coating film for the intermediate layer is a metal compound. The coating film of the lower resist is made of at least an organic compound of a material having low solubility in a solvent of the metal compound solution of the intermediate layer, and the solution of the organic compound of the lower resist is formed on the substrate to be processed. After coating and drying, the solution of the metal compound as the intermediate layer is applied onto the coating film of the lower resist and dried, and the lower resist and the coating film of the intermediate layer are simultaneously subjected to heat treatment. . The lower layer resist may be made of a polymer material having a carbon content of 80% by weight or more, and the solvent of the metal compound solution forming the intermediate layer may be made of a polar solvent. Between the step of applying the lower resist and the step of applying a solution of the next component on the coating film, the method further comprises a step of irradiating the surface of the lower resist with radiation such as ultraviolet rays or electron beams. You may do it.

The method of forming a multilayer resist pattern according to the present invention comprises the steps of: forming a multi-layer coating film composed of at least a lower resist composed of an organic compound and an upper resist on a substrate to be processed; Simultaneously heating the coating film, patterning the upper layer resist to remove unnecessary portions, embedding an intermediate layer made of a metal compound between the resist patterns of the upper layer resist, and masking the intermediate layer Forming a multilayer resist pattern composed of the lower resist and an intermediate layer by etching the lower resist. The organic compound serving as the lower resist may be a material having low solubility in a solvent of the resist solution serving as the upper resist. The lower resist has a carbon content of 8
The solvent of the resist solution for forming the upper resist may be a polar solvent, which is a polymer material of 0% by weight. In the step of forming a multi-layered coating film composed of a lower resist, an intermediate layer serving as a mask for the lower resist, and an upper resist on the substrate to be processed, the mixed solution of the lower resist and the intermediate layer is applied onto the substrate to be processed. You may do it.

According to the method of manufacturing a semiconductor device of the present invention, there is provided a step of forming a film to be processed on a semiconductor substrate, a step of applying and drying a lower resist on the target, and a step of forming a metal on the dried lower resist. A step of applying a compound solution to form a film of the metal compound solution, and a step of simultaneously heating the lower layer resist and the film of the metal compound solution to form an intermediate layer made of the metal compound on the lower layer resist. ,
A step of applying and drying an upper layer resist on the intermediate layer, a step of heating the upper layer resist, a step of patterning the upper layer resist, and the step of etching the intermediate layer using the patterned upper layer resist as a mask Patterning, patterning the lower resist by etching using the patterned intermediate layer as a mask, and etching the film to be processed using the patterned lower resist as a mask. It is characterized by.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. First, the first method will be described with reference to FIGS. 1 to 3 show a first embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a process for forming a multilayer resist pattern by the method of (1). First, the wafer 10 is supported by the rotatable spin chuck 1. The wafer 10 is rotated by the rotation of the spin chuck 1, and the lower resist solution supply nozzle 2 supplies the lower resist solution 3 to the main surface (the surface to be processed) of the rotating wafer 10. As the lower resist, a material having low solubility in the solvent of the SOG film material as the intermediate layer is used (FIG. 1A). The lower resist solution 3 is uniformly applied to the main surface by the rotation of the wafer 10. Thereafter, the lower resist solution 3 applied on the main surface is dried by a method such as spin drying or reduced pressure drying (FIG. 1B), and a film 3 ′ of the lower resist solution is formed on the wafer 10. (FIG. 1 (c)).

Next, the SOG solution 7 is supplied to the main surface of the wafer 10 from the SOG solution supply nozzle 6 (FIG. 2).
(A)). Due to the rotation of the wafer 10, the SOG solution 7
The lower resist solution is uniformly applied on the film 3 '. Thereafter, the SOG solution 7 applied on the film 3 'of the lower resist solution is dried to form a film of the SOG solution 7 (FIG. 2).
(B)). Next, after the wafer 10 is mounted on the hot plate 5, the film of the SOG solution 7 and the film 3 'of the lower resist solution are baked collectively to form the lower resist 4 and the SOG film as an intermediate layer laminated thereon. 8 is formed (FIG. 2C). Next, the upper layer resist solution 11 is supplied to the main surface of the wafer 10 from the upper layer resist solution supply nozzle 9 (FIG. 3A). By rotating the wafer 10, the upper resist solution 11 is uniformly applied on the SOG film 8. Thereafter, the upper resist solution 11 applied on the SOG film 8 is dried to form a film of the upper resist solution 11 (FIG. 3B). Next, the wafer 10 is mounted on the hot plate 5 and baked to form an upper resist 12 on the SOG film 8. In this manner, a multilayer resist film of the upper resist 4, the SOG film 8 as the intermediate layer, and the upper resist 12 is formed on the wafer 10 (FIG. 3).
(C)).

In this method, since a material having low solubility in the solvent of the SOG film material as the intermediate layer is used as the lower resist, there is no need to apply the SOG solution after the lower resist bake, and the lower resist solution is applied and dried. Later, an SOG solution can be applied. And SO
After the G solution is dried, the lower resist solution film and the SOG solution film are simultaneously baked. For this reason, the coating and baking steps for forming the lower resist and the SOG film, which have been repeatedly performed, can be performed once. The baking temperature is a temperature range necessary for curing the lower resist and SOG, and is generally 200 to 500C. The upper limit temperature is determined by the heat resistance of the base including the film to be processed. As a material for the lower layer resist, a polymer material having a high carbon content as described above is desirable. The coating film surface of the lower resist using this material becomes hydrophobic after coating and drying, and SOG
This is because it can be made insoluble in alcohols used as a solvent of the solution. Here, from the viewpoint of etching resistance, the carbon content of the lower resist is preferably 80% by weight or more. If it is less than 80%, the etching resistance is reduced, and the adhesion to the intermediate layer is not good.

During the above drying step, UV (ultraviolet) irradiation or EB (electron beam) irradiation is carried out for the purpose of promoting drying (more desirably, crosslinking reaction) of the surface layer or bulk of the lower resist. You may go. In addition,
There is also a method in which the SOG solution is dropped and spread on the lower resist solution that has been dropped and spread on the substrate to be processed before the drying step. Further, in the present invention, not only the laminated structure of the upper resist / SOG / lower resist, which is the film constitution in the conventional multilayer resist process, but also the film constitution of the upper resist / lower resist, the upper resist of the multilayer resist film is patterned. In the process of applying SOG, which is the mask material of the lower layer resist after etching, etching the lower layer resist and then etching the lower layer resist, the solvent of the upper layer resist has a composition similar to that of the SOG solution, so that it is applicable. is there.

Next, a first embodiment according to the first method will be described with reference to FIGS. In this embodiment, a method of forming a wiring groove in an insulating film formed on a semiconductor substrate such as silicon using the multilayer resist film formed as described above will be described. 4 and 5 are cross-sectional views illustrating a process of manufacturing a semiconductor device in which a wiring groove is formed. The wafer is described as a semiconductor substrate. On a semiconductor substrate 13 such as silicon,
A 1 μm-thick silicon oxide film 14 serving as a film to be processed is formed. On the silicon oxide film 14, a single layer of a lower resist solution comprising a solution of poly (2,6-biphenylylene ethylene) (Mw = 10000, hereinafter referred to as polyarylene) having a solid content of 10 wt% in a cyclohexanone solvent is dissolved. The number of rotations (3
Semiconductor substrate 13 by spin coating at 000 rpm).
Coating and spin drying were performed. Subsequently, an SOG solution having a solid concentration of 4 wt% (solvent:
Propylene glycol monopropyl ether) was applied on the film of the lower resist solution by spin coating at a rotation speed (2500 rpm) at which the film thickness became 100 nm. At this time, no change in the thickness of the lower resist solution due to dissolution of the polyarylene film was observed.

Thereafter, the semiconductor substrate 13 coated with the SOG / polyarylene laminated coating film is placed on a hot plate,
First, heat treatment is performed at 180 ° C. for 1 minute, and then 250 ° C.
Heat treatment was performed at 1 ° C. for 1 minute. The heat treatment was performed in an atmosphere having a humidity of 40%. Defects such as cracks were not observed in the heat-treated laminated coating films 4 and 8 (SOG film 8 / lower-layer resist 4). Then, a chemically amplified positive resist J is formed on the SOG film 8.
A coating film (upper layer resist) 12 of SR M20G (thickness: 200 nm) is formed (FIG. 4A), and NA = 0.68, σ = 0 with a KrF excimer laser exposure apparatus (NSR S203B: manufactured by Nikon Corporation). 0.75, using a halftone mask with a transmittance of 6% under the condition of 2/3 annular illumination.
13 μmL / S was transferred. The exposure amount is 17 mJ / cm ²
Met. The resist pattern formed on the SOG film 8 showed a good shape without footing (FIG. 4B).
Thereafter, using the resist pattern as a mask, CF ₄ / O is applied in a reactive ion etching (RIE) apparatus.
The dry etching of the SOG film 8 was performed using a plasma composed of a mixed gas of ₂ / Ar. SOG film 8 after processing
Indicates a good shape, and a dimensional conversion difference (resist size−S
OG dimension) was 5 nm or less. The residual resist film at this time was 100 nm (FIG. 4C).

Subsequently, the polyarylene film as the lower resist 4 was processed using the SOG film as a mask. A mixed gas of O ₂ / N ₂ was used as an etching gas. The shape of the processed polyarylene film was good, and the dimensional conversion difference (SOG dimension-polyarylene dimension) was 10 nm or less (FIG. 5A). Thereafter, a groove (wiring groove) 15 having a depth of 300 nm is formed in the silicon oxide film 14 to be processed by RIE using a mixed gas of C ₄ F ₈ / O ₂ / Ar (FIG. 5B). The lower resist 4 was peeled off by O ₂ ashing. The silicon oxide film 14 after removing the resist had a good shape. Next, after depositing a barrier metal on the silicon oxide film 14 and inside the wiring groove 15,
A metal film such as aluminum is deposited, and this is
The metal wiring 16 covered with the barrier metal is buried in the wiring groove 15 by flattening by a method such as mical mechanical polishing (FIG. 5C). According to this method, the conventional three baking processes for forming the lower resist, the SOG film, and the upper resist can be reduced to two, a baking process of the SOG / lower resist laminated coating film and a baking process of the upper resist. The baking step can be omitted once.

The thickness of the lower resist used here is as follows:
About 300 to 500 nm, and the thickness of the SOG film is 30 to 1
The thickness of the upper resist is about 0.1 to 0.1 nm.
About 3 μm is appropriate. Next, another example of the first method will be described as a second embodiment. A 1 μm-thick silicon oxide film serving as a film to be processed is formed on a semiconductor substrate such as silicon. Thereafter, Cytop CTXS, which is a copolymer of tetrafluoroethylene and a fluorine-based monomer having a cyclic perfluoroether group, is formed on a semiconductor substrate.
(Trade name: Asahi Glass Co., Ltd.) with solvent CTSOLV180
(Trade name: manufactured by Asahi Glass Co., Ltd.) A lower layer resist is formed on a semiconductor substrate by spin coating at a rotation speed (3000 rpm) such that a solution having a thickness of 500 nm when formed as a single layer is formed in a single layer. And spin-dried. Subsequently, a solid content concentration of 4 wt% is formed on the lower resist.
SOG solution (solvent: propylene glycol monopropyl ether) was applied onto the lower resist by spin coating at a rotation speed (2500 rpm) such that the film thickness became 100 nm. At this time, no change in the thickness of the lower resist due to dissolution was observed.

After that, lamination coating of SOG / lower layer resist
First, place the semiconductor substrate coated with the film on a hot plate.
A heat treatment is performed at 180 ° C. for 1 minute, and then at 250 ° C. for 1 minute.
The heat treatment was performed for a minute. What is the atmosphere in the heat treatment?
The test was performed in a 40% atmosphere. Heat treatment in this way
Defects such as cracks were observed in the processed multilayer coating film.
I couldn't. After that, the chemically amplified polish is placed on the SOG film.
Coating of resist JSR M20G (film thickness 200nm)
After forming a film, a KrF excimer laser exposure device (NSR
 S203B: Nikon Corporation), NA = 0.68, σ
= 0.75, under conditions of 2/3 annular illumination, transmittance 6%
Transfer 0.13μmL / S using a halftone mask
did. Exposure amount is 17 mJ / cm^TwoMet. SOG film
The resist pattern of the upper layer resist formed on the bottom
A good shape was shown without pulling. After that,
Using the turn as a mask, CF in the RIE device_Four/ O _Two
Of the SOG film using a plasma composed of a mixed gas of
Dry etching was performed. Good SOG film after processing
Dimensional conversion difference (resist dimension-SOG)
Dimension) was 5 nm or less. Resist remaining film at this time
Was 100 nm.

Subsequently, a polyarylene film as a lower resist was processed using the SOG film as a mask. A mixed gas of O ₂ / N ₂ was used as an etching gas. The shape of the polyarylene film after processing was good, and the dimensional conversion difference (SOG dimension-polyarylene dimension) was 10 nm or less. After that, the silicon oxide film to be processed is
A groove having a depth of 300 nm was formed by RIE using a mixed gas of ₄ F ₈ / O ₂ / Ar, and the lower resist was peeled off by O ₂ ashing. The silicon oxide film after peeling the lower resist showed a good shape. A metal wiring such as aluminum is buried in this groove. According to this method, the conventional three baking processes for forming the lower resist, the SOG film, and the upper resist can be reduced to two, a baking process of the SOG / lower resist laminated coating film and a baking process of the upper resist. The baking step can be omitted once.

Next, another example of the first method will be described as a third embodiment with reference to FIGS. FIG.
8 are cross-sectional views showing a process for forming a multilayer resist pattern according to the first method of the present invention. Wafer 20 made of silicon or the like supported by spin chuck 21
A 1 μm-thick silicon oxide film serving as a film to be processed is formed thereon. On this silicon oxide film, poly (2,6-biphenylylene ethylene) (Mw = 250) supplied from a nozzle 22 and having a solid content of 1 wt% in a cyclohexanone solvent.
0, hereinafter referred to as polyarylene) was applied on the wafer 20 under the condition that the lower resist 23 solution film composed of a solution in which a single layer was formed had a film thickness of 500 nm (FIG. 6A). Subsequently, the lower resist 23 solution film was transferred into a reduced pressure chamber, and the solution was removed under a reduced pressure of 1 mTorr.
The solvent was dried by allowing to stand for 0 second (FIG. 6 (b)). Thereafter, an EB irradiator installed in the decompression chamber irradiates an electron beam having an acceleration voltage of 10 kV with an irradiation amount of 1 mC / cm ² under a condition of a gap of 3 mm (FIG. 6).
(C)). When the EB irradiation was not performed, the lower resist solution film was dissolved in the SOG solution, and a change in the film thickness was observed after the application of the SOG solution.

Thereafter, an SOG solution film (solvent: propylene glycol monopropyl ether) 27 having a solid concentration of 4 wt% supplied from a nozzle 26 is supplied on the lower resist solution film 23 at a rotation speed (2,500 rpm) at which the film thickness becomes 100 nm.
pm) by spin coating. No change in the thickness of the lower resist due to dissolution of the lower resist solution film in the SOG solution was observed (FIG. 7A). Then, SO
The wafer 20 on which the laminated coating films 23 and 27 of G / lower-layer resist are applied is first placed on a hot plate 25 at 180 ° C.
For 1 minute, and then heat treatment at 250 ° C. for 1 minute to form the lower resist 24 and the SOG film 28. The heat treatment was performed in an atmosphere of 40% humidity (FIG. 7B). Next, the upper resist solution 211 is supplied to the main surface of the wafer 20 from the upper resist solution supply nozzle 29 (FIG. 7C). Wafer 2
0, the upper layer resist solution 211 is uniformly SO
It is applied on the G film 28. Thereafter, the upper resist solution 211 applied on the SOG film 28 is dried to form a film of the upper resist solution 21 (FIG. 8A). Next, the wafer 20 is mounted on the hot plate 25 and baked to form an upper resist 212 on the SOG film 28. Thus, the lower resist 26 and the intermediate layer S
A multilayer resist film of the OG film 28 and the upper resist 212 is formed on the wafer 20 (FIG. 8B).

The laminated film subjected to such a heat treatment has a crack.
No defects such as racks were found. Then, the above S
Chemical amplification type positive resist JSR M20G on OG film
(200 nm thick) coating film (upper resist)
And a KrF excimer laser exposure device (NSR S20
3B: manufactured by Nikon Corporation) NA = 0.68, σ = 0.7
Half-toe with 6% transmittance under 5, 2/3 annular lighting conditions
Using a mask, 0.13 μmL / S was transferred. Dew
Light intensity is 17mJ / cm^TwoMet. On the SOG film 28
The resist pattern of the upper resist is
And showed a good shape. After that,
Using the turn as a mask, CF in the RIE device_Four/ O _Two
Of the SOG film using a plasma composed of a mixed gas of
Dry etching was performed. Good SOG film after processing
Dimensional conversion difference (resist dimension-SOG)
Dimension) was 5 nm or less. Resist remaining film at this time
Was 100 nm.

Subsequently, using the SOG film as a mask, a polyarylene film as a lower resist was processed. A mixed gas of O ₂ / N ₂ was used as an etching gas. The shape of the processed polyarylene film was good, and the dimensional conversion difference (SOG dimension-polyarylene dimension) was 10 nm or less. After that, the silicon oxide film to be processed is subjected to RIE using a mixed gas of C ₄ F ₈ / O ₂ / Ar.
A groove having a depth of 300 nm was formed, and the resist was peeled off by O ₂ ashing. The silicon oxide film after stripping the resist showed a good shape. Next, another example of the first method will be described as a fourth embodiment with reference to FIGS. 9 and 10. 9 and 10 are cross-sectional views showing a process for forming a multilayer resist pattern according to the first method of the present invention. In this figure, the wafer, lower resist and upper resist used in FIGS. 1 to 3 are used. A multilayer resist film including a lower resist 4 and an upper resist 12 is formed on a wafer 10 such as silicon (FIG. 9).
(A)).

Then, the upper resist 12 is exposed using a photomask 17 (FIG. 9B), and is patterned (FIG. 9C). Next, a mask material for the lower resist is formed on the patterned upper resist 12 as S
An OG solution 18 is applied (FIG. 10A), and the SOG film 19 is buried in the portion of the upper resist that has been etched back by etching back (FIG. 10B). Then, S
The upper resist 12 remaining using the OG film 19 as a mask
Then, the patterned resist is formed by etching the lower resist 4 (FIG. 10C). In this embodiment, as in the first embodiment in which the SOG / lower-layer resist is heated simultaneously, the upper-layer resist / lower-layer resist is heated simultaneously. Therefore, conventionally, 2
A single heat treatment is sufficient to perform two heat treatments, and a complicated coating process in a multilayer resist process can be simplified. This embedded SOG
Even in a process in which the lower resist is etched using the film as a mask, the solvent of the upper resist is SO
Since the composition is very close to the solvent of the G solution, the present invention can be applied.

Next, a fourth embodiment which is an example according to the second method of the present invention will be described with reference to FIGS. In this embodiment, a second method will be described, and a method of forming a wiring groove in an insulating film formed on a semiconductor substrate such as silicon using a multilayer resist film formed by this method will be described. 11 and 12 are cross-sectional views showing a process for forming a multilayer resist pattern according to the second method of the present invention. First, the wafer 30 is supported by a rotatable spin chuck 31. The wafer 30 is rotated by the rotation of the spin chuck 31, and the mixed solution supply nozzle 32 is attached to the main surface (the surface to be processed) of the rotating wafer 30.
To lower resist material 33 and SOG 37 as an intermediate layer
Is supplied (FIG. 11A). The mixed solution 34 is uniformly applied to the main surface by the rotation of the wafer 30. Then, the mixed solution 34 applied on the main surface is
It is dried by a method such as spin drying or reduced pressure drying. A layered coating film is formed by utilizing the phase separation of the mixed solution of the lower resist material 37 and the SOG 33.

In a solution in which two or more polymer materials having different polarities are mixed, phase separation occurs when the concentration of the polymer material in the solution reaches a certain value (FIG. 11B). Next, after the wafer 30 is mounted on the hot plate 35, SOG3
The film 7 and the film of the lower resist material 33 are baked together to form a lower resist 36 and an SOG film 38 as an intermediate layer laminated thereon (FIG. 11C). In this case, since the surface energy is thermodynamically stabilized on the surface of the coating film, it is considered that components having a small polarity are likely to collect. Next, the upper resist solution 311 is supplied to the main surface of the wafer 30 from the upper resist solution supply nozzle 39 (FIG. 12A). The upper resist solution 311 is uniformly applied on the SOG film 38 by the rotation of the wafer 30. Thereafter, the upper resist solution 311 applied on the SOG film 38 is dried to form a film of the upper resist solution 311 (FIG. 12B). Next, the wafer 30 is mounted on a hot plate 35 and baked to form the SOG film 3.
8 is formed with an upper resist 312. In this way, a multilayer resist film including the lower resist 36, the SOG film 38 as the intermediate layer, and the upper resist 312 is formed on the wafer 30 (FIG. 12C).

In consideration of such properties, a material having a polar group such as a hydroxyl group such as a phenol novolak resin or polyhydroxystyrene is desirable as the lower layer resist. As the SOG material, a material having a small hydroxyl group content such as a methylsiloxane polymer is desirable. In addition, as an intermediate layer material other than SOG, dimethylpolysilane, diphenylpolysilane, methylphenylpolysilane, or a copolymer of these having no polar group may be used. Next, a process of processing a film formed on a semiconductor substrate using a multilayer resist pattern formed by this method will be described. A 1 μm-thick silicon oxide film serving as a film to be processed is formed on a semiconductor substrate such as silicon. On the film to be processed, any one of phenol novolak resin and poly (p-hydroxystyrene) is used as a lower layer resist material, and poly (methylsilsesquioxane) and poly (dimethylsilane) are used as an intermediate layer material. , Poly (diphenylsilane), poly (methylphenylsilane)
Was dissolved in a PGME solvent so as to have a total solid content of 10 wt%. The ratio of the material of the lower resist film to the material of the intermediate layer was 2: 5 by weight.

The above solution was applied on a wafer by spin coating and dried. Thereafter, the wafer coated with this film was subjected to a heat treatment at 180 ° C. for 1 minute on a hot plate, followed by a heat treatment at 250 ° C. for 1 minute. The heat treatment was performed in an atmosphere having a humidity of 40%. No defects such as cracks were found in the coating film subjected to such a heat treatment. When this coating film was observed with an electron microscope, the upper layer (film thickness: 100 n)
m) and a lower layer (thickness: about 300 nm). When this coating film was subjected to elemental analysis in the depth direction using a quadrupole secondary ion mass spectrometer (SIMSLABMK-III manufactured by VG), Si was detected only in the upper layer film. Thereafter, a coating film (upper resist film) of a chemically amplified positive resist JSR M20G (thickness: 200 nm) is formed on the above coating film, and a NA is obtained with a KrF excimer laser exposure device (NSR S203B: manufactured by Nikon Corporation).
= 0.68, σ = 0.75, 2/3 annular illumination conditions,
0.13 μm using a halftone mask having a transmittance of 6%
mL / S was transferred. The exposure amount was 17 mJ / cm ² . The resist pattern formed on the coating film showed a good shape without footing.

Then, by masking the resist pattern,
The coating film was dry-etched in a RIE apparatus using plasma composed of a mixed gas of CF ₄ / O ₂ / Ar.
The intermediate layer after processing showed a good shape, and the dimensional conversion difference (resist dimension-intermediate layer dimension) was 5 nm or less.
The residual resist film at this time was 100 nm. Subsequently, the lower layer resist was processed using the intermediate layer as a mask. A mixed gas of O ₂ / N ₂ was used as an etching gas. The shape of the processed polyarylene was good, and the dimensional conversion difference (intermediate layer size-lower layer film size) was 10 nm or less. After that, the silicon oxide film to be processed is changed to C ₄ F
₈ / O by RIE using mixed gas of ₂ / Ar, depth 3
A groove of 00 nm was formed, and the resist was stripped by O ₂ ashing. The silicon oxide film after stripping the resist showed a good shape. According to this method, the coating and baking steps for forming the lower resist and the SOG film, which have been repeatedly performed, can be performed once.

[0032]

According to the present invention, it is possible to simplify a coating process in a multi-layer resist process, which has conventionally been performed for each layer by using a plurality of layers. .

[Brief description of the drawings]

FIG. 1 is a manufacturing process sectional view for explaining a multilayer resist pattern forming method of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process for explaining a multilayer resist pattern forming method of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process for explaining a multilayer resist pattern forming method of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process for explaining a method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a manufacturing process sectional view for explaining the multilayer resist pattern forming method of the present invention.

FIG. 7 is a manufacturing process sectional view for explaining the multilayer resist pattern forming method of the present invention.

FIG. 8 is a manufacturing process sectional view for explaining the multilayer resist pattern forming method of the present invention.

FIG. 9 is a manufacturing process cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 10 is a manufacturing process cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.

FIG. 11 is a manufacturing process sectional view for explaining the multilayer resist pattern forming method of the present invention.

FIG. 12 is a cross-sectional view showing a manufacturing process for explaining a multilayer resist pattern forming method of the present invention.

FIG. 13 is a sectional view of a manufacturing process for explaining a conventional method for forming a multilayer resist pattern.

FIG. 14 is a cross-sectional view showing a manufacturing process for explaining a conventional method for forming a multilayer resist pattern.

FIG. 15 is a manufacturing process sectional view for explaining a conventional multilayer resist pattern forming method.

[Explanation of symbols]

1, 21, 31, 101 ... spin chuck 2,
6, 22, 26, 32, 36, 102, 106: nozzle, 3, 23, 33, 103: lower resist solution, 3 ': film of lower resist solution, 4, 24, 3
4, 104: lower layer resist, 5, 25, 35, 10
5 ... Hot plate, 7, 18, 27, 37, 10
7, an intermediate layer solution (SOG solution), 8, 19, 28,
38, 108 ... intermediate layer (SOG film), 10, 20,
30, 100... Wafer, 11, 110, 211,
311: Upper layer resist solution, 12, 212, 312
... Upper resist 13 Semiconductor substrate 14
... Silicon oxide film 15 Wiring groove 16
..Embedded wiring 17 Photomask.

Continuing from the front page (72) Inventor Rynobu Onishi 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 2H096 AA25 CA05 CA14 DA01 HA23 HA27 JA04 KA08 5F046 NA07 NA12 NA17 NA18

Claims (8)

[Claims] 1. A step of forming a multilayer coating film comprising at least a lower resist, an intermediate layer serving as a mask for the lower resist, and an upper resist on a substrate to be processed, and pattern-transferring these multilayer coating films by etching in order. The coating film of the intermediate layer is made of a metal compound, the coating film of the lower resist is made of at least an organic compound of a material having low solubility in the solvent of the metal compound solution of the intermediate layer, After applying the solution of the organic compound of the lower layer resist on the substrate to be processed and drying, apply the solution of the metal compound as the intermediate layer on the coating film of the lower layer resist and dry, and then dry the lower layer resist and the intermediate layer. A method for forming a multilayer resist pattern, comprising simultaneously applying heat treatment to the coating films of the layers. 2. The method according to claim 1, wherein the lower resist is made of a polymer material having a carbon content of 80% by weight or more, and a solvent of the metal compound solution forming the intermediate layer is a polar solvent. The method for forming a multilayer resist pattern according to the above. 3. Irradiating the surface of the lower resist with radiation such as ultraviolet rays or electron beams between the step of applying the lower resist and the step of applying a solution of the next component on the coating film. The method according to claim 1 or 2, further comprising a step. 4. A step of forming a multi-layer coating film composed of at least a lower resist and an upper resist composed of an organic compound on a substrate to be processed, and a step of simultaneously heating the multi-layer coating film composed of the lower resist and the upper resist. Patterning the upper layer resist to remove unnecessary portions; embedding an intermediate layer made of a metal compound between the resist patterns of the upper layer resist; etching the lower layer resist using the intermediate layer as a mask; Forming a multilayer resist pattern composed of the lower resist and an intermediate layer. 5. The method according to claim 4, wherein the organic compound serving as the lower resist is a material having low solubility in a solvent of the resist solution serving as the upper resist. 6. The method according to claim 4, wherein the lower resist is a polymer material having a carbon content of 80% by weight, and a solvent of a resist solution for forming the upper resist is a polar solvent. The method for forming a multilayer resist pattern according to the above. 7. A step of forming a lower resist, a multilayer coating film comprising an intermediate layer serving as a mask of the lower resist and an upper resist on the substrate to be processed, wherein a mixed solution of the lower resist and the intermediate layer is mixed The method according to claim 1, wherein the method is applied on a substrate to be processed. 8. A step of forming a film to be processed on a semiconductor substrate; a step of applying and drying a lower-layer resist on the object to be processed; and a step of applying a metal compound solution on the dried lower-layer resist. Forming a film of the metal compound solution; heat treating the lower layer resist and the film of the metal compound solution simultaneously to form an intermediate layer made of the metal compound on the lower layer resist; A step of applying and drying an upper resist, a step of heating the upper resist, a step of patterning the upper resist, and a step of patterning the intermediate layer by etching using the patterned upper resist as a mask, Patterning the lower resist by etching using the patterned intermediate layer as a mask,
Etching the film to be processed using the patterned lower resist as a mask.