JP2012239171A5 - - Google Patents

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Publication number
JP2012239171A5
JP2012239171A5 JP2012107478A JP2012107478A JP2012239171A5 JP 2012239171 A5 JP2012239171 A5 JP 2012239171A5 JP 2012107478 A JP2012107478 A JP 2012107478A JP 2012107478 A JP2012107478 A JP 2012107478A JP 2012239171 A5 JP2012239171 A5 JP 2012239171A5
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JP
Japan
Prior art keywords
modulus
modular
values
processor
operands
Prior art date
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Application number
JP2012107478A
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English (en)
Japanese (ja)
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JP5977996B2 (ja
JP2012239171A (ja
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Publication date
Priority claimed from EP11176404A external-priority patent/EP2523096A1/en
Application filed filed Critical
Publication of JP2012239171A publication Critical patent/JP2012239171A/ja
Publication of JP2012239171A5 publication Critical patent/JP2012239171A5/ja
Application granted granted Critical
Publication of JP5977996B2 publication Critical patent/JP5977996B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2012107478A 2011-05-11 2012-05-09 サイドチャンネル攻撃に対する抵抗力のあるモジュラー累乗法及び装置 Expired - Fee Related JP5977996B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP11305568 2011-05-11
EP11305568.5 2011-05-11
EP11176404.9 2011-08-03
EP11176404A EP2523096A1 (en) 2011-05-11 2011-08-03 Modular exponentiation and device resistant against side-channel attacks

Publications (3)

Publication Number Publication Date
JP2012239171A JP2012239171A (ja) 2012-12-06
JP2012239171A5 true JP2012239171A5 (enExample) 2015-06-25
JP5977996B2 JP5977996B2 (ja) 2016-08-24

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ID=44546155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012107478A Expired - Fee Related JP5977996B2 (ja) 2011-05-11 2012-05-09 サイドチャンネル攻撃に対する抵抗力のあるモジュラー累乗法及び装置

Country Status (7)

Country Link
US (1) US8984040B2 (enExample)
EP (2) EP2523096A1 (enExample)
JP (1) JP5977996B2 (enExample)
CN (1) CN102779022B (enExample)
BR (1) BR102012010971A2 (enExample)
CA (1) CA2775325A1 (enExample)
MX (1) MX2012005408A (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9645794B2 (en) * 2014-09-23 2017-05-09 Texas Instruments Incorporated Homogeneous atomic pattern for double, add, and subtract operations for digital authentication using elliptic curve cryptography
CN104811297B (zh) * 2015-04-23 2018-06-12 成都信息工程学院 针对RSA之M-ary实现模乘余数输入侧信道攻击
CN106571916B (zh) * 2015-10-12 2020-06-30 瑞昱半导体股份有限公司 解密装置、方法及电路
US10915667B2 (en) * 2016-12-21 2021-02-09 Cryptography Research, Inc. Protecting parallel multiplication operations from external monitoring attacks
EP3447509B1 (en) * 2017-08-21 2021-05-26 Eshard Method of testing the resistance of a circuit to a side channel analysis
WO2020152831A1 (ja) * 2019-01-24 2020-07-30 日本電気株式会社 情報処理装置、秘密計算方法及びプログラム
CN112260818B (zh) * 2020-10-19 2022-09-20 中国人民解放军战略支援部队信息工程大学 侧信道曲线的增强方法、侧信道攻击方法及装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2228493C (en) * 1997-02-03 2005-05-03 Nippon Telegraph And Telephone Corporation Scheme for carrying out modular calculations based on redundant binary calculation
WO2007104706A1 (fr) * 2006-03-16 2007-09-20 Gemplus Procede de securisation d'un calcul d'une exponentiation ou d'une multiplication par un scalaire dans un dispositif electronique
EP1840732A1 (en) * 2006-03-31 2007-10-03 Axalto SA Protection against side channel attacks
FR2949925A1 (fr) * 2009-09-09 2011-03-11 Proton World Int Nv Protection d'une generation de nombres premiers contre des attaques par canaux caches

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