BR102012010971A2 - Método e dispositivo de exponenciação modular resistente aos ataques de canal-lateral - Google Patents

Método e dispositivo de exponenciação modular resistente aos ataques de canal-lateral Download PDF

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Publication number
BR102012010971A2
BR102012010971A2 BRBR102012010971-9A BR102012010971A BR102012010971A2 BR 102012010971 A2 BR102012010971 A2 BR 102012010971A2 BR 102012010971 A BR102012010971 A BR 102012010971A BR 102012010971 A2 BR102012010971 A2 BR 102012010971A2
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BR
Brazil
Prior art keywords
module
modular
mod
result
operands
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BRBR102012010971-9A
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English (en)
Portuguese (pt)
Inventor
Marc Joye
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Thomson Licensing
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/722—Modular multiplication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/723—Modular exponentiation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G06F2207/7261—Uniform execution, e.g. avoiding jumps, or using formulae with the same power profile

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Storage Device Security (AREA)
  • Error Detection And Correction (AREA)
BRBR102012010971-9A 2011-05-11 2012-05-09 Método e dispositivo de exponenciação modular resistente aos ataques de canal-lateral BR102012010971A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP11305568 2011-05-11
EP11176404A EP2523096A1 (en) 2011-05-11 2011-08-03 Modular exponentiation and device resistant against side-channel attacks

Publications (1)

Publication Number Publication Date
BR102012010971A2 true BR102012010971A2 (pt) 2013-11-12

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Family Applications (1)

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BRBR102012010971-9A BR102012010971A2 (pt) 2011-05-11 2012-05-09 Método e dispositivo de exponenciação modular resistente aos ataques de canal-lateral

Country Status (7)

Country Link
US (1) US8984040B2 (enExample)
EP (2) EP2523096A1 (enExample)
JP (1) JP5977996B2 (enExample)
CN (1) CN102779022B (enExample)
BR (1) BR102012010971A2 (enExample)
CA (1) CA2775325A1 (enExample)
MX (1) MX2012005408A (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9645794B2 (en) * 2014-09-23 2017-05-09 Texas Instruments Incorporated Homogeneous atomic pattern for double, add, and subtract operations for digital authentication using elliptic curve cryptography
CN104811297B (zh) * 2015-04-23 2018-06-12 成都信息工程学院 针对RSA之M-ary实现模乘余数输入侧信道攻击
CN106571916B (zh) * 2015-10-12 2020-06-30 瑞昱半导体股份有限公司 解密装置、方法及电路
WO2018118569A1 (en) * 2016-12-21 2018-06-28 Cryptography Research, Inc. Protecting parallel multiplication operations from external monitoring attacks
EP3447509B1 (en) * 2017-08-21 2021-05-26 Eshard Method of testing the resistance of a circuit to a side channel analysis
WO2020152831A1 (ja) * 2019-01-24 2020-07-30 日本電気株式会社 情報処理装置、秘密計算方法及びプログラム
CN112260818B (zh) * 2020-10-19 2022-09-20 中国人民解放军战略支援部队信息工程大学 侧信道曲线的增强方法、侧信道攻击方法及装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175850B1 (en) * 1997-02-03 2001-01-16 Nippon Telegraph And Telephone Corporation Scheme for carrying out modular calculations based on redundant binary calculation
WO2007104706A1 (fr) * 2006-03-16 2007-09-20 Gemplus Procede de securisation d'un calcul d'une exponentiation ou d'une multiplication par un scalaire dans un dispositif electronique
EP1840732A1 (en) * 2006-03-31 2007-10-03 Axalto SA Protection against side channel attacks
FR2949925A1 (fr) * 2009-09-09 2011-03-11 Proton World Int Nv Protection d'une generation de nombres premiers contre des attaques par canaux caches

Also Published As

Publication number Publication date
CN102779022A (zh) 2012-11-14
EP2523097A1 (en) 2012-11-14
JP5977996B2 (ja) 2016-08-24
US8984040B2 (en) 2015-03-17
EP2523097B1 (en) 2016-01-20
CN102779022B (zh) 2017-03-01
US20120290634A1 (en) 2012-11-15
HK1176423A1 (en) 2013-07-26
EP2523096A1 (en) 2012-11-14
MX2012005408A (es) 2012-11-21
CA2775325A1 (en) 2012-11-11
JP2012239171A (ja) 2012-12-06

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Legal Events

Date Code Title Description
B03A Publication of an application: publication of a patent application or of a certificate of addition of invention
B08F Application fees: dismissal - article 86 of industrial property law
B08K Lapse as no evidence of payment of the annual fee has been furnished to inpi (acc. art. 87)