JP2012528391A5 - - Google Patents

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JP2012528391A5
JP2012528391A5 JP2012513148A JP2012513148A JP2012528391A5 JP 2012528391 A5 JP2012528391 A5 JP 2012528391A5 JP 2012513148 A JP2012513148 A JP 2012513148A JP 2012513148 A JP2012513148 A JP 2012513148A JP 2012528391 A5 JP2012528391 A5 JP 2012528391A5
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Japan
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signal
bias
sign
sum
output
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JP2012513148A
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JP5640081B2 (ja
JP2012528391A (ja
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Priority claimed from US12/472,715 external-priority patent/US8316071B2/en
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JP2012513148A 2009-05-27 2010-05-24 飽和を伴う整数乗算および乗算加算演算 Expired - Fee Related JP5640081B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/472,715 US8316071B2 (en) 2009-05-27 2009-05-27 Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor
US12/472,715 2009-05-27
PCT/US2010/035900 WO2010138432A1 (en) 2009-05-27 2010-05-24 Integer multiply and multiply-add operations with saturation

Publications (3)

Publication Number Publication Date
JP2012528391A JP2012528391A (ja) 2012-11-12
JP2012528391A5 true JP2012528391A5 (enExample) 2013-07-04
JP5640081B2 JP5640081B2 (ja) 2014-12-10

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JP2012513148A Expired - Fee Related JP5640081B2 (ja) 2009-05-27 2010-05-24 飽和を伴う整数乗算および乗算加算演算

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US (1) US8316071B2 (enExample)
EP (1) EP2435904B1 (enExample)
JP (1) JP5640081B2 (enExample)
KR (1) KR101560340B1 (enExample)
CN (1) CN102804128B (enExample)
WO (1) WO2010138432A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8838664B2 (en) * 2011-06-29 2014-09-16 Advanced Micro Devices, Inc. Methods and apparatus for compressing partial products during a fused multiply-and-accumulate (FMAC) operation on operands having a packed-single-precision format
WO2014105154A1 (en) * 2012-12-24 2014-07-03 Intel Corporation Systems, methods, and computer program products for performing mathematical operations
US20160179530A1 (en) * 2014-12-23 2016-06-23 Elmoustapha Ould-Ahmed-Vall Instruction and logic to perform a vector saturated doubleword/quadword add
US9836278B2 (en) * 2015-05-29 2017-12-05 Huawei Technologies Co., Ltd. Floating point computation apparatus and method
CN115480730A (zh) 2016-10-20 2022-12-16 英特尔公司 用于经融合的乘加的系统、装置和方法
US11327718B2 (en) * 2020-03-19 2022-05-10 Kabushiki Kaisha Toshiba Arithmetic circuitry for power-efficient multiply-add operations
US11720328B2 (en) * 2020-06-26 2023-08-08 Advanced Micro Devices, Inc. Processing unit with small footprint arithmetic logic unit
CN111610955B (zh) * 2020-06-28 2022-06-03 中国人民解放军国防科技大学 一种数据饱和加打包处理部件、芯片及设备
US12688010B2 (en) 2021-03-22 2026-07-21 Rebellions Inc. Processing element, neural processing device including same, and method for calculating thereof
KR102258566B1 (ko) * 2021-03-22 2021-06-01 리벨리온 주식회사 프로세싱 엘리먼트, 이의 동작 방법, 및 이를 포함하는 가속기
CN116257207B (zh) * 2022-09-08 2023-10-03 重庆位图信息技术有限公司 一种数据截位方法、模块、计算机设备及存储介质
CN116155481B (zh) * 2023-02-24 2025-05-13 长沙理工大学 一种sm3算法的数据加密实现方法和装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6211933A (ja) * 1985-07-09 1987-01-20 Nec Corp 演算回路
US5623434A (en) * 1994-07-27 1997-04-22 Chromatic Research, Inc. Structure and method of using an arithmetic and logic unit for carry propagation stage of a multiplier
US5953241A (en) * 1995-08-16 1999-09-14 Microunity Engeering Systems, Inc. Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
JP3710193B2 (ja) * 1996-03-11 2005-10-26 沖電気工業株式会社 積和演算回路
JPH1173408A (ja) * 1997-08-29 1999-03-16 Internatl Business Mach Corp <Ibm> 演算処理システム及び演算処理方法
US6223198B1 (en) * 1998-08-14 2001-04-24 Advanced Micro Devices, Inc. Method and apparatus for multi-function arithmetic
US7882165B2 (en) * 2003-12-29 2011-02-01 Xilinx, Inc. Digital signal processing element having an arithmetic logic unit
US7870182B2 (en) * 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
US20060101244A1 (en) * 2004-11-10 2006-05-11 Nvidia Corporation Multipurpose functional unit with combined integer and floating-point multiply-add pipeline
US7428566B2 (en) * 2004-11-10 2008-09-23 Nvidia Corporation Multipurpose functional unit with multiply-add and format conversion pipeline
CN101069152A (zh) 2004-12-01 2007-11-07 皇家飞利浦电子股份有限公司 具有多操作数运算电路的电子设备
US7716266B2 (en) * 2005-02-01 2010-05-11 International Business Machines Corporation Common shift-amount calculation for binary and hex floating point
JP2006227939A (ja) * 2005-02-17 2006-08-31 Matsushita Electric Ind Co Ltd 演算装置
CN100410873C (zh) * 2005-04-12 2008-08-13 威盛电子股份有限公司 分离饱和加减功能以改善处理器管线的关键执行阶段时程
US8082287B2 (en) * 2006-01-20 2011-12-20 Qualcomm Incorporated Pre-saturating fixed-point multiplier

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