JP2012235089A - パッケージキャリアおよびその製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000010410 layer Substances 0.000 claims abstract description 194
- 239000012790 adhesive layer Substances 0.000 claims abstract description 92
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 239000002184 metal Substances 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 63
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 22
- 239000010949 copper Substances 0.000 claims description 22
- 230000004308 accommodation Effects 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 description 10
- 150000001875 compounds Chemical class 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/642—Heat extraction or cooling elements characterized by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Led Device Packages (AREA)
Abstract
【解決手段】第1表面111、第2表面113、および互いに背向する第1表面111と第2表面113が連結する開口116を有する基板110が提供される。第1粘着層は基板110の第1表面111上に形成される。第1粘着層と基板110は窪みを定義する。熱伝導素子130は窪みに配置され、第1粘着層を介し窪みに固定される。第2粘着層と第2粘着層上に位置する金属層150aは基板110の第2表面113に形成される。金属層150aは熱伝導素子130の底面に接続される。熱伝導素子130は金属層150aと第1粘着層との間に位置する。第1粘着層は基板110の第1表面111を露出するために取り除かれる。
【選択図】図1I
Description
110 基板
111 第1表面
112 絶縁層
113 第2表面
114 銅層
115 パターン化銅層
116 開口
120 第1粘着層
130、130a 熱伝導素子
131 頂面
132、132a 第1伝導層
133 底面
134 絶縁材層
136 第2伝導層
140a、140b 第2粘着層
150a、150b、150c 金属層
151 表面
152 収容凹部
154 突出部
160 伝導柱
170 ソルダーマスク層
200a、200b 熱発生素子
210 モールドコンパウンド(molding compound)
220 ボンディングワイヤー
C 窪み
S1 収容空間
Claims (15)
- 第1表面、第2表面、および互いに背向する第1表面と第2表面が連結する開口を有する基板を提供することと、
前記基板の第1表面上に第1粘着層を形成し、前記第1粘着層と前記基板が窪みを定義することと、
前記窪みに熱伝導素子を配置し、前記熱伝導素子は前記第1粘着層を介し前記窪みに固定されることと、
第2粘着層と、前記第2粘着層上に位置する金属層を前記基板の第2表面上に形成し、前記金属層は前記熱伝導素子の底面に接続され、前記熱伝導素子は前記金属層と前記第1粘着層の間に位置することと、
前記第1粘着層が前記基材の前記第1表面を露出させるために取り除かれることと、
を備えるパッケージキャリアの製造方法。 - 前記基板の第2表面上に前記第2粘着層と前記金属層を形成するときに、前記第2粘着層により前記熱伝導素子の底面を覆い、前記熱伝導素子は前記第1粘着層と前記第2粘着層の間に位置することと、
前記熱伝導素子底面の一部を露出させるために前記金属層の一部と前記第2粘着層の一部を取り除くことと、
前記熱伝導素子の底面の露出された部分に複数の伝導柱を形成し、そのうち前記熱伝導素子は前記伝導柱により前記金属層に接続され、前記伝導柱の前記熱伝導素子から離れた側の表面と前記金属層の第2粘着層から離れた側の表面は実質共面であることと、
を更に備える請求項1に記載の製造方法。 - 前記第2粘着層は前記基板の第2表面と前記金属層との間に位置し、前記金属層は収容凹部を有し、前記熱伝導素子の底面は前記収容凹部に配置される請求項1に記載の製造方法。
- 前記第2粘着層は前記基板の第2表面と前記金属層との間に位置し、前記金属層は突出部を有し、前記熱伝導素子の底面は前記突出部上に配置される請求項1に記載の製造方法。
- 前記熱伝導素子は、第1伝導層、第2伝導層、および前記第1伝導層と前記第2伝導層との間に位置する絶縁層を含む請求項1に記載の製造方法。
- 前記絶縁層の材料がセラミックスである請求項5に記載の製造方法。
- 前記基板が、絶縁層と、前記絶縁層上に位置するパターン化銅層を含み、前記パターン化銅層は前記絶縁層の一部を露出し、更に、前記第1粘着層を取り除いた後、前記パターン化銅層上と前記絶縁層の一部上にソルダーマスク層を形成することを備える請求項5に記載の製造方法。
- 熱発生素子を積載するパッケージキャリアであって、
第1表面、第2表面、互いに背向する第1表面と第2表面が連結する開口を有する基板と、
前記基板の前記第2表面上に配置される粘着層と、
前記粘着層を介し前記基板に接着され、前記開口と収容空間を定義する金属層と、
収容空間に配置され、互いに背向する頂面と底面を有する熱伝導素子とを含み、
前記金属層は前記熱伝導素子の底面に接続され、前記熱発生素子は前記熱伝導素子の頂面に配置される、
パッケージキャリア。 - 前記熱伝導素子は、第1伝導層、第2伝導層、前記第1伝導層と前記第2伝導層との間に位置する絶縁層を含む請求項8に記載のパッケージキャリア。
- 前記絶縁層の材料がセラミックスである請求項9に記載のパッケージキャリア。
- 更に、複数の伝導柱を含み、
前記粘着層が、前記熱伝導素子の底面と前記金属層との間に拡張され、前記伝導柱が前記金属層と前記粘着層を貫通し前記熱伝導素子の底面の一部に接続する請求項8に記載のパッケージキャリア。 - 前記粘着層は、前記基板の第2表面と前記金属層との間に位置し、前記金属層は前記収容凹部を有し、前記熱伝導素子の底面は前記収容凹部に配置される請求項8に記載のパッケージキャリア。
- 前記粘着層は、前記基板の第2表面と前記金属層との間に位置し、前記金属層は突出部を有し、前記熱伝導素子の底面は前記突出部に配置される請求項8に記載のパッケージキャリア。
- 前記基板が、絶縁層と、前記絶縁層上に位置するパターン化銅層を含み、前記パターン化銅層が前記絶縁層の一部を露出する請求項8に記載のパッケージキャリア。
- 前記パターン化銅層上と前記絶縁層の一部上に配置されるソルダーマスク層を更に備える請求項14に記載のパッケージキャリア。
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TW100115472A TWI437930B (zh) | 2011-05-03 | 2011-05-03 | 封裝載板及其製作方法 |
TW100115472 | 2011-05-03 |
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JP2012235089A true JP2012235089A (ja) | 2012-11-29 |
JP5536814B2 JP5536814B2 (ja) | 2014-07-02 |
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US (1) | US8513530B2 (ja) |
JP (1) | JP5536814B2 (ja) |
CN (1) | CN102769076B (ja) |
TW (1) | TWI437930B (ja) |
Cited By (5)
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KR20160038359A (ko) * | 2014-09-30 | 2016-04-07 | 삼성전기주식회사 | 방열 구조체를 포함하는 회로기판 |
KR20160080826A (ko) * | 2014-12-29 | 2016-07-08 | 삼성전기주식회사 | 회로기판 및 회로기판 제조방법 |
JP2017059812A (ja) * | 2015-09-16 | 2017-03-23 | 旭徳科技股▲ふん▼有限公司 | パッケージキャリアおよびその製造方法 |
JP2023023889A (ja) * | 2021-08-06 | 2023-02-16 | 日亜化学工業株式会社 | 回路基板及び発光装置並びにそれらの製造方法 |
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US9960099B2 (en) * | 2013-11-11 | 2018-05-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thermally conductive molding compound structure for heat dissipation in semiconductor packages |
US10510707B2 (en) | 2013-11-11 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thermally conductive molding compound structure for heat dissipation in semiconductor packages |
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KR20160015980A (ko) * | 2014-08-01 | 2016-02-15 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
KR102222608B1 (ko) * | 2014-08-01 | 2021-03-05 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
KR20160038359A (ko) * | 2014-09-30 | 2016-04-07 | 삼성전기주식회사 | 방열 구조체를 포함하는 회로기판 |
KR102194720B1 (ko) * | 2014-09-30 | 2020-12-23 | 삼성전기주식회사 | 방열 구조체를 포함하는 회로기판 |
KR20160080826A (ko) * | 2014-12-29 | 2016-07-08 | 삼성전기주식회사 | 회로기판 및 회로기판 제조방법 |
KR102295105B1 (ko) * | 2014-12-29 | 2021-08-31 | 삼성전기주식회사 | 회로기판 및 회로기판 제조방법 |
JP2017059812A (ja) * | 2015-09-16 | 2017-03-23 | 旭徳科技股▲ふん▼有限公司 | パッケージキャリアおよびその製造方法 |
JP2023023889A (ja) * | 2021-08-06 | 2023-02-16 | 日亜化学工業株式会社 | 回路基板及び発光装置並びにそれらの製造方法 |
JP7401791B2 (ja) | 2021-08-06 | 2023-12-20 | 日亜化学工業株式会社 | 回路基板及び発光装置並びにそれらの製造方法 |
US12035481B2 (en) | 2021-08-06 | 2024-07-09 | Nichia Corporation | Circuit board, light emitting device, and manufacturing method thereof |
Also Published As
Publication number | Publication date |
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TW201247038A (en) | 2012-11-16 |
US20120279760A1 (en) | 2012-11-08 |
US8513530B2 (en) | 2013-08-20 |
CN102769076A (zh) | 2012-11-07 |
TWI437930B (zh) | 2014-05-11 |
CN102769076B (zh) | 2014-11-05 |
JP5536814B2 (ja) | 2014-07-02 |
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