JP2012199587A - High-breakdown-voltage semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent occurrence of snapback phenomenon.SOLUTION: A high-breakdown-voltage semiconductor device comprises: a semiconductor substrate 10; a p-type base region 11; an n-type emitter region 12; n-type cathode regions 13 and p-type collector regions 14 that are alternately disposed adjacent to an end surface of the semiconductor substrate 10 side by side and are formed toward a second primary surface 2 from a first primary surface 1 with a depth not penetrating the semiconductor substrate 10; a trench region 36 that is adjacent to the end surface of the first primary surface 1 of the semiconductor substrate 10, is formed toward the second primary surface 2 from the first primary surface 1, and isolates the n-type cathode regions 13 and the p-type collector regions 14; a control electrode 40 that faces, via an interlayer insulating film 39, the p-type base region 11 sandwiched by the semiconductor substrate 10 and the n-type emitter region 12; a first main electrode 41 that contacts the p-type base region 11 and the n-type emitter region 12; and a second main electrode that is electrically connected to the n-type cathode regions 13 and the p-type collector regions 14.

Description

  The present invention relates to a high voltage semiconductor device, and more particularly to a high voltage semiconductor device in which an IGBT or power MOSFET and a free wheel diode are formed in a single semiconductor substrate.

  In recent years, from the viewpoint of energy saving, inverter circuits have been widely used for controlling home appliances and industrial power devices. In order to control electric power, an inverter circuit repeatedly turns on or off a voltage or current by a power semiconductor device incorporated in the inverter circuit. As a power semiconductor device, an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is mainly used because of its characteristics.

  The inverter circuit often drives an inductive load such as an induction motor. In this case, back electromotive force is generated from the inductive load. For this reason, a free wheel diode is required to recirculate a current in a direction opposite to the main current such as an IGBT generated from the counter electromotive force.

  In general, an inverter circuit in which an IGBT or the like and a free-wheeling diode are connected in reverse parallel as individual components is used. However, in order to reduce the size and weight of the inverter device, development of a high-breakdown-voltage semiconductor device in which an IGBT or the like and a reflux diode are integrated into a single chip is being promoted (see Patent Documents 1 to 4 below). In the one-chip high voltage semiconductor device, for example, both the collector region of the IGBT and the cathode region of the free-wheeling diode are formed on the back surface side of the semiconductor substrate.

  By the way, in the one-chip high voltage semiconductor device, if the IGBT collector region and the reflux diode cathode region are not formed sufficiently apart on the back side of the semiconductor substrate, a snapback phenomenon occurs. To do. If the IGBT collector region and the cathode region of the free-wheeling diode are sufficiently separated on the back surface side of the semiconductor substrate, the manufacturing cost due to the decrease in performance due to the decrease in the effective area of the IGBT collector region and the increase in the chip area Invite the rise.

  In order to avoid the above performance degradation and increase in manufacturing cost, if the IGBT collector region and the diode cathode region are not sufficiently separated on the back side of the semiconductor substrate, the IGBT collector region and the free wheel diode cathode region By forming an isolation means such as a trench with an insulator embedded in between, the occurrence of the snapback phenomenon can be suppressed. However, when a separating means such as a trench in which an insulator is embedded is used, a deep groove must be formed in the thickness direction of the semiconductor substrate, resulting in an increase in manufacturing cost.

Japanese Patent Laid-Open No. 04-192366 JP 2004-363328 A JP 2007-227982 A US Patent Application Publication No. 2009/0140289

  The present invention provides a high voltage semiconductor device in which an IGBT or a power MOSFET and a free wheel diode are formed in a single semiconductor substrate, and can suppress the occurrence of a snapback phenomenon. For the purpose.

  In the high breakdown voltage semiconductor device according to the first aspect of the present invention, a first conductivity type semiconductor substrate having first and second main surfaces and the first main surface of the semiconductor substrate are formed. A first conductivity type first semiconductor region surrounded by the semiconductor substrate on one main surface, and a first conductivity type formed on the first main surface and sandwiching the first semiconductor region with the semiconductor substrate. Depths that are alternately arranged adjacent to the second semiconductor region and the end surface of the first main surface of the semiconductor substrate and do not penetrate the semiconductor substrate from the first main surface toward the second main surface. The first conductive type third semiconductor region and the second conductive type fourth semiconductor region, which are formed respectively, are adjacent to the end surface of the first main surface of the semiconductor substrate and from the first main surface to the second semiconductor region. 2 The third semiconductor region formed toward the main surface A trench region that separates the fourth semiconductor region; a control electrode that is formed to face the first semiconductor region sandwiched between the semiconductor substrate and the second semiconductor region with an interlayer insulating film interposed therebetween; A first main electrode formed in contact with both the first semiconductor region and the second semiconductor region; and a second main electrode formed electrically connected to the third semiconductor region and the fourth semiconductor region. A main electrode.

  In a high voltage semiconductor device according to a second aspect of the present invention, a first conductivity type semiconductor substrate having first and second main surfaces and the first main surface of the semiconductor substrate are formed. A first conductivity type first semiconductor region surrounded by the semiconductor substrate on one main surface, and a first conductivity type formed on the first main surface and sandwiching the first semiconductor region with the semiconductor substrate. Adjacent to the end surface of the first main surface of the semiconductor substrate and the second semiconductor region, the second semiconductor region is arranged alternately with the semiconductor substrate in between, and from the first main surface toward the second main surface. The first-conductivity-type third semiconductor region and the second-conductivity-type fourth semiconductor region each formed at a depth not penetrating the semiconductor substrate, and the first substrate sandwiched between the semiconductor substrate and the second semiconductor region. Paired with an interlayer insulating film in the semiconductor region The control electrode formed to connect the first main electrode formed in contact with both the first semiconductor region and the second semiconductor region, and the third semiconductor region and the fourth semiconductor region are connected. , A resistor or a diode, and a second main electrode electrically connected to the fourth semiconductor region.

  Preferably, the resistor or the diode is arranged on the first main surface so as to face the semiconductor substrate sandwiched between the third semiconductor region and the fourth semiconductor region with the interlayer insulating film interposed therebetween. Or disposed inside the semiconductor substrate between the third semiconductor region and the fourth semiconductor region. Preferably, a fifth semiconductor region of a second conductivity type formed on the second main surface of the semiconductor substrate, a third main electrode formed in contact with the fifth semiconductor region, and the second main electrode And connecting means for connecting the third main electrode.

According to the present invention, there is provided a high voltage semiconductor device in which an IGBT or power MOSFET and a free wheel diode are formed in a single semiconductor substrate, which can suppress the occurrence of a snapback phenomenon. Obtainable.

1 is a plan view showing a high voltage semiconductor device in Embodiment 1. FIG. It is arrow sectional drawing regarding the II-II line | wire in FIG. FIG. 10 is a plan view showing a high voltage semiconductor device in a second embodiment. It is arrow sectional drawing regarding the IV-IV line | wire in FIG. FIG. 10 is a plan view showing a high voltage semiconductor device according to another embodiment of the second embodiment. It is arrow sectional drawing regarding the VI-VI line in FIG. It is arrow sectional drawing regarding the VII-VII line in FIG. FIG. 11 is a plan view showing a high voltage semiconductor device in a third embodiment. It is arrow sectional drawing regarding the IX-IX line in FIG. FIG. 38 is a plan view showing a high voltage semiconductor device according to another mode of the third embodiment. It is arrow sectional drawing regarding the XI-XI line in FIG. It is arrow sectional drawing regarding the XII-XII line | wire in FIG. FIG. 6 is a cross-sectional view showing a high voltage semiconductor device in a fourth embodiment. FIG. 38 is a plan view showing a high voltage semiconductor device according to another mode of the fourth embodiment. It is arrow sectional drawing regarding the XV-XV line | wire in FIG. FIG. 9 is a cross-sectional view showing a high voltage semiconductor device in a fifth embodiment. It is sectional drawing which shows the high voltage semiconductor device in other forms of Embodiment 5. It is arrow sectional drawing regarding the XVIII-XVIII line | wire in FIG. It is sectional drawing which shows the high voltage semiconductor device in Embodiment 6. It is sectional drawing which shows the high voltage semiconductor device in other forms of Embodiment 6. It is sectional drawing which shows the high voltage | pressure-resistant semiconductor device in other form of Embodiment 6. FIG. FIG. 10 is a plan view showing a high voltage semiconductor device in a seventh embodiment. It is the elements on larger scale of the area | region enclosed by the XXIII line | wire in FIG. It is arrow sectional drawing regarding the XXIV-XXIV line | wire in FIG. It is arrow sectional drawing regarding the XXV-XXV line | wire in FIG. FIG. 20 is a plan view showing a high voltage semiconductor device in an eighth embodiment. It is the elements on larger scale of the area | region enclosed by the XXVII line in FIG. It is arrow sectional drawing regarding the XXVIII-XXVIII line | wire in FIG. It is arrow sectional drawing regarding the XXIX-XXIX line | wire in FIG. FIG. 29 is a plan view showing a high voltage semiconductor device according to still another embodiment of the eighth embodiment. It is arrow sectional drawing regarding the XXXI-XXXI line | wire in FIG. FIG. 38 is a plan view showing a high voltage semiconductor device according to the ninth embodiment. It is the elements on larger scale of the area | region enclosed by the XXXIII line | wire in FIG. It is arrow sectional drawing regarding the XXXIV-XXXIV line | wire in FIG. It is arrow sectional drawing regarding the XXXV-XXXV line | wire in FIG. FIG. 38 is a plan view showing a high breakdown voltage semiconductor device in the tenth embodiment. It is the elements on larger scale of the area | region enclosed by the XXXVII line in FIG. It is arrow directional cross-sectional view regarding the XXXVIII-XXXVIII line | wire in FIG. It is arrow sectional drawing regarding the XXXIX-XXXIX line | wire in FIG. It is arrow sectional drawing regarding the XL-XL line | wire in FIG.

  Hereinafter, a high voltage semiconductor device according to each embodiment of the present invention will be described with reference to the drawings. In each embodiment described below, when referring to the number, amount, and the like, the scope of the present invention is not necessarily limited to the number, amount, and the like unless otherwise specified. The same parts and corresponding parts are denoted by the same reference numerals, and redundant description may not be repeated.

[Embodiment 1]
With reference to FIG. 1 and FIG. 2, Embodiment 1 based on this invention is demonstrated. In the high breakdown voltage semiconductor device in the present embodiment, an IGBT (n-channel type) and a free wheel diode are formed in a single semiconductor substrate.

(IGBT)
With reference to FIG. 2, the IGBT formed inside the high voltage semiconductor device will be described. The IGBT includes an n-type semiconductor substrate 10, a relatively high concentration n ⁺ -type buffer region 10B, a p-type base region (first semiconductor region) 11, a relatively high concentration p ⁺ -type region 11a, A relatively high concentration n ⁺ -type emitter region (second semiconductor region) 12, a relatively high concentration p ⁺ -type collector region (fourth semiconductor region) 14, an insulating film 31, and a gate electrode (control electrode) 40. It consists of and.

The p-type base region 11 is formed in a substantially rectangular shape in plan view on the first main surface 1 of the n-type semiconductor substrate 10. The p-type base region 11 is surrounded by the semiconductor substrate 10 on the first main surface 1. A p ⁺ type region 11 a is formed on the surface of the p type base region 11. The p ⁺ type region 11a is formed in order to obtain a good ohmic connection between the p type base region 11 and a first main electrode 41 described later.

The n ⁺ -type emitter region 12 is selectively formed on the surface of the p-type base region 11. The n ⁺ -type emitter region 12 sandwiches the p-type base region 11 with the semiconductor substrate 10. In other words, the n ⁺ -type emitter region 12 is surrounded by the p-type base region 11 on the first main surface 1 of the semiconductor substrate 10.

The p ⁺ type collector region 14 is formed over the entire second main surface 2 of the semiconductor substrate 10. The n ⁺ -type buffer region 10B is formed on the opposite side of the second main surface 2 with the p ⁺ -type collector region 14 in between. The n ⁺ -type buffer region 10B can suppress the spread of the depletion layer during reverse bias as a channel stopper.

Gate electrode 40 is formed in a groove provided in first main surface 1 of semiconductor substrate 10 with insulating film 31 interposed. The insulating film 31 penetrates the p-type base region 11 in the thickness direction of the semiconductor substrate 10. The gate electrode 40 is opposed to the p-type base region 11 sandwiched between the semiconductor substrate 10 and the n ⁺ -type emitter region 12 with an insulating film 31 interposed therebetween. A portion of the p-type base region 11 sandwiched between the semiconductor substrate 10 and the n ⁺ -type emitter region 12 and facing the gate electrode 40 with the insulating film 31 forms a channel region. The gate electrode 40 and the insulating film 31 in the present embodiment constitute a trench electrode as shown in FIG. 2, but may be a so-called planar electrode formed on the surface of the semiconductor substrate 10.

  A plurality of gate electrodes 40 are formed along the first main surface 1 of the semiconductor substrate 10. Referring to FIG. 1, the gate electrodes 40 are formed in parallel with a predetermined gap therebetween (in the left-right direction in FIG. 1). The ends of each gate electrode 40 are electrically connected to each other by a gate wiring (not shown). The gate wiring is connected to the gate pad 40GP, and the gate electrodes 40 constitute a common potential. One end of the gate wire 40W is connected to the gate pad 40GP, and the other end of the gate wire 40W is connected to the gate pad 40P on the external terminal side.

Referring to FIG. 2, in the IGBT, n-type semiconductor substrate 10 and n ⁺ -type emitter region 12 serve as source / drain regions, and channel region (n-channel) of p-type base region 11 is controlled by gate electrode 40. Is done. That is, the n-type semiconductor substrate 10, the n ⁺ -type emitter region 12, the gate electrode 40, and the p-type base region 11 form a field effect transistor structure.

Further, in the IGBT, a pnp transistor structure including a p-type base region 11, an n-type semiconductor substrate 10, an n ⁺ -type buffer region 10B, and a p ⁺ -type collector region 14 is formed. The current is controlled by the field effect transistor. Thereby, the high voltage semiconductor device in the present embodiment can function as an IGBT.

(Reflux diode)
The free-wheeling diode formed inside the high breakdown voltage semiconductor device includes an n ⁺ -type cathode region (third semiconductor region) 13, an n-type semiconductor substrate 10, a p-type base region 11, and a relatively high concentration of p. ^{And a +} -type region 11a. The n-type semiconductor substrate 10, the p-type base region 11, and the p ⁺ -type region 11a are shared by the IGBT and the free-wheeling diode formed inside the high-voltage semiconductor device.

The n ⁺ -type cathode region 13 is formed adjacent to the end surface of the semiconductor substrate 10 from the first main surface 1 toward the second main surface 2. The n ⁺ -type cathode region 13 is formed with a depth that does not penetrate the semiconductor substrate 10 in the thickness direction. The n ⁺ -type cathode region 13 can also suppress the spread of the depletion layer during forward bias as a channel stopper.

The n ⁺ type cathode region 13 and the n type semiconductor substrate 10 constitute an n type region as a diode, and the p type base region 11 and the p ⁺ type region 11a constitute a p type region as a diode. ing. A pn junction structure is formed between the n-type region and the p-type region. Thereby, the freewheeling diode can function as a diode.

(Electric field relaxation means)
On the first main surface 1 of the semiconductor substrate 10, an electric field relaxation means 20 is formed between the p-type base region 11 and the n ⁺ -type cathode region 13. Referring to FIG. 1, electric field relaxation means 20 in the present embodiment has a planar field plate structure. The electric field relaxation means 20 is provided in an annular shape so as to surround a region where the IGBT is formed (see FIG. 1).

  Referring to FIG. 2, electric field relaxation means 20 having a planar field plate structure includes an interlayer insulating film 39, a plurality of conductive films 48, and a plurality of conductive films 49. Each conductive film 48 and each conductive film 49 are at a floating potential.

  The interlayer insulating film 39 is formed on the first main surface 1 of the semiconductor substrate 10. Each conductive film 49 is formed in an annular shape inside the interlayer insulating film 39. Each conductive film 49 is formed with a predetermined gap in the normal direction. Each conductive film 49 is covered with an interlayer insulating film 39, and each conductive film 49 is insulated from each other by the interlayer insulating film 39.

  Each conductive film 48 is formed in a ring shape on the surface of the interlayer insulating film 39 located between the adjacent conductive films 49 and 49. Each conductive film 48 is formed so as to straddle the adjacent conductive films 49, 49 in plan view. The conductive films 48 are formed with a predetermined gap therebetween in the normal direction.

(Main electrode)
On the first main surface 1 of the semiconductor substrate 10, an interlayer insulating film 31 </ b> A is formed so as to cover the gate electrode 40. A first main electrode 41 is formed on the first main surface 1 of the semiconductor substrate 10 from above the interlayer insulating film 31A. The gate electrode 40 and the first main electrode 41 are insulated by the interlayer insulating film 31A.

The first main electrode 41 is formed in contact with both the p ⁺ type region 11 a and the n ⁺ type emitter region 12. The first main electrode 41 is formed so as to cover a part of the interlayer insulating film 39 constituting the electric field relaxation means 20 (the left end portion of the interlayer insulating film 39 in FIG. 2).

Referring to FIG. 1, a first main electrode 41 is connected to one end of emitter wire 41W, and emitter pad 41P is connected to the other end of emitter wire 41W. Referring to FIGS. 1 and 2, first main electrode 41 is connected to p ⁺ type region 11a, p type base region 11 and n ⁺ type emitter region 12 through emitter pad 41P and emitter wire 41W (reference). ) An electrode for applying a potential.

With reference to FIG. 2, second main electrode 42 ^</ b ^> P is formed in contact with p ⁺ -type collector region 14 formed on second main surface 2 of semiconductor substrate 10. The second main electrode 42P functions as a collector pad. The second main electrode 42P is an electrode that applies a (high) potential to the p ⁺ -type collector region 14.

The third main electrode 43 is formed to extend in an opening (contact hole) formed in the interlayer insulating film 39 and is in contact with the surface side of the n ⁺ -type cathode region 13. The third main electrode 43 is an electrode that applies a (high) potential to the n ⁺ -type cathode region 13. The second main electrode 42P and the third main electrode 43 are electrically connected by connection means 42W such as a conductive wire.

  When the high voltage semiconductor device according to the present embodiment functions as an IGBT, the first main electrode 41 corresponds to an emitter electrode, the second main electrode 42P corresponds to a collector electrode, and the gate electrode 40 corresponds to a gate electrode. To do.

  When the high voltage semiconductor device in the present embodiment functions as a (reflux) diode, the first main electrode 41 corresponds to an anode electrode, and the third main electrode 43 corresponds to a cathode electrode.

Here, as described above, the n ⁺ -type cathode region 13 is adjacent to the end surface of the semiconductor substrate 10 and does not penetrate the semiconductor substrate 10 in the thickness direction from the first main surface 1 toward the second main surface 2. It is formed with depth. Further, the n ⁺ -type cathode region 13 is in contact with the third main electrode 43, and the second main electrode 42P and the third main electrode 43 are electrically connected by connection means 42W such as a conductive wire.

The n ⁺ -type cathode region 13 is formed adjacent to the end surface of the semiconductor substrate 10 at a depth that does not penetrate the semiconductor substrate 10 from the first main surface 1 toward the second main surface 2. The resistance R2 between the type base region 11 and the n ⁺ type cathode region 13 is larger than the resistance R1 between the p type base region 11 and the p ⁺ type collector region 14.

(Action / Effect)
With reference to FIG. 2, the on-operation of the IGBT will be described. A positive collector voltage is applied between the first main electrode 41 and the second main electrode 42P. In this state, a predetermined positive gate voltage is applied between the first main electrode 41 and the gate electrode 40, and the gate is turned on. At this time, the channel region of the p-type base region 11 is inverted from p-type to n-type to form a channel region.

Electrons are injected from the first main electrode 41 into the n-type semiconductor substrate 10 through the channel region. The injected electrons cause the p ⁺ -type collector region 14 and the n-type semiconductor substrate 10 to be in a forward bias state, and holes are injected from the p ⁺ -type collector region 14 into the n-type semiconductor substrate 10. . As a result, the resistance of the n-type semiconductor substrate 10 is greatly reduced (so-called conductivity modulation), the on-resistance of the IGBT is greatly reduced, and a current flows in the direction of the arrow AR1.

The IGBT off operation (turn-off) will be described. In the on state, a positive gate voltage is applied between the first main electrode 41 and the gate electrode 40. When this gate voltage is set to zero or negative (reverse bias), the channel region of the p-type base region 11 inverted to the n-type returns to the p-type, and electrons are injected from the first main electrode 41 into the semiconductor substrate 10. Stop. By this stop, the injection of holes from the p ⁺ type collector region 14 into the semiconductor substrate 10 is also stopped, and no current flows in the direction of the arrow AR1.

  Thereafter, the electrons and holes accumulated in the n-type semiconductor substrate 10 are recovered to the second main electrode 42P and the first main electrode 41, respectively, or recombined with each other to disappear. To do.

The ON operation of the free wheel diode will be described. As described above, the free-wheeling diode has a pn junction structure including the n ⁺ type cathode region 13 and the n type semiconductor substrate 10, the p type base region 11 and the p ⁺ type region 11a. When a forward bias (anode voltage) exceeding a predetermined threshold is applied between the first main electrode 41 and the third main electrode 43, the n-type semiconductor substrate 10 is positively connected from the p-type base region 11. Holes are injected, and electrons are injected from the n ⁺ -type cathode region 13. As a result, the forward voltage is significantly reduced, and a current flows in the direction of the arrow AR2.

The off operation of the freewheeling diode will be described. After the forward voltage is applied to the freewheeling diode (on state), when the voltage is switched in the reverse direction (off state), a current in the reverse direction of the arrow AR2 flows for a predetermined time (recovery operation). The n ⁺ -type cathode region 13 suppresses the injection of minority carriers (holes) into the n-type semiconductor substrate 10 and shortens the turn-off time of the IGBT.

  Therefore, it is equivalent to a circuit in which an IGBT and a diode are connected in antiparallel between the first main electrode 41 and the second main electrode 42P and between the first main electrode 41 and the third main electrode 43. Become. That is, the high voltage semiconductor device in this embodiment has a function as a circuit in which an IGBT and a free wheel diode are connected in antiparallel.

As described above, the n ⁺ -type cathode region 13 is adjacent to the end surface of the semiconductor substrate 10 and does not penetrate the semiconductor substrate 10 in the thickness direction from the first main surface 1 toward the second main surface 2. Is formed. According to the high voltage semiconductor device in the present embodiment, the n ⁺ type cathode region 13 is formed on the p ⁺ type collector region 14 side of the IGBT (the back surface of the semiconductor substrate 10 (the second main surface 2 side)). Compared to the case, a sufficient distance is secured between the p ⁺ type collector region 14 of the IGBT and the n ⁺ type cathode region 13 of the freewheeling diode.

According to the high breakdown voltage semiconductor device in the present embodiment, the resistance R2 between the p-type base region 11 and the n ⁺ -type cathode region 13 is the resistance between the p-type base region 11 and the p ⁺ -type collector region 14. It is larger than R1, and the occurrence of the snapback phenomenon is suppressed. Since a sufficient distance is secured between the p ⁺ type collector region 14 of the IGBT and the n ⁺ type cathode region 13 of the free-wheeling diode, the occurrence of the snapback phenomenon is suppressed without increasing the chip area, and the manufacturing cost is increased. The rise of is also suppressed.

Further, the n ⁺ -type cathode region 13 is formed adjacent to the end surface of the semiconductor substrate 10 so as not to penetrate the semiconductor substrate 10 in the thickness direction from the first main surface 1 toward the second main surface 2. As a result, the effective area of the p ⁺ -type collector region 14 of the IGBT does not decrease, and the performance as a high breakdown voltage semiconductor device does not deteriorate.

[Other Embodiments of Embodiment 1]
With reference to FIG. 2, another embodiment of the first embodiment will be described. In the high breakdown voltage semiconductor device of the first embodiment, the lifetime LT1 between the p-type base region 11 and the p ⁺ -type collector region 14 is between the p-type base region 11 and the n ⁺ -type cathode region 13. It may be different from the lifetime LT2.

  At the time of turning off (turning off) the IGBT formed inside the high breakdown voltage semiconductor device, as described in the first embodiment, electrons and holes accumulated in the n-type semiconductor substrate 10 (holes). ) Are recovered to the second main electrode 42P and the first main electrode 41, respectively, or recombine with each other to disappear.

  When the IGBT is turned off, the average time until electrons and holes recombine and disappear is the lifetime (minority carrier lifetime).

In order to make the lifetime LT1 and the lifetime LT2 different, for example, the semiconductor substrate 10 (or the p-type base region 11 and the p ⁺ -type collector region between the p-type base region 11 and the n ⁺ -type cathode region 13 is used. 14 may be irradiated locally with an electron beam, proton, helium, or the like. Further, the semiconductor substrate 10 may be irradiated with an electron beam, proton, helium, or the like using masking or the like.

  Since the lifetime LT1 and the lifetime LT2 are different, the characteristics of the IGBT and the free wheel diode formed inside the high voltage semiconductor device can be controlled independently.

[Embodiment 2]
A second embodiment based on the present invention will be described with reference to FIG. 3 and FIG. The high withstand voltage semiconductor device according to the present embodiment and the high withstand voltage semiconductor device according to the first embodiment are different in configuration between the electric field relaxation means 20 and the n ⁺ -type cathode region 13. It is substantially the same.

Referring to FIG. 4, electric field relaxation means 20 in the present embodiment has a field contact ring structure. Specifically, the electric field relaxation means 20 having a field contact structure is composed of a plurality of p ⁺ -type regions (fifth semiconductor regions) 15 having a relatively high concentration.

Each p ⁺ type region 15 is formed with a depth of 15D from the first main surface 1 to the second main surface 2 of the semiconductor substrate 10. Each p ⁺ type region 15 is formed in an annular shape inside the semiconductor substrate 10 and surrounds the region where the IGBT is formed (see FIG. 3). The p ⁺ -type regions 15 are spaced apart from each other in the normal direction and have a floating potential.

A conductive film 48 may be formed on the surface side of the p ⁺ -type region 15 with an interlayer insulating film 39 interposed therebetween. The conductive film 48 is formed extending in the opening formed in the interlayer insulating film 39 and is in contact with the surface side of the p ⁺ -type region 15. A plurality of conductive films 48 are formed annularly along each p ⁺ -type region 15. By forming the conductive film 48 on the surface side of the p ⁺ -type region 15, the depletion layer can be extended more stably. Since the potential difference between the front surface and the back surface of the interlayer insulating film 39 is reduced, it is possible to further ensure the breakdown voltage characteristics as a high breakdown voltage semiconductor device.

The n ⁺ -type cathode region 13 in the present embodiment is formed adjacent to the end surface of the semiconductor substrate 10 from the first main surface 1 toward the second main surface 2. The n ⁺ -type cathode region 13 is formed with a depth (13D) that does not penetrate the semiconductor substrate 10 in the thickness direction. The depth 13D of the n ⁺ -type cathode region 13 in the present embodiment is set deeper than the depth 15D of the p ⁺ -type region 15.

n ⁺ -type for the depth 13D of the cathode region 13 is deeper than the depth 15D of the ^{p +} -type region 15, ^{n +} -type cathode region 13 and the n-type semiconductor substrate 10, p-type base region 11 and the ^{p +} -type region The current path as a free-wheeling diode flowing between 11a is shortened. Therefore, according to the high breakdown voltage semiconductor device of the present embodiment, the current path as the free wheel diode is shortened, so that the performance as the free wheel diode can be improved.

As described in the other embodiments of the first embodiment, the lifetime LT1 between the p-type base region 11 and the p ⁺ -type collector region 14 is the same as that between the p-type base region 11 and the n ⁺ -type cathode region 13. It may be different from the lifetime LT2 between. Each characteristic of the IGBT and the freewheeling diode formed inside the high voltage semiconductor device can be independently controlled.

[Other Embodiments of Embodiment 2]
Another embodiment of the second embodiment will be described with reference to FIGS. The high breakdown voltage semiconductor device according to the other embodiment and the high breakdown voltage semiconductor device according to the second embodiment are different in configuration between the electric field relaxation means 20 and the n ⁺ -type cathode region 13. It is substantially the same.

Referring to FIG. 6, electric field relaxation means 20 in the present embodiment has a field contact ring structure (plurality of p ⁺ -type regions 15), as in the second embodiment.

Referring to FIG. 5, each p ⁺ type region 15 in the present embodiment is provided in a broken line shape in the circumferential direction surrounding the region where the IGBT is formed (p type base region 11). That is, each p ⁺ -type region 15 includes a portion formed as the p ⁺ -type region 15 (portion shown in FIG. 6) and a portion not formed as the p ⁺ -type region 15 (portion shown in FIG. 7) in the circumferential direction. ).

Similar to the second embodiment, a conductive film 48 may be formed on the surface side of each p ⁺ type region 15. A plurality of conductive films 48 are formed annularly along each p ⁺ -type region 15. The conductive film 48 has a portion formed as the p ⁺ -type region 15, may be formed on both a single continuous annular along with the p ⁺ -type region 15 is not formed partially as Not limited to this. The conductive film 48 is formed only above the portion formed as the p ⁺ -type region 15, in the circumferential direction in the same manner as the p ⁺ -type region 15 may be provided like a dashed line.

The n ⁺ -type cathode region 13 in the present embodiment is formed adjacent to the end surface of the semiconductor substrate 10 from the first main surface 1 toward the second main surface 2. The n ⁺ -type cathode region 13 is formed with a depth that does not penetrate the semiconductor substrate 10 in the thickness direction. The depth of the n ⁺ -type cathode region 13 in the present embodiment, unlike the second embodiment, may be deeper than the depth of the p ⁺ -type region 15, even shallower than the depth of the p ⁺ -type region 15 It may be the same as the depth of the p ⁺ type region 15.

A plurality of p ⁺ -type regions 15 constituting the electric field relaxation means 20, because it is provided in broken-line in the circumferential direction surrounding the region (p-type base region 11) where IGBT is formed as p ⁺ -type region 15 In a portion not formed (portion shown in FIG. 7), a current as a free-wheeling diode flows between the n ⁺ -type cathode region 13 and the n-type semiconductor substrate 10 and the p-type base region 11 and the p ⁺ -type region 11a. The route becomes shorter. According to the high voltage semiconductor device in the present embodiment, the performance as a free wheel diode can be improved.

The depth of the n ⁺ -type cathode region 13 may be set deeper than the depth of the p ⁺ -type region 15 as in the second embodiment. According to this configuration, even in the portion formed as the p ⁺ -type region 15 (the portion shown in FIG. 6), the current path as the freewheeling diode is shortened, and the performance as the freewheeling diode can be improved.

[Embodiment 3]
A third embodiment based on the present invention will be described with reference to FIG. 8 and FIG. The high withstand voltage semiconductor device according to the present embodiment and the high withstand voltage semiconductor device according to the second embodiment are different in configuration between the electric field relaxation means 20 and the n ⁺ -type cathode region 13. It is substantially the same.

  Referring to FIG. 9, electric field relaxation means 20 in the present embodiment has a trench type field plate structure. Specifically, the electric field relaxation means 20 having a trench type field plate structure is composed of a plurality of first trench regions 50.

  Each first trench region 50 has a conductive layer 51 and an insulating film 52. The conductive layer 51 is formed in a groove provided in the first main surface 1 of the semiconductor substrate 10 with an insulating film 52 interposed. The conductive layer 51 is surrounded by an insulating film 52, and the conductive layer 51 and the semiconductor substrate 10 are insulated by the insulating film 52.

  Each first trench region 50 is formed with a depth of 50D from the first main surface 1 to the second main surface 2 of the semiconductor substrate 10. Each first trench region 50 is formed in an annular shape inside the semiconductor substrate 10 and surrounds the region where the IGBT is formed (see FIG. 8). The first trench regions 50 are spaced from each other in the normal direction and have a floating potential.

  A conductive film 48 may be formed on the surface side of the first trench region 50 with an interlayer insulating film 39 interposed therebetween. In this case, the conductive film 48 is formed in a ring shape on the surface of the interlayer insulating film 39 located between the adjacent first trench regions 50 and 50. The conductive film 48 is formed so as to straddle the adjacent first trench regions 50 and 50 in a plan view. The conductive films 48 are spaced apart from each other in the normal direction. By forming the conductive film 48 on the surface side of the first trench region 50, it is possible to further ensure the breakdown voltage characteristics as a high breakdown voltage semiconductor device. In the figure, the conductive film 48 and the conductive layer 51 are insulated by an interlayer insulating film 39. However, an opening is provided in the interlayer insulating film 39, and the conductive film 48 and the conductive layer 51 in the first trench region 50 are in contact with each other. You may comprise.

The n ⁺ -type cathode region 13 in the present embodiment is formed adjacent to the end surface of the semiconductor substrate 10 from the first main surface 1 toward the second main surface 2. The n ⁺ -type cathode region 13 is formed with a depth (13D) that does not penetrate the semiconductor substrate 10 in the thickness direction. The depth 13D of the n ⁺ -type cathode region 13 in the present embodiment is set deeper than the depth 50D of the first trench region 50.

Since the depth 13D of n ⁺ -type cathode region 13 is deeper than the depth 50D of the first trench region 50, ^{n +} -type cathode region 13 and the n-type semiconductor substrate 10, p-type base region 11 and the ^{p +} -type region The current path as a free-wheeling diode flowing between 11a is shortened. Therefore, according to the high breakdown voltage semiconductor device of the present embodiment, the current path as the free wheel diode is shortened, so that the performance as the free wheel diode can be improved.

As described in the other embodiments of the first embodiment, the lifetime LT1 between the p-type base region 11 and the p ⁺ -type collector region 14 is the same as that between the p-type base region 11 and the n ⁺ -type cathode region 13. It may be different from the lifetime LT2 between. Each characteristic of the IGBT and the freewheeling diode formed inside the high voltage semiconductor device can be independently controlled.

[Other Embodiments of Embodiment 3]
With reference to FIGS. 10-12, the other form of Embodiment 3 is demonstrated. The high withstand voltage semiconductor device according to the other embodiment and the high withstand voltage semiconductor device according to the third embodiment are different in configuration between the electric field relaxation means 20 and the n ⁺ -type cathode region 13. It is substantially the same.

  Referring to FIG. 11, electric field relaxation means 20 in the present embodiment has a trench type field plate structure (a plurality of first trench regions 50), as in the third embodiment.

  Referring to FIG. 10, each first trench region 50 in the present embodiment is provided in a broken line shape in the circumferential direction surrounding the region where the IGBT is formed (p-type base region 11). That is, each first trench region 50 has a portion formed as the first trench region 50 (portion shown in FIG. 11) and a portion not formed as the first trench region 50 (portion shown in FIG. 12) in the circumferential direction. ).

  As in the third embodiment, a conductive film 48 may be formed on the surface side of each first trench region 50 with an interlayer insulating film 39 interposed therebetween. A plurality of conductive films 48 are annularly formed along each first trench region 50. The conductive film 48 may be formed in one continuous annular shape along both the portion formed as the first trench region 50 and the portion not formed as the first trench region 50. Not limited to this. The conductive film 48 may be formed only above the portion formed as the first trench region 50, and may be provided in a broken line shape like the first trench regions 50 in the circumferential direction.

The n ⁺ -type cathode region 13 in the present embodiment is formed adjacent to the end surface of the semiconductor substrate 10 from the first main surface 1 toward the second main surface 2. The n ⁺ -type cathode region 13 is formed with a depth that does not penetrate the semiconductor substrate 10 in the thickness direction. Unlike the third embodiment, the depth of the n ⁺ -type cathode region 13 in the present embodiment may be deeper than the depth of the first trench region 50 or may be shallower than the depth of the first trench region 50. It may be the same as the depth of the first trench region 50.

The plurality of first trench regions 50 constituting the electric field relaxation means 20 are provided in a broken line shape in the circumferential direction surrounding the region where the IGBT is formed (p-type base region 11). In a portion not formed (portion shown in FIG. 12), a current as a free-wheeling diode flows between the n ⁺ -type cathode region 13 and the n-type semiconductor substrate 10 and the p-type base region 11 and the p ⁺ -type region 11a. The route becomes shorter. According to the high voltage semiconductor device in the present embodiment, the performance as a free wheel diode can be improved.

The depth of the n ⁺ -type cathode region 13 may be set deeper than the depth of the first trench region 50 as in the third embodiment. According to this configuration, also in the portion formed as the first trench region 50 (portion shown in FIG. 11), the current path as the freewheeling diode is shortened, and the performance as the freewheeling diode can be improved.

[Embodiment 4]
A fourth embodiment based on the present invention will be described with reference to FIG. The high voltage semiconductor device in the present embodiment and the high voltage semiconductor device in the second embodiment are different in connection means 42W, and the other configurations are substantially the same. FIG. 13 corresponds to FIG. 4 in the second embodiment.

The connection means 42W in the present embodiment includes a conductive wire 71 and a resistor 72 formed on the surface of the second main electrode 42P. Resistor 72, the conductive film 72M, a relatively high concentration of ^{n +} -type regions 72da, relatively low concentration of n ^- consists type region 72 dB, and by relatively laminated high-concentration ^{n +} -type region 72Dc sequentially ing. The conductive film 72M, the n ⁺ type region 72Da, the n ⁻ type region 72Db, and the n ⁺ type region 72Dc are electrically connected to each other.

One end of the conductive wire 71 and the third main electrode 43 are connected, and the other end of the conductive wire 71 and the surface of the conductive film 72M of the resistor 72 are connected. The n ⁺ type region 72Dc of the resistor 72 is in contact with the surface of the second main electrode 42P. Thus, the second main electrode 42P and the third main electrode 43 are electrically connected by the connecting means 42W.

  Since the connecting means 42W that electrically connects the second main electrode 42P and the third main electrode 43 includes the resistor 72, the resistance on the cathode side of the freewheeling diode increases. According to the high voltage semiconductor device in the present embodiment, it is possible to further suppress the occurrence of the snapback phenomenon.

  In addition, although the structure of the connection means 42W in this Embodiment was demonstrated based on the structure applied to the high voltage semiconductor device in Embodiment 2, it is not restricted to this. The configuration of connection means 42W in the present embodiment can also be applied to the high voltage semiconductor device in the first or third embodiment.

[Other Embodiments of Embodiment 4]
With reference to FIGS. 14 and 15, another embodiment of the fourth embodiment will be described. The high breakdown voltage semiconductor device according to the other embodiment and the high breakdown voltage semiconductor device according to the fourth embodiment are different in configuration in connection means 42W, and the other configurations are substantially the same.

Referring to FIG. 15, resistor 72 in the present embodiment is formed on first main surface 1 of semiconductor substrate 10 with interlayer insulating film 39 interposed therebetween. The resistor 72 is located on the opposite side of the n ⁺ -type cathode region 13 with the interlayer insulating film 39 interposed therebetween.

The third main electrode 43 and the n ⁺ type region 72Dc are formed in contact with each other. One end of the conductive wire 71 is in contact with the surface of the conductive film 72M. The other end of the conductive wire 71 and the second main electrode 42P are connected. Thus, the second main electrode 42P and the third main electrode 43 are electrically connected by the connecting means 42W.

  According to the high breakdown voltage semiconductor device in the present embodiment, the resistor 72 is formed on the first main surface 1 of the semiconductor substrate 10 (with the interlayer insulating film 39 interposed therebetween), so that the entire system of the high breakdown voltage semiconductor device is obtained. It becomes possible to achieve downsizing.

[Embodiment 5]
A fifth embodiment based on the present invention will be described with reference to FIG. The high voltage semiconductor device in the present embodiment and the high voltage semiconductor device in the second embodiment are different in connection means 42W, and the other configurations are substantially the same. FIG. 16 corresponds to FIG. 4 in the second embodiment.

The connection means 42W in the present embodiment includes a conductive wire 71 and a diode 73 formed on the surface of the second main electrode 42P. The diode 73 is configured by sequentially stacking a conductive film 73M, a relatively high concentration p ⁺ type region 73Da, a relatively low concentration n ⁻ type region 73Db, and a relatively high concentration n ⁺ type region 73Dc. Yes. The conductive film 73M, the p ⁺ type region 73Da, the n ⁻ type region 73Db, and the n ⁺ type region 73Dc are electrically connected to each other.

One end of the conductive wire 71 and the third main electrode 43 are connected, and the other end of the conductive wire 71 and the surface of the conductive film 73M of the diode 73 are connected. The n ⁺ type region 73Dc of the diode 73 is in contact with the surface of the second main electrode 42P. Thus, the second main electrode 42P and the third main electrode 43 are electrically connected by the connecting means 42W.

  Since the connecting means 42W for electrically connecting the second main electrode 42P and the third main electrode 43 includes the diode 73, the resistance on the cathode side of the reflux diode increases. According to the high voltage semiconductor device in the present embodiment, it is possible to further suppress the occurrence of the snapback phenomenon.

  In addition, although the structure of the connection means 42W in this Embodiment was demonstrated based on the structure applied to the high voltage semiconductor device in Embodiment 2, it is not restricted to this. The configuration of connection means 42W in the present embodiment can also be applied to the high voltage semiconductor device in the first or third embodiment.

[Other Embodiments of Embodiment 5]
With reference to FIGS. 17 and 18, another embodiment of the fifth embodiment will be described. The high breakdown voltage semiconductor device according to the other embodiment and the high breakdown voltage semiconductor device according to the fifth embodiment are different in configuration in connection means 42W, and the other configurations are substantially the same.

Referring to FIG. 18, diode 73 in the present embodiment is formed on first main surface 1 of semiconductor substrate 10 with interlayer insulating film 39 interposed therebetween. The diode 73 is located on the opposite side of the n ⁺ -type cathode region 13 with the interlayer insulating film 39 interposed therebetween.

The third main electrode 43 and the p ⁺ type region 73Da are formed in contact with each other. One end of the conductive wire 71 is in contact with the surface of the conductive film 73M. The other end of the conductive wire 71 and the second main electrode 42P are connected. Thus, the second main electrode 42P and the third main electrode 43 are electrically connected by the connecting means 42W.

  According to the high voltage semiconductor device in the present embodiment, the diode 73 is formed on the first main surface 1 of the semiconductor substrate 10 (with the interlayer insulating film 39 interposed therebetween), so that the entire system of the high voltage semiconductor device is It is possible to reduce the size.

[Embodiment 6]
With reference to FIG. 19, Embodiment 6 based on this invention is demonstrated. The high breakdown voltage semiconductor device in the present embodiment is different from the high breakdown voltage semiconductor device in the second embodiment in that it further includes a second trench region 60, and the other configurations are substantially the same. FIG. 19 corresponds to FIG. 4 in the second embodiment.

  The second trench region 60 in the present embodiment has a conductive layer 61 and an insulating film 62. The conductive layer 61 is formed in a groove provided in the first main surface 1 of the semiconductor substrate 10 with an insulating film 62 interposed. The conductive layer 61 is surrounded by an insulating film 62, and the conductive layer 61 is insulated from the semiconductor substrate 10 and the p-type base region 11 by the insulating film 62. The thickness of the insulating film 62 constituting the second trench region 60 is preferably set to be relatively thick. In the p-type base region 11A including the channel region (details will be described below), it becomes difficult to invert as a channel, and the occurrence of the snapback phenomenon can be further suppressed.

  Second trench region 60 is formed to penetrate p-type base region 11 in the thickness direction of semiconductor substrate 10 from first main surface 1 of semiconductor substrate 10. The second trench region 60 is formed at a position where both sides of the second trench region 60 are sandwiched in the first main surface 1 by the p-type base region 11 (11A, 11B) by penetrating the p-type base region 11. Yes.

As described above, a channel region is formed in a portion of p-type base region 11 sandwiched between semiconductor substrate 10 and n ⁺ -type emitter region 12 and facing gate electrode 40 and insulating film 31. In the high voltage semiconductor device according to the present embodiment (and the first to fifth embodiments), a plurality of gate electrodes 40, p-type base regions 11, and n ⁺ -type emitter regions 12 are formed inside the semiconductor substrate 10. A plurality of channel regions are also formed.

The second trench region 60 is located further on the n ⁺ -type cathode region 13 side than the region where the plurality of channel regions are formed. The second trench region 60 separates the p-type base region 11 penetrated by the second trench region 60 into a p-type base region 11A including a channel region and a p-type base region 11B not including a channel region. ing. The p-type base region 11 </ b> A and the p-type base region 11 </ b> B are electrically connected by the first main electrode 41 while being separated by the second trench region 60.

The p-type base region 11 </ b> A and the p-type base region 11 </ b> B may be electrically connected by another connection means such as another resistor in a state where they are separated by the second trench region 60. The second trench region 60 is disposed further on the n ⁺ -type cathode region 13 side than the region where the plurality of channel regions are formed, and is parallel to each gate electrode 40 and each gate electrode 40. A plurality of both sides may be formed. The second trench region 60 is disposed on the n ⁺ -type cathode region 13 side further than the region where the plurality of channel regions are formed, and in addition, all the gate electrodes 40 are parallel to each gate electrode 40. It may be formed respectively on both sides of.

  A third trench region 63 may be further formed in the p-type base region 11B not including the channel region. The third trench region 63 has a conductive layer 64 and an insulating film 65. The conductive layer 64 is formed in a groove provided in the first main surface 1 of the semiconductor substrate 10 with an insulating film 65 interposed. The conductive layer 64 is surrounded by an insulating film 65, and the conductive layer 64 is insulated from the semiconductor substrate 10 and the p-type base region 11 </ b> B by the insulating film 65.

  The impurity concentration of the p-type base region 11A including the channel region is preferably set lower than the impurity concentration of the p-type base region 11B not including the channel region. Even if the anode potential of the freewheeling diode is increased, the p-type base region 11B not including the channel region is not inverted as a channel by the potential of the second trench region 60, so that the occurrence of the snapback phenomenon is further suppressed. Can do.

  The depth 60 </ b> D of the second trench region 60 is formed to extend deeper than the depth 11 </ b> AD of the p-type base region 11 so as to penetrate at least the p-type base region 11.

  The gate electrode 40 and the insulating film 31 in the present embodiment constitute a trench electrode. In the present embodiment, the depth 60D of the second trench region 60 may be formed so as to extend deeper than the depth 40D of the trench electrode. More preferably, as shown in FIG. 19, the second trench region 60 may be formed to extend to a substantially central position in the thickness direction of the semiconductor substrate 10.

  When gate electrode 40 and insulating film 31 are formed as planar electrodes on first main surface 1 of semiconductor substrate 10, the p-type base region is provided so as to penetrate at least p-type base region 11. 11 may be formed so as to extend deeper than 11 AD. Also in this case, more preferably, as shown in FIG. 19, the second trench region 60 may be formed so as to extend to a substantially central position in the thickness direction of the semiconductor substrate 10.

According to the high breakdown voltage semiconductor device in the present embodiment, the p-type base region 11B located closer to the n ⁺ -type cathode region 13 than the second trench region 60 is independent as the anode of the freewheeling diode even when the IGBT is turned on. And function. That is, it is possible to operate (turn on) the free wheel diode independently even when the IGBT is on.

This will be described more specifically. The IGBT emitter (n ⁺ -type emitter region 12) and the anode (p-type base region 11) of the freewheeling diode are set to a positive potential by the first main electrode 41, and the IGBT collector (p ⁺ -type collector region 14) is the second main electrode. 42P is set to 0 V, and the gate of the IGBT (gate electrode 40) is set to a positive potential.

By forming the second trench region 60, the IGBT emitter (n ⁺ -type emitter region 12), the IGBT channel region (p-type base region 11 A), and the free-wheeling diode cathode (n ⁺ -type cathode region 13). The resistance of the current path in the direction of the arrow AR2 passing through the anode AR (p-type base region 11B) and the resistance of the current path in the direction of the arrow AR3 passing through the cathode (n ⁺ type cathode region 13) of the free-wheeling diode. Get higher.

For this reason, the MOS operation in the IGBT is suppressed, and the free wheel diode can be operated (turned on) independently even when the IGBT is turned on. According to the above configuration, in the direction of the arrow AR1 passing through the IGBT collector (p ⁺ -type collector region 14), the IGBT channel region (p-type base region 11A), and the IGBT emitter (n ⁺ -type emitter region 12). The resistance of the current path remains unchanged or becomes low.

  A case where the second trench region 60 and the p-type base region 11B are not formed will be described. In this case, when the IGBT is turned on, it is difficult to operate (turn on) the free wheel diode independently.

This will be described more specifically. The IGBT emitter (n ⁺ -type emitter region 12) and the anode (p-type base region 11) of the freewheeling diode are set to a positive potential by the first main electrode 41, and the IGBT collector (p ⁺ -type collector region 14) is the second main electrode. 42P is set to 0 V, and the gate of the IGBT (gate electrode 40) is set to a positive potential.

The resistance of the current path in the direction of the arrow AR2 passing through the IGBT emitter (n ⁺ -type emitter region 12), the IGBT channel region (p-type base region 11A), and the cathode (n ⁺ -type cathode region 13) of the freewheeling diode is The resistance of the current path in the direction of arrow AR3 passing through the anode (p-type base region 11B) of the free-wheeling diode and the cathode (n ⁺ -type cathode region 13) of the free-wheeling diode is lower (until a relatively high voltage is applied). .

  For this reason, the MOS operation in the IGBT becomes dominant, and it becomes difficult to operate (turn on) the free wheel diode independently during the on operation of the IGBT.

According to the high breakdown voltage semiconductor device in the present embodiment, the p-type base region 11B located closer to the n ⁺ -type cathode region 13 than the second trench region 60 is independent as the anode of the freewheeling diode even when the IGBT is turned on. And function. Therefore, it is possible to operate (turn on) the free wheel diode independently even when the IGBT is on.

[Other Embodiments of Embodiment 6]
With reference to FIG. 20, another embodiment of the sixth embodiment will be described. In the high breakdown voltage semiconductor device of the sixth embodiment, the depth 11AD of the p-type base region 11A including the channel region is set to be shallower than the depth 11BD of the p-type base region 11B not including the channel region. Good.

  According to the high breakdown voltage semiconductor device in the present embodiment, the efficiency of hole injection is higher in the p-type base region 11B not including the channel region than in the p-type base region 11A including the channel region. As a result, the occurrence of the snapback phenomenon can be further suppressed.

[Further Embodiment of Embodiment 6]
With reference to FIG. 21, still another embodiment of the sixth embodiment will be described. In the high breakdown voltage semiconductor device of the sixth embodiment described above, the peak concentration region 11AP of the p-type base region 11A including the channel region is larger than the peak concentration region 11BP of the p-type base region 11B not including the channel region. It is good to be set in a deep position in the thickness direction.

  According to the high breakdown voltage semiconductor device in the present embodiment, the efficiency of hole injection is higher in the p-type base region 11B not including the channel region than in the p-type base region 11A including the channel region. As a result, the occurrence of the snapback phenomenon can be further suppressed.

[Embodiment 7]
A seventh embodiment based on the present invention will be described with reference to FIGS. Also in the high voltage semiconductor device in the present embodiment, the IGBT and the free wheel diode are formed in a single semiconductor substrate, as in the first to sixth embodiments. For convenience of explanation, in FIG. 23, a part of the interlayer insulating film 39 (on the right side in the drawing) is cut away. Referring to FIG. 24, interlayer insulating film 39 extends to the end surface of semiconductor substrate 10 (toward the right side in FIG. 24).

(IGBT)
With reference to FIGS. 22 to 25, the IGBT formed inside the high voltage semiconductor device will be described. Referring to FIG. 24, the IGBT includes an n-type semiconductor substrate 10, a p-type base region (first semiconductor region) 11, a relatively high concentration n ⁺ -type emitter region (second semiconductor region) 12, and A relatively high concentration p ⁺ -type collector region (fourth semiconductor region) 14, an interlayer insulating film 39, and a gate electrode (control electrode) 40 are included. In order to obtain a good ohmic connection between the p-type base region 11 and a first main electrode 41 described later, a p ⁺ -type region may be formed on the surface of the p-type base region 11.

  The p-type base region 11 is selectively formed on the first main surface 1 of the n-type semiconductor substrate 10. A plurality of p-type base regions 11 are arranged in parallel to a first main electrode 41 (see FIG. 22) described later. The p-type base region 11 is surrounded by the semiconductor substrate 10 on the first main surface 1.

The n ⁺ -type emitter region 12 is selectively formed on the surface of the p-type base region 11. The n ⁺ -type emitter region 12 sandwiches the p-type base region 11 with the semiconductor substrate 10. In other words, the n ⁺ -type emitter region 12 is surrounded by the p-type base region 11 on the first main surface 1 of the semiconductor substrate 10.

Unlike the first to sixth embodiments, p ⁺ -type collector region 14 is adjacent to the end surface of semiconductor substrate 10 and is formed from first main surface 1 toward second main surface 2. The p ⁺ -type collector region 14 is formed with a depth that does not penetrate the semiconductor substrate 10 in the thickness direction.

Referring to FIG. 23, both ends of p ⁺ type collector region 14 (in the vertical direction of the drawing in FIG. 23) are sandwiched between semiconductor substrates 10. The p ⁺ type collector regions 14 and the n ⁺ type cathode regions 13 to be described later are arranged alternately along the end surface of the first main surface 1 of the semiconductor substrate 10. At the end face of the semiconductor substrate 10, the semiconductor substrate 10 is sandwiched between the p ⁺ type collector region 14 and the n ⁺ type cathode region 13 (in a direction parallel to the end face of the semiconductor substrate 10). The p ⁺ -type collector region 14 and the n ⁺ -type cathode region 13 are formed over the entire circumference of the semiconductor substrate 10 along the end surface of the first main surface 1 with the semiconductor substrate 10 interposed therebetween.

Referring to FIG. 24, gate electrode 40 faces p-type base region 11 sandwiched between semiconductor substrate 10 and n ⁺ -type emitter region 12 with interlayer insulating film 39 interposed therebetween. A portion of the p-type base region 11 sandwiched between the semiconductor substrate 10 and the n ⁺ -type emitter region 12 and facing the gate electrode 40 via the interlayer insulating film 39 forms a channel region. The gate electrode 40 has a so-called DMOS (Double Diffuse MOS) structure together with the semiconductor substrate 10, the n ⁺ -type emitter region 12 and the p-type base region 11. The gate electrode 40 and the interlayer insulating film 39 in the present embodiment constitute a planar electrode as shown in FIG. 22, but are so-called trench electrodes formed extending inside the semiconductor substrate 10. Also good.

  Referring to FIG. 22, gate electrodes 40 are formed in parallel along first main surface 1 of semiconductor substrate 10, and ends of each gate electrode 40 are electrically connected to each other by gate wiring 40T. Yes. Each gate electrode 40 is connected to a gate pad 40GP by a gate wiring 40T, and each gate electrode 40 constitutes a common potential. One end of the gate wire 40W is connected to the gate pad 40GP, and the other end of the gate wire 40W is connected to the gate pad 40P on the external terminal side.

Referring to FIG. 24, in the IGBT, n-type semiconductor substrate 10 and n ⁺ -type emitter region 12 serve as source / drain regions, and n-channel of p-type base region 11 is controlled by gate electrode 40. That is, the semiconductor substrate 10, the n ⁺ -type emitter region 12, the gate electrode 40, and the p-type base region 11 form a field effect transistor structure.

Further, in the IGBT, a pnp transistor structure including a p-type base region 11, an n-type semiconductor substrate 10, and a p ⁺ -type collector region 14 is formed, and the base current is generated by the above-described field effect transistor. Be controlled. Thereby, the high voltage semiconductor device in the present embodiment can function as an IGBT.

(Reflux diode)
The free-wheeling diode formed inside the high breakdown voltage semiconductor device includes an n ⁺ -type cathode region (third semiconductor region) 13, an n-type semiconductor substrate 10, and a p-type base region 11. The n-type semiconductor substrate 10 and the p-type base region 11 are shared by the IGBT and the freewheeling diode formed inside the high voltage semiconductor device.

The n ⁺ -type cathode region 13 is formed adjacent to the end surface of the semiconductor substrate 10 from the first main surface 1 toward the second main surface 2. The n ⁺ -type cathode region 13 is formed with a depth that does not penetrate the semiconductor substrate 10 in the thickness direction.

Both ends of the n ⁺ -type cathode region 13 (in the vertical direction in FIG. 23) are sandwiched between the semiconductor substrates 10. The n ⁺ -type cathode regions 13 and the p ⁺ -type collector regions 14 are alternately arranged along the end surface of the first main surface 1 of the semiconductor substrate 10 along the entire circumference of the end surface (with the semiconductor substrate 10 interposed therebetween). It is arranged.

The n ⁺ -type cathode region 13 and the n-type semiconductor substrate 10 constitute an n-type region as a diode, and the p-type base region 11 constitutes a p-type region as a diode. A pn junction structure is formed between these n-type and p-type regions. Thereby, the freewheeling diode can function as a diode.

In the high breakdown voltage semiconductor device according to the present embodiment, no electric field relaxation means is formed, and an insulating film is formed between p type base region 11 and n ⁺ type cathode region 13 and p ⁺ type collector region 14. 38 is formed. The insulating film 38 is formed on the first main surface 1 of the semiconductor substrate 10 in order to suppress leakage current and characteristic variation. The insulating film 38 is an oxide film having a low interface order, for example.

(Main electrode)
Referring to FIGS. 22 and 24, first main electrode 41 is formed in parallel along first main surface 1 of semiconductor substrate 10. The first main electrodes 41 are electrically connected to each other. The first main electrode 41 is formed to extend into an opening (contact hole) provided in the interlayer insulating film 39. The first main electrode 41 is formed in contact with both the p-type base region 11 and the n ⁺ -type emitter region 12. The gate electrode 40 and the first main electrode 41 are insulated by an interlayer insulating film 39.

The first main electrode 41 is connected to one end of the emitter wire 41W, and the emitter pad 41P is connected to the other end of the emitter wire 41W. The first main electrode 41 is an electrode that applies a (reference) potential to the p-type base region 11 and the n ⁺ -type emitter region 12 through the emitter pad 41P and the emitter wire 41W.

The collector pad 42 ^</ b ^> T is formed in contact with the p ⁺ type collector region 14 formed on the end surface side of the first main surface 1 of the semiconductor substrate 10. The collector pad 42T and the n ⁺ -type cathode region 13 are electrically connected via a resistor 72 or a diode 73. One end of the connecting means 42W and the collector pad 42T are connected, and the other end of the connecting means 42W and the second main electrode 42P are connected. Thus, the second main electrode 42P can apply a (high) potential to the n ⁺ -type cathode region 13 or the p ⁺ -type collector region 14.

  When the high voltage semiconductor device according to the present embodiment functions as an IGBT, the first main electrode 41 corresponds to an emitter electrode, the second main electrode 42P corresponds to a collector electrode, and the gate electrode 40 corresponds to a gate electrode. To do.

  When the high voltage semiconductor device according to the present embodiment functions as a (reflux) diode, the first main electrode 41 corresponds to an anode electrode, and the second main electrode 42P corresponds to a cathode electrode.

(Action / Effect)
Referring to FIG. 24, in the high breakdown voltage semiconductor device in the present embodiment, both p ⁺ type collector region 14 as the collector of IGBT and n ⁺ type cathode region 13 as the cathode of the freewheeling diode are semiconductors. It is formed on the first main surface 1 side of the substrate 10. That is, the current that flows when the IGBT is turned on and the current that flows when the free wheel diode is turned on flow in parallel.

The second main electrode 42P can apply a (high) potential to the n ⁺ -type cathode region 13 or the p ⁺ -type collector region 14. At this time, the connection means is directly connected to the p ⁺ -type collector region 14 and connected to the n ⁺ -type cathode region 13 via a resistor 72 or a diode 73. Therefore, the resistance between the current that flows when the IGBT is on and the current that flows when the freewheeling diode is on (the point where the current that flows when the IGBT is on and the current that flows when the freewheel diode is on) is high. Therefore, the occurrence of the snapback phenomenon can be suppressed.

[Embodiment 8]
Embodiment 8 based on the present invention will be described with reference to FIGS. Also in the high voltage semiconductor device according to the present embodiment, the IGBT and the free wheel diode are formed in a single semiconductor substrate as in the first to seventh embodiments. For convenience of explanation, in FIG. 27, a part of the interlayer insulating film 39 (on the right side of the drawing) is cut away. Referring to FIG. 28, interlayer insulating film 39 extends to the end surface of semiconductor substrate 10 (toward the right side in FIG. 28).

(IGBT)
With reference to FIGS. 26 to 29, the IGBT formed inside the high voltage semiconductor device will be described. Referring to FIG. 28, the IGBT includes an n-type semiconductor substrate 10, a p-type base region (first semiconductor region) 11, a relatively high concentration n ⁺ -type emitter region (second semiconductor region) 12, and A relatively high concentration p ⁺ -type collector region (fourth semiconductor region) 14, an interlayer insulating film 39, and a gate electrode (control electrode) 40 are included. In order to obtain a good ohmic connection between the p-type base region 11 and a first main electrode 41 described later, a p ⁺ -type region may be formed on the surface of the p-type base region 11.

  The p-type base region 11 is selectively formed on the first main surface 1 of the n-type semiconductor substrate 10. A plurality of p-type base regions 11 are arranged in parallel to a first main electrode 41 (see FIG. 26) described later. The p-type base region 11 is surrounded by the semiconductor substrate 10 on the first main surface 1.

The n ⁺ -type emitter region 12 is selectively formed on the surface of the p-type base region 11. The n ⁺ -type emitter region 12 sandwiches the p-type base region 11 with the semiconductor substrate 10. In other words, the n ⁺ -type emitter region 12 is surrounded by the p-type base region 11 on the first main surface 1 of the semiconductor substrate 10.

  Referring to FIGS. 27 to 29, a trench region 36 is formed on the end surface of the semiconductor substrate 10 over the entire circumference. The trench region 36 is formed so that the side wall portion 36B extending in the direction perpendicular to the end surface of the semiconductor substrate 10 and the back surface portion formed so as to contact the end surface of the semiconductor substrate 10 and connect the end portions of the side wall portions 36B. 36A.

  The side wall portion 36B and the back surface portion 36A of the trench region 36 are each formed in a plate shape, and each includes an insulating film (not shown) and a thin plate-like conductive layer (not shown) included in the insulating film. It is out.

The p ⁺ -type collector region 14 is adjacent to the end surface of the semiconductor substrate 10 with the back surface portion 36 ^</ b ^{> A} of the trench region 36 interposed therebetween. The p ⁺ type collector region 14 is formed from the first main surface 1 toward the second main surface 2. The p ⁺ type collector region 14 is formed with a depth that does not penetrate the semiconductor substrate 10.

Both ends of the p ⁺ -type collector region 14 (in the vertical direction in FIG. 27) are sandwiched between the side wall portions 36B of the trench region 36. The p ⁺ type collector regions 14 and the n ⁺ type cathode regions 13 to be described later are arranged alternately along the end surface of the first main surface 1 of the semiconductor substrate 10. At the end face of the semiconductor substrate 10, the side wall portion 36 ^</ b ^> B of the trench region 36 is sandwiched (in a direction parallel to the end face of the semiconductor substrate 10) by the p ⁺ type collector region 14 and the n ⁺ type cathode region 13. The p ⁺ -type collector region 14 and the n ⁺ -type cathode region 13 extend over the entire circumference of the semiconductor substrate 10 along the end surface of the first main surface 1 of the semiconductor substrate 10 with the side wall portion 36B of the trench region 36 interposed therebetween. Is formed.

Referring to FIG. 28, gate electrode 40 faces p-type base region 11 sandwiched between semiconductor substrate 10 and n ⁺ -type emitter region 12 with interlayer insulating film 39 interposed therebetween. A portion of the p-type base region 11 sandwiched between the semiconductor substrate 10 and the n ⁺ -type emitter region 12 and facing the gate electrode 40 via the interlayer insulating film 39 forms a channel region. The gate electrode 40 has a so-called DMOS (Double Diffuse MOS) structure together with the semiconductor substrate 10, the n ⁺ -type emitter region 12 and the p-type base region 11. The gate electrode 40 and the interlayer insulating film 39 in the present embodiment constitute a planar electrode as shown in FIG. 26, but are so-called trench electrodes formed extending inside the semiconductor substrate 10. Also good.

  Referring to FIG. 26, gate electrodes 40 are formed in parallel along first main surface 1 of semiconductor substrate 10, and the ends of each gate electrode 40 are electrically connected to each other by gate wiring 40T. Yes. Each gate electrode 40 is connected to a gate pad 40GP by a gate wiring 40T, and each gate electrode 40 constitutes a common potential. One end of the gate wire 40W is connected to the gate pad 40GP, and the other end of the gate wire 40W is connected to the gate pad 40P on the external terminal side.

Referring to FIG. 28, in the IGBT, n-type semiconductor substrate 10 and n ⁺ -type emitter region 12 serve as source / drain regions, and n-channel of p-type base region 11 is controlled by gate electrode 40. That is, the semiconductor substrate 10, the n ⁺ -type emitter region 12, the gate electrode 40, and the p-type base region 11 form a field effect transistor structure.

Further, in the IGBT, a pnp transistor structure including a p-type base region 11, an n-type semiconductor substrate 10, and a p ⁺ -type collector region 14 is formed, and the base current is generated by the above-described field effect transistor. Be controlled. Thereby, the high voltage semiconductor device in the present embodiment can function as an IGBT.

(Reflux diode)
The free-wheeling diode formed inside the semiconductor device includes an n ⁺ -type cathode region (third semiconductor region) 13, an n-type semiconductor substrate 10, and a p-type base region 11.

The n ⁺ -type cathode region 13 is adjacent to the end surface of the semiconductor substrate 10 with the back surface portion 36 ^</ b ^{> A} of the trench region 36 interposed therebetween. The n ⁺ -type cathode region 13 is formed from the first main surface 1 toward the second main surface 2. The n ⁺ -type cathode region 13 is formed with a depth that does not penetrate the semiconductor substrate 10 in the thickness direction.

Both ends of the n ⁺ -type cathode region 13 (in the vertical direction in the drawing of FIG. 28) are sandwiched between trench regions 36. The n ⁺ type cathode region 13 and the p ⁺ type collector region 14 extend along the end surface of the first main surface 1 of the semiconductor substrate 10 along the entire circumference of the end surface (with the side wall portion 36B of the trench region 36 sandwiched). They are arranged alternately.

The n ⁺ -type cathode region 13 and the n-type semiconductor substrate 10 constitute an n-type region as a diode, and the p-type base region 11 constitutes a p-type region as a diode. A pn junction structure is formed between these n-type and p-type regions. Thereby, the freewheeling diode can function as a diode.

In the high breakdown voltage semiconductor device in this embodiment, no electric field relaxation means is formed, and an insulating film is provided between the p-type base region 11 and the n ⁺ -type cathode region 13 or the p ⁺ -type collector region 14. 38 is formed. It is formed on the first main surface 1 of the semiconductor substrate 10 in order to suppress leakage current and characteristic fluctuation. The insulating film 38 is an oxide film having a low interface order, for example.

(Main electrode)
Referring to FIGS. 26 and 28, first main electrode 41 is formed in parallel along first main surface 1 of semiconductor substrate 10. The first main electrodes 41 are electrically connected to each other. The first main electrode 41 is formed to extend into an opening (contact hole) provided in the interlayer insulating film 39. The first main electrode 41 is formed in contact with both the p-type base region 11 and the n ⁺ -type emitter region 12. The gate electrode 40 and the first main electrode 41 are insulated by an interlayer insulating film 39.

The first main electrode 41 is connected to one end of the emitter wire 41W, and the emitter pad 41P is connected to the other end of the emitter wire 41W. The first main electrode 41 is an electrode that applies a (reference) potential to the p-type base region 11 and the n ⁺ -type emitter region 12 through the emitter pad 41P and the emitter wire 41W.

Unlike Embodiment 7, collector pad 42T is formed in contact with both n ⁺ -type cathode region 13 and p ⁺ -type collector region 14 formed on the end surface side of first main surface 1 of semiconductor substrate 10. ing. One end of the connecting means 42W and the collector pad 42T are connected, and the other end of the connecting means 42W and the second main electrode 42P are connected. Thus, the second main electrode 42P can apply a (high) potential to the n ⁺ -type cathode region 13 or the p ⁺ -type collector region 14.

  When the high voltage semiconductor device according to the present embodiment functions as an IGBT, the first main electrode 41 corresponds to an emitter electrode, the second main electrode 42P corresponds to a collector electrode, and the gate electrode 40 corresponds to a gate electrode. To do.

  When the high voltage semiconductor device according to the present embodiment functions as a (reflux) diode, the first main electrode 41 corresponds to an anode electrode, and the second main electrode 42P corresponds to a cathode electrode.

(Action / Effect)
Referring to FIG. 28, in the high breakdown voltage semiconductor device according to the present embodiment, both the p ⁺ type collector region 14 as the IGBT collector and the n ⁺ type cathode region 13 as the cathode of the freewheeling diode are semiconductors. It is formed on the first main surface 1 side of the substrate 10. That is, the current that flows when the IGBT is turned on and the current that flows when the free wheel diode is turned on flow in parallel.

A trench region 36 is formed between the n ⁺ type cathode region 13 and the p ⁺ type collector region 14. Therefore, the resistance between the current that flows when the IGBT is on and the current that flows when the freewheeling diode is on (the point where the current that flows when the IGBT is on and the current that flows when the freewheel diode is on) is high. Therefore, the occurrence of the snapback phenomenon can be suppressed.

[Another embodiment of the eighth embodiment]
With reference to FIG. 28, another embodiment of the eighth embodiment will be described. An insulating film 37 (SOI isolation insulating film) is preferably formed on the second main surface 2 side of the n ⁺ -type cathode region 13 and the p ⁺ -type collector region 14 with the semiconductor substrate 10 interposed therebetween. The insulating film 37 is formed so as to protrude further from the side wall portion 36 </ b> B of the trench region 36 to the center side in plan view of the semiconductor substrate 10. Insulating film 37, the side wall portion 36B of n ⁺ -type cathode region trench region 36 are formed at both ends of 13, with 36B, are formed so as to enclose the n ⁺ -type cathode region 13 from the end face side of the semiconductor substrate 10 .

  Since the insulating film 37 is formed, the current flowing during the ON operation of the IGBT and the current flowing during the ON operation of the freewheeling diode (the current flowing during the ON operation of the IGBT and the current flowing during the on operation of the freewheeling diode) Therefore, the occurrence of snapback phenomenon can be further suppressed.

[Still another form of the eighth embodiment]
Still another embodiment of the eighth embodiment will be described with reference to FIGS. 30 and 31. FIG. The high breakdown voltage semiconductor device according to the present embodiment and the high breakdown voltage semiconductor device according to the eighth embodiment include a configuration of the collector pad 42T, a point further including another collector pad 42C, and a resistor 72 or a diode 73. Furthermore, it differs in the point provided, and it is substantially equivalent about another structure. FIG. 30 corresponds to FIG. 27 in the eighth embodiment. FIG. 31 corresponds to FIG. 28 in the eighth embodiment.

In the high breakdown voltage semiconductor device of the eighth embodiment, collector pad 42T is formed in contact with both n ⁺ type cathode region 13 and p ⁺ type collector region 14. On the other hand, referring to FIGS. 30 and 31, collector pad 42 < ^/ b> T in the present embodiment is formed in contact with only n ⁺ -type cathode region 13.

The collector pad 42 </ b> T is formed to extend in a direction perpendicular to the end surface of the semiconductor substrate 10. Inside the interlayer insulating film 39, a resistor 72 or a diode 73 is buried on the end face side of the semiconductor substrate 10 of the collector pad 42T. One end of the collector pad 42T is in contact with the n ⁺ -type cathode region 13, and the other end of the collector pad 42T is in contact with the resistor 72 or the diode 73.

The collector pad 42C is formed on the semiconductor substrate 10 with the insulating film 38 and the interlayer insulating film 39 interposed therebetween. The collector pad 42 ^</ b ^> C extends into an opening (contact hole) formed in the interlayer insulating film 39 and is in contact with the p ⁺ -type collector region 14 through the opening. Referring to FIG. 30, collector pad 42 ^</ b ^> C is formed extending from the portion in contact with p ⁺ -type collector region 14 toward the end surface of semiconductor substrate 10. The ends of the extended portions of the collector pad 42 </ b> C are connected in a direction parallel to the end surface of the semiconductor substrate 10.

  The collector pad 42C and the collector pad 42T are electrically connected by the resistor 72 or the diode 73. One end of the connecting means (corresponding to the connecting means 42W in the seventh embodiment, see FIG. 26) and the collector pad 42T are connected, and the other end of the connecting means and the second main electrode 42P are connected.

Referring to FIG. 31, in the high breakdown voltage semiconductor device according to the present embodiment, as in the eighth embodiment, ap ⁺ type collector region 14 as the collector of the IGBT and an n ⁺ type cathode as the cathode of the freewheeling diode. Both the region 13 and the region 13 are formed on the first main surface 1 side of the semiconductor substrate 10. That is, the current that flows when the IGBT is turned on and the current that flows when the free wheel diode is turned on flow in parallel.

A trench region 36 is formed between the n ⁺ type cathode region 13 and the p ⁺ type collector region 14. Therefore, the resistance between the current that flows when the IGBT is turned on and the current that flows when the free-wheeling diode is turned on is increased, and the occurrence of the snapback phenomenon can be suppressed.

The second main electrode 42P can apply a (high) potential to the n ⁺ -type cathode region 13 or the p ⁺ -type collector region 14. At this time, the connection means is directly connected to the p ⁺ -type collector region 14 and connected to the n ⁺ -type cathode region 13 via a resistor 72 or a diode 73. Therefore, the resistance between the current flowing when the freewheeling diode is turned on (the point where the current flowing when the IGBT is turned on and the current flowing when the freewheeling diode is turned on) is higher (compared to the eighth embodiment). Thus, the occurrence of the snapback phenomenon can be further suppressed.

[Embodiment 9]
A ninth embodiment based on the present invention will be described with reference to FIGS. In the high voltage semiconductor device of the present embodiment, a free wheel diode and two IGBTs (both n-channel type) are formed in a single semiconductor substrate. For convenience of explanation, in FIG. 33, a part of the third main electrode 43T is broken and shown. Referring to FIG. 34, third main electrode 43T extends to the end surface of semiconductor substrate 10 (toward the right side in FIG. 34).

(IGBT)
Referring to FIG. 34, the first IGBT includes an n-type semiconductor substrate 10, a relatively high concentration n ⁺ -type buffer region 10B, a p-type base region (first semiconductor region) 11, and a relatively high level. The p ⁺ type region 11a having a concentration, the n ⁺ type emitter region (second semiconductor region) 12 having a relatively high concentration, the p ⁺ type collector region (fourth semiconductor region) 14 having a relatively high concentration, and the insulating film 31 And a gate electrode (control electrode) 40.

The n-type semiconductor substrate 10, the n ⁺ -type buffer region 10B, the p-type base region 11, the p ⁺ -type region 11a, the n ⁺ -type emitter region 12, the insulating film 31 and the gate electrode 40 are substantially the same as in the second embodiment. Composed.

The p ⁺ type collector region 14 is selectively formed on the second main surface 2 of the semiconductor substrate 10. Specifically, on the second main surface 2 of the semiconductor substrate 10, p ⁺ -type collector regions 14 are formed in parallel (in the vertical direction on the paper of FIG. 32). The p ⁺ -type collector region 14 is formed over the entire surface of the second main surface 2 of the semiconductor substrate 10 at a predetermined interval.

Referring to FIG. 35, n ⁺ type buffer region 10B is formed extending to the second main surface 2 side of semiconductor substrate 10 in the region where p ⁺ type collector region 14 is not formed.

In the first IGBT, as in the second embodiment, the n-type semiconductor substrate 10 and the n ⁺ -type emitter region 12 serve as source / drain regions, and the n-channel of the p-type base region 11 is controlled by the gate electrode 40. The That is, the semiconductor substrate 10, the n ⁺ -type emitter region 12, the gate electrode 40, and the p-type base region 11 form a field effect transistor structure.

Further, in the first IGBT, a pnp transistor structure including a p-type base region 11, an n-type semiconductor substrate 10, an n ⁺ -type buffer region 10B, and a p ⁺ -type collector region 14 is formed. The base current is controlled by the field effect transistor. Thereby, the high voltage semiconductor device in the present embodiment can function as an IGBT.

The second IGBT includes an n-type semiconductor substrate 10, a relatively high concentration n ⁺ -type buffer region 10A, a p-type base region (first semiconductor region) 11, and a relatively high concentration p ⁺ -type region 11a. And an n ⁺ -type emitter region (second semiconductor region) 12, a p ⁺ -type collector region (fifth semiconductor region) 15B, an insulating film 31, and a gate electrode (control electrode) 40.

The n-type semiconductor substrate 10, the p-type base region 11, the p ⁺ -type region 11a, the n ⁺ -type emitter region 12, the insulating film 31 and the gate electrode 40 are common to the first IGBT.

The p ⁺ -type collector region 15 ^</ b ^> B is formed adjacent to the end surface of the semiconductor substrate 10 toward the second main surface 2 from the first main surface 1. The p ⁺ -type collector region 15B is formed with a depth that does not penetrate the semiconductor substrate 10.

Referring to FIG. 36, both ends of p ⁺ type collector region 15B (in the up and down direction in FIG. 36) are sandwiched between n ⁺ type buffer regions 10A. The p ⁺ -type collector regions 15 ^</ b ^> B are arranged alternately along the end surface of the first main surface 1 of the semiconductor substrate 10 together with the n ⁺ -type cathode region 13 described later. On the end face of the semiconductor substrate 10, the n ⁺ -type buffer region 10 A is sandwiched between the p ⁺ -type collector region 15 B and the n ⁺ -type cathode region 13. The p ⁺ type collector region 15 < ^/ b> B and the n ⁺ type cathode region 13 are formed along the entire periphery of the semiconductor substrate 10 along the end surface of the first main surface 1 of the semiconductor substrate 10.

Referring to FIG. 34, in the second IGBT, n-type semiconductor substrate 10 and n ⁺ -type emitter region 12 serve as source / drain regions, and n-channel of p-type base region 11 is controlled by gate electrode 40. . That is, the semiconductor substrate 10, the n ⁺ -type emitter region 12, the gate electrode 40, and the p-type base region 11 form a field effect transistor structure.

Further, in the second IGBT, a pnp transistor structure including a p-type base region 11, an n-type semiconductor substrate 10, an n ⁺ -type buffer region 10A, and a p ⁺ -type collector region 15B is formed. The base current is controlled by the field effect transistor. Thereby, the high voltage semiconductor device in the present embodiment can function as an IGBT.

(Reflux diode)
Referring to FIG. 35, the free-wheeling diode formed inside the semiconductor device includes an n ⁺ -type cathode region (third semiconductor region) 13, an n-type semiconductor substrate 10, and a p-type base region 11. Has been.

The n ⁺ -type cathode region 13 is formed adjacent to the end surface of the semiconductor substrate 10 from the first main surface 1 toward the second main surface 2. The n ⁺ -type cathode region 13 is formed with a depth that does not penetrate the semiconductor substrate 10. The n-type semiconductor substrate 10, the p-type base region 11, and the p ⁺ -type region 11a are shared by the first and second IGBTs and the free-wheeling diode formed inside the semiconductor device.

Referring to FIG. 36, both ends of n ⁺ type cathode region 13 (in the up and down direction in FIG. 36) are sandwiched between n ⁺ type buffer regions 10A. The n ⁺ -type cathode regions 13 and the p ⁺ -type collector regions 15B are alternately arranged along the end surface of the first main surface 1 of the semiconductor substrate 10 along the entire circumference of the end surface (with the semiconductor substrate 10 interposed). ing.

The n ⁺ type cathode region 13, the n ⁺ type buffer region 10A, and the n type semiconductor substrate 10 constitute an n type region as a diode, and the p type base region 11 constitutes a p type region as a diode. is doing. A pn junction structure is formed between these n-type and p-type regions. Thereby, the freewheeling diode can function as a diode.

n ⁺ A ^{n +} -type buffer region 10A between the type cathode region 13 and the ^{p +} -type collector region 15B, ^{n +} -type cathode region 13 and the ^{p +} -type collector region 15B and the resistor 72 or to electrically connect the A diode 73 is embedded. The resistor 72 or the diode 73 may be formed on the first main surface 1 of the semiconductor substrate 10 in order to electrically connect the n ⁺ type cathode region 13 and the p ⁺ type collector region 15B. .

  In the high voltage semiconductor device in the present embodiment, the electric field relaxation means 20 similar to that in the second embodiment is formed.

(Main electrode)
On the first main surface 1 of the semiconductor substrate 10, an interlayer insulating film 31 </ b> A is formed so as to cover the gate electrode 40, as in the second embodiment. A first main electrode 41 is formed on the first main surface 1 of the semiconductor substrate 10 from above the interlayer insulating film 31A. The gate electrode 40 and the first main electrode 41 are insulated by the interlayer insulating film 31A.

The first main electrode 41 is formed in contact with both the p ⁺ type region 11 a and the n ⁺ type emitter region 12. The first main electrode 41 is formed so as to cover a part of the interlayer insulating film 39 constituting the electric field relaxation means 20 (the left end portion of the interlayer insulating film 39 in the drawing).

Referring to FIG. 32, first main electrode 41 is connected to one end of emitter wire 41W, and emitter pad 41P is connected to the other end of emitter wire 41W. Referring to FIG. 34, first main electrode 41 has a (reference) potential with respect to p ⁺ type region 11a, p type base region 11 and n ⁺ type emitter region 12 through emitter pad 41P and emitter wire 41W. It is an electrode to give.

The second main electrode 42P is formed in contact with the p ⁺ type collector region 14 formed on the second main surface 2 of the semiconductor substrate 10. The second main electrode 42P functions as a collector pad. The second main electrode 42P is an electrode that applies a (high) potential to the p ⁺ -type collector region 14.

The third main electrode 43T is formed extending in an opening (contact hole) formed in the interlayer insulating film 39, and is in contact only with the surface side of the p ⁺ -type collector region 15B. The third main electrode 43T is first electrically connected to the p ⁺ type collector region 15B, and is electrically connected to the n ⁺ type cathode region 13 via the resistor 72 or the diode 73.

The third main electrode 43 is an electrode that applies (high) potential to the n ⁺ -type cathode region 13 and the p ⁺ -type collector region 15B. The second main electrode 42P and the third main electrode 43T are electrically connected by connection means 42W such as a conductive wire.

  When the high voltage semiconductor device in the present embodiment functions as an IGBT, the first main electrode 41 corresponds to an emitter electrode, the second main electrode 42P or the third main electrode 43T corresponds to a collector electrode, and the gate electrode 40 corresponds to a gate electrode.

  When the high voltage semiconductor device according to the present embodiment functions as a (reflux) diode, the first main electrode 41 corresponds to an anode electrode, and the third main electrode 43T corresponds to a cathode electrode.

(Action / Effect)
Referring to FIG. 34, when the IGBT is on, current flows in the direction of arrow AR1 or arrow AR2. During the IGBT off operation, no current flows in the arrow AR1 direction and the arrow AR2 direction.

  Referring to FIG. 35, a current flows in the direction of arrow AR3 when the freewheeling diode is on. The current flows in a direction opposite to and parallel to the current flowing in the direction of the arrow AR2 when the second IGBT is turned on.

  Therefore, it is equivalent to a circuit in which an IGBT and a diode are connected in antiparallel between the first main electrode 41 and the second main electrode 42P and between the first main electrode 41 and the third main electrode 43T. Become. That is, the high voltage semiconductor device in this embodiment has a function as a circuit in which an IGBT and a free wheel diode are connected in antiparallel.

The third main electrode 43T can apply a (high) potential to the n ⁺ -type cathode region 13 or the p ⁺ -type collector region 15B. At this time, the connecting means 42W is directly connected to the p ⁺ type collector region 15B, and is connected to the n ⁺ type cathode region 13 via the resistor 72 or the diode 73. Therefore, the resistance between the current that flows when the IGBT is turned on and the current that flows when the free-wheeling diode is turned on is increased, and the occurrence of the snapback phenomenon can be suppressed.

  In the high voltage semiconductor device according to the present embodiment, the first IGBT is formed between the first main surface 1 and the second main surface 2 of the semiconductor substrate 10, and the second IGBT is formed along the first main surface 1. The IGBT is formed. Therefore, it is possible to form a large area on the collector side of the IGBT, and it is possible to improve the performance as a high voltage semiconductor device and reduce the size and weight.

[Embodiment 10]
A tenth embodiment based on the present invention will be described with reference to FIGS. The high breakdown voltage semiconductor device in the present embodiment and the high breakdown voltage semiconductor device in the ninth embodiment are alternately arranged between the p ⁺ type collector region 15B and the n ⁺ type cathode region 13 with the trench region 80 interposed therebetween. The third main electrode 43T is formed in contact with the surfaces of both the p ⁺ -type collector region 15B and the n ⁺ -type cathode region 13, and the resistor 72 and the diode 73 are arranged. It is different in that it is not provided, and the others are substantially the same.

Referring to FIGS. 36 and 39, p ⁺ -type collector region 15B and n ⁺ -type cathode region 13 are adjacent to the end surface of semiconductor substrate 10 in the same manner as in the ninth embodiment. 2 It is formed toward the main surface 2. The p ⁺ type collector region 15 < ^/ b> B and the n ⁺ type cathode region 13 are formed with a depth that does not penetrate the semiconductor substrate 10.

Both ends of the p ⁺ -type collector region 15B and the n ⁺ -type cathode region 13 (in the vertical direction of the drawing in FIG. 36) are sandwiched between trench regions 80. The trench region 80 includes an insulating film 82 and a thin plate-like conductive layer 81 included in the insulating film 82. The p ⁺ type collector regions 15 ^</ b> B and the n ⁺ type cathode regions 13 are arranged alternately along the end surface of the first main surface 1 of the semiconductor substrate 10. The p ⁺ -type collector region 15B and the n ⁺ -type cathode region 13 are formed along the end surface of the first main surface 1 of the semiconductor substrate 10 over the entire circumference of the semiconductor substrate 10 (with the trench region 80 interposed therebetween). .

The third main electrode 43T is formed in contact with both the n ⁺ type cathode region 13 and the p ⁺ type collector region 15B formed on the end surface side of the first main surface 1 of the semiconductor substrate 10. One end of the connection means 42W and the third main electrode 43T are connected, and the other end of the connection means 42W and the second main electrode 42P are connected. Thus, the second main electrode 42P can apply a (high) potential to the n ⁺ -type cathode region 13 or the p ⁺ -type collector region 15B.

(Action / Effect)
Referring to FIGS. 38 and 39, as in the ninth embodiment, current flows in the direction of arrow AR1 or arrow AR2 when the IGBT is turned on. During the IGBT off operation, no current flows in the arrow AR1 direction and the arrow AR2 direction. Referring to FIG. 40, the current flows in the direction of arrow AR3 when the freewheeling diode is on. The current flows in a direction opposite to and parallel to the current flowing in the direction of the arrow AR2 when the second IGBT is turned on.

  Accordingly, as in the ninth embodiment, the IGBT and the diode are antiparallel between the first main electrode 41 and the second main electrode 42P and between the first main electrode 41 and the third main electrode 43T. It is equivalent to the circuit connected to. That is, the high voltage semiconductor device in this embodiment has a function as a circuit in which an IGBT and a free wheel diode are connected in antiparallel.

A trench region 80 is formed between the n ⁺ type cathode region 13 and the p ⁺ type collector region 15B. Therefore, the resistance between the current that flows when the IGBT is turned on and the current that flows when the free-wheeling diode is turned on is increased, and the occurrence of the snapback phenomenon can be suppressed.

  As mentioned above, although the form for implementing invention of this invention was demonstrated, it should be thought that the form disclosed this time is an illustration and restrictive at no points. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

DESCRIPTION OF SYMBOLS 1 1st main surface, 2nd 2nd main surface, 10 Semiconductor substrate, 10A, 10Bn ⁺ type | mold buffer area | region, 11, 11A, 11B p-type base area | region, 11a, 73Dap ⁺ type | mold area | region, 11AP, 11BP peak concentration area | region, 12 n ⁺ type emitter region, 13 n ⁺ type cathode region, 14, 15, 15B p ⁺ type collector region, 11AD, 11BD, 13D, 15D, 40D, 50D, 60D depth, 20 electric field relaxation means, 31, 37, 38, 52, 62, 65, 82 Insulating film, 31A, 39 Interlayer insulating film, 36, 80 Trench region, 36A Side wall, 36B Back surface, 40 Gate electrode, 40P, 40GP Gate pad, 40T Gate wiring, 40W Gate wire , 41 first main electrode, 41P emitter pad, 41W emitter wire, 42P second main electrode, 42C, 42T collection Tap pad, 42W connection means, 43, 43T third main electrode, 48, 49, 72M, 73M conductive film, 50 first trench region, 51, 61, 64, 81 conductive layer, 60 second trench region, 63 third trench Area, 71 Conductive wire, 72 Resistor, 72 Da, 72 Dc, 73 Dcn ⁺ type area, 72 Db, 73 Db n ⁻ type area, 73 Diode, AR1 to AR3 arrows, LT1, LT2 lifetime, R1, R2 resistance.

Claims (4)

A first conductivity type semiconductor substrate having first and second main surfaces;
A first conductive region of a second conductivity type formed on the first main surface of the semiconductor substrate and surrounded by the semiconductor substrate on the first main surface;
A second semiconductor region of a first conductivity type formed on the first main surface and sandwiching the first semiconductor region with the semiconductor substrate;
The semiconductor substrate is alternately arranged adjacent to the end surface of the first main surface, and is formed at a depth that does not penetrate the semiconductor substrate from the first main surface toward the second main surface. A third semiconductor region of the first conductivity type and a fourth semiconductor region of the second conductivity type;
A trench region adjacent to an end surface of the first main surface of the semiconductor substrate, formed from the first main surface toward the second main surface, and separating the third semiconductor region and the fourth semiconductor region; ,
A control electrode formed to face the first semiconductor region sandwiched between the semiconductor substrate and the second semiconductor region with an interlayer insulating film interposed therebetween;
A first main electrode formed in contact with both the first semiconductor region and the second semiconductor region;
A second main electrode formed in electrical connection with the third semiconductor region and the fourth semiconductor region;
A high voltage semiconductor device comprising: A first conductivity type semiconductor substrate having first and second main surfaces;
A first conductive region of a second conductivity type formed on the first main surface of the semiconductor substrate and surrounded by the semiconductor substrate on the first main surface;
A second semiconductor region of a first conductivity type formed on the first main surface and sandwiching the first semiconductor region with the semiconductor substrate;
Adjacent to the end surface of the first main surface of the semiconductor substrate, the semiconductor substrates are alternately arranged while sandwiching the semiconductor substrate, and do not penetrate the semiconductor substrate from the first main surface toward the second main surface. A first conductivity type third semiconductor region and a second conductivity type fourth semiconductor region, each formed at a depth;
A control electrode formed to face the first semiconductor region sandwiched between the semiconductor substrate and the second semiconductor region with an interlayer insulating film interposed therebetween;
A first main electrode formed in contact with both the first semiconductor region and the second semiconductor region;
A resistor or a diode connecting the third semiconductor region and the fourth semiconductor region;
A second main electrode electrically connected to the fourth semiconductor region;
Comprising
High voltage semiconductor device. The resistor or the diode is:
Disposed on the first main surface so as to face the semiconductor substrate sandwiched between the third semiconductor region and the fourth semiconductor region with the interlayer insulating film interposed therebetween, or the third semiconductor region The high breakdown voltage semiconductor device according to claim 2, wherein the high breakdown voltage semiconductor device is disposed inside the semiconductor substrate between the first semiconductor region and the fourth semiconductor region. A fifth semiconductor region of a second conductivity type formed on the second main surface of the semiconductor substrate;
A third main electrode formed in contact with the fifth semiconductor region;
Connecting means for connecting the second main electrode and the third main electrode;
The high breakdown voltage semiconductor device according to claim 1, further comprising:

Images