JP2012186251A - Three-terminal capacitor, and mounting structure of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the following problem: even if a conventional three-terminal capacitor is used as a bypass capacitor by using it in a non-through state, reduction of ESL is not sufficient and further reduction of ELS is required.SOLUTION: In a three-terminal capacitor 21, a through via 26 passing through a dielectric 22 in the thickness direction thereof is provided while making no electrical contact with a ground internal electrode 25 and making electrical contact with a through internal electrode 23. The both upper and lower end faces of the through via 26 are exposed to the surface of the dielectric 22 between input and output terminals 24a, 24b. Therefore, a return path reaching a ground plane layer 33 from a power supply plane layer 32 through capacitance by way of the through via 26 is newly formed between power supply line wiring patterns 31a, 31b and the ground plane layer 33 by using this three-terminal capacitor in the non-through state with the through via 26 connected to the power supply plane layer 32 and with an interval between the input and output terminals 24a, 24b short-circuited by the power supply plane layer 32.

Description

  The present invention relates to a three-terminal capacitor including a through internal electrode and a ground internal electrode, and a mounting structure thereof.

  Conventionally, this type of three-terminal capacitor has, for example, the structure shown in FIG. The three-terminal capacitor 1 generally includes a through internal electrode 3 provided linearly through the dielectric 2 and a substantially cross-shaped ground internal electrode that forms a capacitance between the through internal electrode 3. 4 is provided.

  As a mounting structure of such a three-terminal capacitor 1, there has been conventionally disclosed, for example, in Patent Document 1, and an outline thereof is shown in FIG. 2. In the three-terminal capacitor 1, both ends of the penetration internal electrode 3 are connected to the input / output terminals 5a and 5b, and the ground internal electrode 4 is connected to the ground terminals 5c and 5d. The three-terminal capacitor 1 has a pair of input / output terminals 5a and 5b soldered to the divided power line wiring patterns 6a and 6b, respectively, and a surface between the divided power line wiring patterns 6a and 6b. Has been implemented. The ground terminals 5 c and 5 d are solder-connected to the relay land electrode layer 7 and connected to the ground line ground layer 9 through the via hole 8.

Japanese Patent Laid-Open No. 2001-15585

  As shown in FIG. 3, the conventional three-terminal capacitor 1 is provided with a power plane layer 10 on the inner layer of the circuit board, and the power line wiring patterns 6a and 6b are connected to the power plane layer 10 via via holes 11a and 11b. By connecting, the input / output terminals 5a and 5b are short-circuited by the power supply plane layer 10 and used in a so-called non-penetrating manner. By being used in this way, the three-terminal capacitor 1 functions as a bypass capacitor having a low residual inductance (ESL). In this figure, the same parts as those in FIG.

  However, even if the conventional three-terminal capacitor 1 is used in a non-penetrating manner as described above, in recent high-frequency electronic circuits in which signal transmission is performed at an extremely high frequency, the ESL is not sufficiently reduced, and further low There is a need for ESL.

The present invention has been made to solve such problems,
A penetrating internal electrode provided through the dielectric,
A pair of input / output terminals connected to both ends of the penetrating internal electrode and exposed on the surface of the dielectric,
A ground internal electrode that forms a capacitance with the penetrating internal electrode in the dielectric,
A ground terminal connected to the ground internal electrode and exposed on the surface of the dielectric;
A three-terminal capacitor was configured by including a lead-out conductor provided in the dielectric body and connected to the penetrating internal electrode and exposed on the dielectric surface between the input and output terminals.

  According to this configuration, the penetrating internal electrode provided penetrating the dielectric body is electrically connected to the dielectric surface between the input / output terminals via the lead conductor from the dielectric body. Therefore, the lead conductor exposed on the dielectric surface between the input and output terminals is connected to the power supply layer configured to overlap the layer provided with the power supply line wiring pattern, and each divided power supply line is connected The input / output terminals respectively connected to the wiring patterns are short-circuited by this power supply layer, and a three-terminal capacitor is used in a non-through manner. By using in this way, the return path (return current path) of the through current flowing from the IC passes from the power line pattern on the IC power supply terminal side through the through internal electrode in the three-terminal capacitor and through the capacitor to the ground. The path leading to the layer, and the power supply line wiring pattern on the IC power supply terminal side directly flows to the power supply layer, passes through the through internal electrode in the three-terminal capacitor from the other power supply line wiring pattern, and passes through the capacitor to the ground layer In addition to the path leading to, a path from the power supply layer to the ground layer via the lead conductor through the capacitor is newly formed. As a result, the residual inductance formed between the power line wiring pattern and the ground layer has a configuration in which the residual inductance formed in each of the above paths is connected in parallel. For this reason, the residual inductance formed between the power supply layer and the ground layer is short-circuited between the divided power supply line wiring patterns by the power supply layer, and the conventional three-terminal capacitor is used in a non-through manner. Compared to the case, the residual inductance formed in the new return path is reduced by the amount added in parallel, and the residual inductance can be further reduced.

Further, the present invention is a mounting structure of the above three-terminal capacitor,
A pair of input / output terminals is connected to each divided power line wiring pattern, and a three-terminal capacitor is surface-mounted between the divided power line wiring patterns.
Each divided power line wiring pattern is connected to the power supply layer configured to overlap the layer provided with the power line wiring pattern through the first via hole, respectively.
The lead conductor conducting to the through internal electrode is connected to the power supply layer via the second via hole.

  According to this configuration, in the three-terminal capacitor surface-mounted between the divided power supply line wiring patterns, the lead-out conductor that conducts to the through internal electrode is connected to the power supply layer through the second via hole. Then, each divided power line wiring pattern is connected to the power supply layer through the first via hole, whereby the input / output terminals are short-circuited at the power supply layer, and the three-terminal capacitor is used without passing through. The Therefore, in the mounting structure of this configuration, the residual inductance formed between the power supply layer and the ground layer is a configuration in which the residual inductance formed in each of the return paths is connected in parallel, and a new return path is created. The residual inductance formed is reduced by the amount added in parallel. For this reason, the mounting structure of the 3 terminal capacitor which can further reduce a residual inductance using said 3 terminal capacitor is provided.

  According to the present invention, there is provided a three-terminal capacitor capable of further reducing ESL and a mounting structure thereof by using a three-terminal capacitor in a non-through manner in a high-frequency electronic circuit in which signal transmission is performed at an extremely high frequency. Is done.

It is a perspective view which shows the internal structure of the conventional 3 terminal capacitor. It is a perspective view which shows the mounting structure which wired the conventional 3 terminal capacitor by the penetration specification. It is a perspective view which shows the mounting structure which wired the conventional 3 terminal capacitor by the non-penetration specification. It is a perspective view which shows the 3 terminal capacitor by one embodiment of this invention. It is a perspective view which shows the mounting structure of the 3 terminal capacitor by one Embodiment of this invention which wired the 3 terminal capacitor shown in FIG. 4 by non-penetration specification. It is a graph which shows the simulation result compared with the conventional product in order to confirm the effect of this invention product.

    Next, a three-terminal capacitor and its mounting structure according to an embodiment of the present invention will be described.

  4A and 4B show the multilayer ceramic chip three-terminal capacitor 21 according to the present embodiment. FIG. 4A is an external perspective view thereof, and FIG. 4B is an exploded perspective view showing the internal configuration thereof.

  The three-terminal capacitor 21 includes a penetrating internal electrode 23 that is provided so as to linearly penetrate the rectangular parallelepiped dielectric 22. The penetration internal electrode 23 is connected to a pair of input / output terminals 24 a and 24 b at both ends in the length direction, and the input / output terminals 24 a and 24 b are formed on the surfaces of both end faces facing in the length direction of the dielectric 22. It is exposed and provided. In the dielectric 22, a substantially cross-shaped ground internal electrode 25 that forms a capacitance with the through internal electrode 23 is provided. Both ends in the width direction of the ground internal electrode 25 are connected to a pair of ground terminals 24 c and 24 d, and the ground terminals 24 c and 24 d are provided to be exposed on the surfaces of both sides facing each other in the width direction of the dielectric 22. It has been. In the dielectric 22, a plurality of through internal electrodes and ground internal electrodes (not shown) similar to the through internal electrodes 23 and the ground internal electrodes 25 are alternately stacked to form a plurality of capacitors. These through internal electrodes and ground internal electrodes (not shown) are also connected to the input / output terminals 24a and 24b and the ground terminals 24c and 24d, respectively, similarly to the through internal electrode 23 and the ground internal electrode 25. In the following description, the through internal electrode 23 includes a through internal electrode (not shown), and the ground internal electrode 25 includes a ground internal electrode (not shown).

  The three-terminal capacitor 21 is provided with a through via 26 that penetrates the dielectric 22 in the thickness direction. The through via 26 is provided through a hole formed in the center of the ground internal electrode 25 and not in electrical contact with the ground internal electrode 25 but in electrical contact with the through internal electrode 23. The upper and lower circular end faces of the through via 26 are exposed on the surface of the dielectric 22 between the input / output terminals 24a and 24b. The through via 26 is connected to the through internal electrode 23 in the dielectric 22 and constitutes a lead conductor provided to be exposed on the surface of the dielectric 22 between the input / output terminals 24a and 24b.

  FIG. 5 is a perspective view showing a mounting structure of the three-terminal capacitor 21 on the circuit board.

  The power line wiring patterns 31a and 31b are formed on the surface of a multilayer circuit board on which a high-frequency electronic circuit is formed. The power line wiring patterns 31a and 31b are connected to power terminals such as a driving DC power source (not shown) and a digital IC (highly integrated circuit) (not shown) having an extremely high operating frequency. The three-terminal capacitor 21 is surface-mounted between the divided power line wiring patterns 31a and 31b, and the input / output terminals 24a and 24b are soldered to the divided power line wiring patterns 31a and 31b, respectively.

  The multilayer circuit board is provided with a power plane layer 32 and a ground plane layer 33 so as to overlap with a layer provided with the power line wiring patterns 31a and 31b. The power plane layer 32 and the ground plane layer 33 are formed by forming a copper foil or the like on one side, the power plane layer 32 is connected to the positive side of the driving DC power source, and the ground plane layer 33 is connected to the negative side of the driving DC power source. Has been. The divided power supply line wiring patterns 31a and 31b are connected to the power supply plane layer 32 constituting the power supply layer via the first via holes 34a and 34b, respectively.

  In addition, ground line wiring patterns 35a and 35b connected to a ground terminal such as a digital IC are formed on the surface of the multilayer circuit board. The three-terminal capacitor 21 is surface-mounted on a multilayer circuit board, so that the ground terminals 24c and 24d are solder-connected to the divided ground line wiring patterns 35a and 35b, respectively. Further, the three-terminal capacitor 21 is surface-mounted on the multilayer circuit board, so that the through via 26 is solder-connected to the second via hole 36. The ground line wiring patterns 35a and 35b are connected to the ground plane layer 33 through third via holes 37a and 37b, respectively, and the through via 26 is connected to the power supply plane layer 32 through the second via hole 36. The

  According to the three-terminal capacitor 21 shown in FIG. 4 according to the present embodiment, the through internal electrode 23 provided through the dielectric 22 enters the dielectric 22 via the through via 26. Conduction is conducted to the surface of the dielectric 22 between the output terminals 24a and 24b. Therefore, the through via 26 exposed on the surface of the dielectric 22 between the input / output terminals 24a, 24b is connected to the power plane layer 32, and the input / output terminals 24a, 24b are short-circuited by the power plane layer 32. Thus, the three-terminal capacitor 21 is used without passing through. By using in this way, the return path of the through current flowing from the IC passes from the power supply line wiring pattern 31b on the IC power supply terminal side through the through internal electrode 23 in the three-terminal capacitor 21 and through the capacitance to the ground plane layer. The first internal circuit 23 in the three-terminal capacitor 21 flows directly from the power line wiring pattern 31b on the IC power terminal side to the power plane layer 32 and from the other power line wiring pattern 31a. In addition to the second path from the power plane layer 32 to the ground plane layer 33 through the capacitor, the third path from the power plane layer 32 through the second via hole 36 to the ground plane layer 33 through the through via 26 and the capacitor. A new route is formed.

  As a result, the ESL formed between the power line wiring patterns 31a and 31b and the ground plane layer 33 has a configuration in which the ESL formed in each return path is connected in parallel. For this reason, the ESL formed between the power line wiring patterns 31a and 31b and the ground plane layer 33 has a power plane layer between the divided power line wiring patterns 6a and 6b as shown in FIG. Compared to the conventional case of short-circuiting at 10 and using the three-terminal capacitor 1 non-through, the ESL formed in the new third return path is reduced by the amount added in parallel, and further ESL reduction is achieved. It becomes possible.

  Further, according to the mounting structure of the three-terminal capacitor 21 shown in FIG. 5 according to the present embodiment, the three-terminal capacitor 21 surface-mounted between the divided power line wiring patterns 31 a and 31 b is connected to the through internal electrode 23. The conductive through via 26 is connected to the power plane layer 32 through the second via hole 36. Then, the divided power supply line wiring patterns 31a and 31b are connected to the power supply plane layer 32 through the first via holes 34a and 34b, respectively, so that the input / output terminals 24a and 24b are connected with the power supply plane layer 32. Short-circuited, the three-terminal capacitor 21 is used without passing through. Therefore, the ESL formed between the power supply line wiring patterns 31a and 31b and the ground plane layer 33 in the mounting structure of this embodiment is formed in each of the first, second, and third return paths. ESLs are connected in parallel, and the ESL formed in the new third return path is reduced by the amount added in parallel.

  Specifically, the first return path is a path from the power line pattern 31b on the IC power terminal side to the ground plane layer 33 through the through internal electrode 23 in the three-terminal capacitor 21 and through the capacitor. Yes, the second return path flows directly from the power supply line wiring pattern 31b on the IC power supply terminal side to the power supply plane layer 32, and passes through the internal electrode 23 in the three-terminal capacitor 21 from the other power supply line wiring pattern 31a. This is a path that reaches the ground plane layer 33 through the capacitor. The newly added third return path is a path from the power supply plane layer 32 through the second via hole 36, through the through via 26, and via the capacitance to the ground plane layer 33.

  Therefore, the mounting structure of the three-terminal capacitor 21 as shown in FIG. 5 that can further reduce ESL using the three-terminal capacitor 21 shown in FIG. 4 is provided.

  The applicant conducted a simulation in order to confirm the effects exhibited by the above-described three-terminal capacitor 21 and its mounting structure. In this simulation, the length L, width W, and thickness T of the three-terminal capacitor 21 were set to L = 1.6 mm, W = 0.8 mm, and T = 0.6 mm, respectively. The via diameter of the through via 26 was 0.3 mm, and the capacity of the three-terminal capacitor 21 was 1 [μF].

  The graph shown in FIG. 6 represents the result of calculating the impedance with respect to the ground of the mounting structure of the three-terminal capacitor 21 in this simulation. In the graph, the horizontal axis represents frequency [Hz] and the vertical axis represents impedance [Ω]. A characteristic line 41 indicated by a one-dot chain line is obtained by a simulation in which the conventional three-terminal capacitor 1 shown in FIG. 1 having the same size and the same capacity as the above-described three-terminal capacitor 21 is wired with the penetration specification shown in FIG. Represents impedance characteristics. Further, the characteristic line 42 shown by a dotted line is obtained by a simulation in which the conventional three-terminal capacitor 1 shown in FIG. 1 having the same size and the same capacity as the above-mentioned three-terminal capacitor 21 is wired with the non-penetration specification shown in FIG. Represents impedance characteristics. A characteristic line 43 shown by a solid line represents an impedance characteristic obtained by a simulation in which the three-terminal capacitor 21 of the present invention shown in FIG.

  As shown in the graph, it is confirmed that the impedance of the non-penetrating specification is lower in the penetrating specification represented by the characteristic line 41 and the non-penetrating specification represented by the characteristic lines 42 and 43. It was. In addition, even in the non-penetrating specification, the conventional product represented by the characteristic line 42 and the product of the present invention represented by the characteristic line 43 have a lower inductance and a lower impedance in the product of the present invention, which further reduces ESL. It was confirmed that it was planned.

  In the above-described three-terminal capacitor 21 according to the present embodiment, the case where one through via 26 is in electrical contact with the through internal electrode 23 and penetrates the thickness direction of the dielectric 22 has been described. The via 26 may be configured to be in electrical contact with the penetrating internal electrode 23 and penetrate the dielectric 22 in the thickness direction. With this configuration, the inductance is further reduced, the impedance is further reduced, and the ESL can be further reduced. Further, even with one through via 26, it is possible to further reduce the ESL by increasing the diameter of the through via 26.

  The three-terminal capacitor 21 and its mounting structure according to the present embodiment are used in a high-frequency electronic circuit in which signal transmission is performed at an extremely high frequency. By being used in such a high-frequency electronic circuit, the ESL can be further reduced, and high-frequency noise generated in the power supply line and the like can be more effectively reduced.

DESCRIPTION OF SYMBOLS 21 ... Three-terminal capacitor 22 ... Dielectric 23 ... Through-hole internal electrode 24a, 24b ... Input / output terminal 24c, 24d ... Ground terminal 25 ... Ground internal electrode 26 ... Through-via 31a, 31b ... Wiring pattern for power supply lines 32 ... Power supply plane layer (Power layer)
33 ... Ground plane layer (ground layer)
34a, 34b ... first via hole 35a, 35b ... ground line wiring pattern 36 ... second via hole 37a, 37b ... third via hole

Claims (2)

A penetrating internal electrode provided through the dielectric,
A pair of input / output terminals connected to both ends of the through-hole internal electrode and exposed on the surface of the dielectric;
A ground internal electrode that forms a capacitance with the through internal electrode in the dielectric;
A ground terminal connected to the ground internal electrode and exposed on the surface of the dielectric;
A three-terminal capacitor comprising: a lead-out conductor provided in the dielectric body and connected to the penetrating internal electrode and exposed on the dielectric surface between the input / output terminals. The mounting structure for a three-terminal capacitor according to claim 1,
A pair of the input / output terminals is connected to each divided power line wiring pattern, and the three-terminal capacitor is surface-mounted between the divided power line wiring patterns,
Each of the divided power supply line wiring patterns is connected to a power supply layer configured to overlap a layer provided with the power supply line wiring pattern through a first via hole, respectively.
The three-terminal capacitor mounting structure, wherein the lead-out conductor is connected to the power supply layer through a second via hole.

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