JP6610072B2 - Multilayer capacitor and wiring board - Google Patents

Description

  The present invention relates to a multilayer capacitor and a wiring board on which the multilayer capacitor is mounted.

  In a digital circuit, a decoupling capacitor is inserted between a power supply and a ground in order to absorb load fluctuation during operation of the IC or LSI and to remove noise. At that time, from the viewpoint of suppressing voltage fluctuations, it is preferable that the power source impedance is low. Therefore, it is desirable that the impedance of the decoupling capacitor is also low, so that the IC has sufficient capacitance according to the power source impedance required by the IC. Capacitors are used.

  However, in a high frequency region of several MHz or more, the impedance cannot be lowered only by the capacitance due to the influence of the inductance of the wiring connecting the power supply terminal such as an IC and the capacitor. Therefore, an attempt has been made to reduce inductance by disposing a capacitor in the vicinity of a semiconductor integrated circuit element such as an IC or LSI and minimizing the wiring from the power supply and ground line to the capacitor of the semiconductor integrated circuit element. (For example, refer to Patent Document 1).

  Here, Patent Document 1 discloses a semiconductor element storage package having a plurality of via-hole conductors that penetrates an insulating substrate and serves as an electric circuit and a ground circuit, and a semiconductor element mounted on the semiconductor element storage package. Are connected by a plurality of solder balls respectively formed on a plurality of via hole conductors, and further, an electronic component mounting board provided with a multilayer ceramic capacitor so as to bridge between the plurality of solder balls is disclosed. .

  According to this electronic component mounting board, the wiring from the semiconductor element storage package to the multilayer ceramic capacitor, and the wiring from the multilayer ceramic capacitor to the semiconductor element are only the length of the solder ball, and thus generated on the board. Inductance can be reduced.

JP 2005-340535 A

  However, in the electronic component mounting board (wiring board) described in Patent Document 1 described above, a predetermined interval corresponding to the size of the multilayer ceramic capacitor is required when the multilayer ceramic capacitor is mounted. Therefore, for example, when the multilayer ceramic capacitor does not fit between the solder balls, it is necessary to change the arrangement and the number of the solder balls in order to ensure the interval.

  The present invention has been made to solve the above problems, and is directly mounted on a wiring board on which a plurality of solder balls are arranged without changing the arrangement of the solder balls or removing the solder balls. An object of the present invention is to provide a multilayer capacitor that can be used, and a wiring board on which the multilayer capacitor is mounted.

  A multilayer capacitor according to the present invention is a multilayer capacitor mounted on a wiring board on which a semiconductor integrated circuit is mounted and a plurality of solder balls are disposed on one surface, and corresponds to the arrangement of the solder balls, A multilayer body in which a plurality of through holes are formed in the stacking direction, and the thickness of the stack body in the stacking direction is thinner than the maximum length in the direction perpendicular to the one surface of the solder ball, and is formed in the stack The diameter of the through hole is larger than the maximum length in the direction parallel to the one surface of the solder ball.

  According to the multilayer capacitor of the present invention, a plurality of through holes are formed in the stacking direction corresponding to the arrangement of the solder balls, and the diameter of the through holes is parallel to the one surface. Since it is larger than the maximum length, when the multilayer capacitor is mounted on the wiring board, the solder ball fits in the through hole. Further, since the thickness in the stacking direction of the stacked body is thinner than the maximum length of the solder balls in the direction perpendicular to the one surface, the wiring board can be mounted on, for example, the main board using the solder balls. As a result, it is possible to directly mount the wiring board on which the plurality of solder balls are arranged without changing the arrangement of the solder balls or removing the solder balls.

  In the multilayer capacitor according to the present invention, the multilayer body is configured by alternately laminating a plurality of internal electrodes formed with a plurality of through holes and a plurality of dielectric layers formed with a plurality of through holes. The diameter of the through hole formed in the electrode is preferably larger than the diameter of the through hole formed in the dielectric layer.

  In this case, since the diameter of the through hole formed in the internal electrode is larger than the diameter of the through hole formed in the dielectric layer, the internal electrode is prevented from being exposed to the inner peripheral surface of the through hole. Therefore, it is possible to prevent a short circuit between the internal electrode of the multilayer capacitor and the solder ball.

  In the multilayer capacitor according to the present invention, it is preferable that each of the plurality of internal electrodes is divided into a plurality of parts.

  In this case, since each of the plurality of internal electrodes is divided into a plurality of parts, a plurality of capacitors can be formed in one laminated body. Therefore, it is possible to deal with a plurality of different voltage systems with one component.

  The multilayer capacitor according to the present invention preferably includes a pair of external electrodes formed on the side surface of the multilayer body.

  In this case, since the pair of external electrodes are formed on the side surface of the laminate, it can be manufactured relatively easily.

  The multilayer capacitor according to the present invention preferably includes two or more pairs of external electrodes formed on the side surface of the multilayer body.

  In this case, since two or more pairs of external electrodes are formed on the side surface of the laminate, for example, the direction of current flow is reversed between one pair of external electrodes and the other pair of external electrodes. By arranging in such a manner, the magnetic fields (magnetic fluxes) generated by the currents can be canceled with each other, and the inductance can be further reduced.

  In the multilayer capacitor according to the present invention, it is preferable that the external electrodes are arranged side by side on one side surface of the multilayer body.

  In this case, since the external electrodes are arranged side by side on the side surface on one side of the laminate, it is possible to increase the degree of freedom of arrangement.

  In the multilayer capacitor according to the present invention, it is preferable that the external electrode is disposed to face each of the opposing side surfaces of the multilayer body.

  In this case, since the external electrode is disposed to face each of the opposing side surfaces of the stacked body, for example, the direction in which current flows between the external electrode in one pair and the external electrode in the other pair It becomes easy to arrange so that becomes reverse.

  In the multilayer capacitor according to the present invention, the external electrode includes a ground external electrode connected to the ground terminal of the semiconductor integrated circuit and a power external electrode connected to the power supply terminal of the semiconductor integrated circuit. It is preferable that the external electrodes and the power supply external electrodes are alternately arranged.

  In this case, the external electrode includes a ground external electrode connected to the ground terminal of the semiconductor integrated circuit and a power external electrode connected to the power supply terminal of the semiconductor integrated circuit, and the ground external electrode and the power external electrode Are arranged alternately. Therefore, the magnetic field (magnetic flux) generated by the parasitic inductance cancels each other, and the inductance can be reduced. Therefore, the power source impedance in the high frequency region can be further reduced.

  A wiring board according to the present invention is a wiring board on which a semiconductor integrated circuit is mounted and a plurality of solder balls are disposed on one surface, and any one of the multilayer capacitors is mounted on the one surface. It is characterized by being.

  According to the wiring board of the present invention, since any one of the above multilayer capacitors is mounted on one surface, the arrangement and number of solder balls are not changed (that is, the arrangement of the solder balls is changed or the solder balls are changed) Without removing the ball), the multilayer capacitor can be directly mounted, and the power source impedance can be further reduced.

  According to the present invention, it is possible to directly mount a multilayer capacitor on a wiring board on which a plurality of solder balls are arranged without changing the arrangement of the solder balls or removing the solder balls.

It is a bottom view which shows the structure of the multilayer capacitor which concerns on embodiment, and the interposer by which this multilayer capacitor was mounted. It is a side view which shows the structure of the multilayer capacitor which concerns on embodiment, and the interposer by which this multilayer capacitor was mounted. It is a figure which shows the structure of the internal electrode and external electrode of the multilayer capacitor which concerns on embodiment. It is a figure which shows the structure of the internal electrode and external electrode of the multilayer capacitor which concerns on a modification.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals are used for the same or corresponding parts. Moreover, in each figure, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  First, the configuration of the multilayer capacitor 1 according to the embodiment and the interposer (corresponding to the wiring board described in the claims) 10 on which the multilayer capacitor 1 is mounted will be described with reference to FIGS. FIG. 1 is a bottom view showing the configuration of the multilayer capacitor 1 and the interposer 10 on which the multilayer capacitor 1 is mounted. FIG. 2 is a side view showing the configuration of the multilayer capacitor 1 and the interposer 10 on which the multilayer capacitor 1 is mounted. FIG. 3 is a diagram illustrating the configuration of the internal electrodes 4 and 5 and the external electrodes 6 and 7 of the multilayer capacitor 1.

  The interposer 10 is a printed board (wiring board) that relays between the LSI chip 12 and the main board 20 having different terminal pitches. The interposer 10 has an LSI chip (corresponding to the semiconductor integrated circuit described in claims) 12 mounted on the upper surface and a plurality of hemispherical solder balls on the lower surface (corresponding to one surface described in the claims). 11 are arranged in a grid pattern. That is, the interposer 10 is a BGA (Ball Grid Array) type printed circuit board. In FIGS. 1 and 2, the scale ratios of the multilayer capacitor 1 and the solder balls 11 with respect to the interposer 10 are changed as appropriate for easy understanding of the drawings.

  On the lower surface (bottom surface) of the interposer 10, a multilayer capacitor 1 that functions as a decoupling capacitor is mounted between the power source and the ground in order to absorb load fluctuation during operation of the LSI chip 12 and to remove noise. . That is, the multilayer capacitor 1 is mounted so as to be inserted between the interposer 10 and the main board 20.

  The multilayer capacitor 1 includes a multilayer body 2 formed in a rectangular parallelepiped shape, and four pairs of external electrodes 6 and 7 formed on both side surfaces of the multilayer body 2.

The multilayer body 2 is configured by alternately laminating a plurality of dielectric layers 3 formed in a rectangular shape and a plurality of internal electrodes 4 and 5. The dielectric layer 3 is made of, for example, a dielectric ceramic mainly composed of BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ or the like. Note that subcomponents such as a Mn compound, Fe compound, Cr compound, Co compound, and Ni compound may be added to these main components.

  In particular, in the laminate 2, a plurality of (eight in the example of FIG. 1) through-holes 8 are formed in the lamination direction corresponding to the arrangement and pitch of the solder balls 11. Here, the diameter of each through-hole 8 formed in the multilayer body 2 (multilayer capacitor 1) is formed larger than the maximum length φ2 of the solder ball 11 in a direction parallel to the lower surface of the interposer 10. Therefore, when the multilayer capacitor 1 is mounted on the interposer 10, the solder balls 11 are accommodated inside the through holes 8.

  More specifically, the laminate 2 includes a plurality of internal electrodes 4 and 5 in which a plurality (eight) through-holes 8B are formed, and a plurality of dielectric layers in which a plurality (eight) through-holes 8 are formed. 3 are alternately stacked. Here, the diameter of the through hole 8B formed in the internal electrodes 4 and 5 is the same as that of the through hole 8 formed in the dielectric layer 3 (the diameter of the through hole of the dielectric layer 3 is the same as the diameter of the through hole of the laminate 2). Therefore, the same reference numerals are used for convenience).

  In addition, the thickness of the multilayer body 2 (multilayer capacitor 1) in the stacking direction is smaller than the maximum length φ1 of the solder ball 11 in the direction perpendicular to the lower surface of the interposer 10. Therefore, the interposer 10 can be mounted on the main board 20 with the multilayer capacitor 1 mounted.

  The internal electrodes 4 and 5 are formed in a rectangular thin film shape. The internal electrodes 4 and the internal electrodes 5 are alternately stacked so as to face each other with the dielectric layer 3 interposed therebetween. Each of the internal electrodes 4 and 5 is made of, for example, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like. The internal electrodes 4 and 5 are drawn out on both side surfaces of the multilayer body 2.

  Four pairs of external electrodes 6 and 7 are formed on both side surfaces of the laminate 2. That is, the external electrode 6 and the external electrode 7 are formed side by side on the side surface of the multilayer body 2 so as to face each other with the multilayer body 2 interposed therebetween. The external electrodes 6 and 7 are made of, for example, a conductive material containing silver as a main component. The external electrode 6 is connected to the lead portion of the internal electrode 4 described above. On the other hand, the external electrode 7 is connected to a lead portion of the internal electrode 5.

  More specifically, the external electrodes 6 and 7 are the ground external electrodes 6 connected to the ground terminals of the LSI chip 12 (more specifically, the solder balls 11 connected to the terminals via vias), A power supply (or signal) terminal of the LSI chip 12 (more specifically, a solder ball 11 connected to the terminal through a via) and a power supply (or signal) external electrode 7 connected to the ground external The electrodes 6 and the power supply external electrodes 7 are alternately arranged. Note that the terminals (the solder balls 11) of the LSI chip 12 and the external electrodes 6 and 7 may be connected via, for example, a printed wiring, or configured to be in direct contact (connection). Also good.

  Here, the number of pairs of the external electrodes 6 and 7 is not limited to four pairs, and may be one pair, for example. Alternatively, the external electrodes 6 and 7 may be arranged only on one side surface of the laminate 2.

  Next, a method for manufacturing the multilayer capacitor 1 will be described. First, a dielectric paste mainly composed of a barium titanate-based dielectric material or the like is applied by screen printing to form the dielectric layer 3.

  Subsequently, for example, a conductive paste containing silver as a main component is applied by screen printing to form a conductive paste layer having a hole, that is, an internal electrode 4 (5) having a through hole 8B. Thereafter, in the same manner, the respective layers are sequentially laminated, that is, the dielectric layers 3 and the internal electrodes 4 and 5 are alternately laminated.

  Then, after all the layers are formed, the through holes 8 are formed in the stacking direction of the stacked body 2. Thereafter, each multilayer capacitor is cut by dicing or the like. Then, after firing under predetermined conditions, for example, Sn plating or Ni plating is applied to the external electrodes 6 and 7. The multilayer capacitor 1 is manufactured as described above.

  According to the present embodiment, a plurality (eight) of through holes 8 are formed in the stacking direction corresponding to the arrangement and pitch of the solder balls 11, and the diameter of the through holes 8 is parallel to the lower surface of the interposer 10. Therefore, when the multilayer capacitor 1 is mounted on the interposer 10, the solder ball 11 fits inside the through-hole 8. As a result, the multilayer capacitor 1 can be directly mounted on the interposer 10 provided with the plurality of solder balls 11 without changing the arrangement of the solder balls 11 or removing the solder balls 11. In addition, since the thickness in the stacking direction of the multilayer body 2 is thinner than the maximum length φ1 of the solder ball 11 in the direction perpendicular to the lower surface of the interposer 10, the interposer 10 on which the multilayer capacitor 1 is mounted using the solder ball 11 is mainly It can be mounted on the substrate 20.

  According to this embodiment, since the diameter of the through hole 8B formed in the internal electrodes 4 and 5 is larger than the diameter of the through hole 8 formed in the dielectric layer 3, the internal electrodes 4 and 5 are formed in the through hole 8. It is prevented from being exposed to the inner peripheral surface of the. Therefore, it is possible to prevent the internal electrodes 4 and 5 of the multilayer capacitor 1 and the solder ball 11 from being short-circuited.

  According to this embodiment, four pairs of external electrodes 6 and 7 are arranged side by side on the opposite side surfaces of the multilayer body 2, and the ground external electrodes 6 and the power supply external electrodes 7 are alternately arranged. Yes. Therefore, the magnetic field (magnetic flux) generated by the parasitic inductance cancels each other, and the inductance can be reduced. Therefore, the power source impedance in the high frequency region can be further reduced.

(Modification)
In the above embodiment, each of the internal electrodes 4 and 5 is composed of one (that is, not divided) electrode. However, as shown in FIG. 4, there are a plurality of internal electrodes 4B and 5B (4 in this embodiment). The internal electrodes 4a, 4b, 4c, 4d and the internal electrodes 5a, 5b, 5c, 5d may be configured. Here, FIG. 4 is a diagram showing the configuration of the internal electrodes 4B and 5B and the external electrodes 6 and 7 of the multilayer capacitor 1B according to the modification. In this case, the power supply external terminals 7 and the ground external terminals 6 are preferably arranged alternately on both side surfaces of the multilayer body 2B. Since other configurations are the same as or similar to those of the multilayer capacitor 1 described above, detailed description thereof is omitted here.

  According to this modification, each of the plurality of internal electrodes 4B and 5B is divided into a plurality of pieces, and thus a plurality of capacitors can be formed in one stacked body 2B. Therefore, it is possible to deal with a plurality of different voltage systems with one component.

  Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above-described embodiment, the multilayer capacitor 1 is mounted (applied) on the interposer 10, but can be applied to a printed board (wiring board) other than the interposer.

  Further, the arrangement and number of the through holes 8 of the multilayer capacitor 1 and the arrangement and number of the solder balls 11 of the interposer 10 shown in the drawings are examples, and can be arbitrarily set. Further, the number of external electrodes 6 and 7 of the multilayer capacitor 1 is not limited to the above embodiment.

  In the above embodiment, the external electrode 6 is connected to the ground terminal of the LSI chip 12 (more specifically, the solder ball 11 connected to the terminal via the via), and the external electrode 7 is connected to the power supply of the LSI chip 12. (Or signal) terminals (more specifically, the solder balls 11 connected to the terminals via vias) are connected to each other, but the reverse, that is, the external electrode 6 is connected to the power (or signal) terminal. The external electrode 7 may be connected to the ground terminal.

  Furthermore, in the above embodiment, the case where one multilayer capacitor 1 is mounted on the interposer 10 has been described as an example. However, the number of multilayer capacitors 1 mounted on the interposer 10 may be two or more. It can be arbitrarily set according to the requirements.

DESCRIPTION OF SYMBOLS 1,1B multilayer capacitor 2, 2B multilayer body 3 Dielectric layer 4, 5, 4B, 5B Internal electrode 6, 7 External electrode 8 Through hole 8B Through hole 10 Interposer 11 Solder ball 12 LSI chip 20 Main board

Claims (9)

A multilayer capacitor mounted on a wiring board on which a semiconductor integrated circuit is mounted and a plurality of solder balls are disposed on one surface,
Corresponding to the arrangement of the solder balls, comprising a laminate in which a plurality of through holes are formed in the lamination direction,
The thickness of the stacked body in the stacking direction is thinner than the maximum length in the direction perpendicular to the one surface of the solder ball, and the diameter of the through hole formed in the stacked body is the thickness of the solder ball. much larger than the maximum length of one side parallel to the direction,
The laminated body is configured by alternately laminating a plurality of internal electrodes formed with a plurality of through holes and a plurality of dielectric layers formed with a plurality of through holes,
The diameters of all the through holes formed in the internal electrode are larger than the diameters of all the through holes formed in the dielectric layer. A multilayer capacitor characterized in that it is not exposed on the peripheral surface . A gap is provided between the inner peripheral surface of the through hole and the solder ball so that the inner peripheral surface of all the through holes formed in the laminate does not contact the solder ball. The multilayer capacitor according to claim 1. Wherein the plurality of each internal electrode, the multilayer capacitor according to claim 1 or 2, characterized in that it is divided into a plurality.   The multilayer capacitor according to claim 1, further comprising a pair of external electrodes formed on a side surface of the multilayer body.   The multilayer capacitor according to claim 1, further comprising two or more pairs of external electrodes formed on a side surface of the multilayer body.   The multilayer capacitor according to claim 4, wherein the external electrodes are arranged side by side on one side surface of the multilayer body.   The multilayer capacitor according to claim 4, wherein the external electrode is disposed to face each of the opposing side surfaces of the multilayer body. The external electrode includes a ground external electrode connected to a ground terminal of the semiconductor integrated circuit, and a power external electrode connected to a power supply terminal of the semiconductor integrated circuit,
The multilayer capacitor according to claim 7, wherein the ground external electrode and the power external electrode are alternately arranged. In a wiring board on which a semiconductor integrated circuit is mounted and a plurality of solder balls are arranged on one side,
A multilayer substrate according to claim 1, wherein the multilayer capacitor is mounted on the one surface.

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