KR101912279B1 - Multi-layered ceramic capacitor part and board for mounting the same - Google Patents

Multi-layered ceramic capacitor part and board for mounting the same Download PDF

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Publication number
KR101912279B1
KR101912279B1 KR1020160109349A KR20160109349A KR101912279B1 KR 101912279 B1 KR101912279 B1 KR 101912279B1 KR 1020160109349 A KR1020160109349 A KR 1020160109349A KR 20160109349 A KR20160109349 A KR 20160109349A KR 101912279 B1 KR101912279 B1 KR 101912279B1
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South Korea
Prior art keywords
surface
ceramic body
insulating layer
lead portion
formed
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KR1020160109349A
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Korean (ko)
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KR20160106026A (en
Inventor
박민철
김현태
안영규
이교광
박상수
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삼성전기 주식회사
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Priority to KR1020130084041A priority patent/KR20140038872A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • H01G4/1209Ceramic dielectrics characterised by the ceramic dielectric material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02Mountings
    • H01G2/06Mountings specially adapted for mounting on a printed-circuit support
    • H01G2/065Mountings specially adapted for mounting on a printed-circuit support for surface mounting, e.g. chip capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/005Electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10015Non-printed capacitor

Abstract

According to an embodiment of the present invention, there is provided a ceramic body including a ceramic body including a plurality of dielectric layers, first and second draw-outs disposed inside the ceramic body and exposed at a first surface in a width direction of the ceramic body, A first internal electrode exposed in third and fourth surfaces in the longitudinal direction and a third internal electrode exposed in a first width direction of the ceramic body and spaced apart from the first and second lead portions by a predetermined distance, A second internal electrode exposed on the third and fourth surfaces in the lengthwise direction, and a second internal electrode disposed on the first surface in the width direction of the ceramic body, the first to third lead portions being connected to the first to third lead portions, An outer electrode, and an insulating layer disposed on a first surface in the width direction or a third surface and a fourth surface in the longitudinal direction of the ceramic body, wherein the insulating layer is formed of a ceramic slurry.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a multilayer ceramic capacitor,

The present invention relates to a multilayer ceramic capacitor and a circuit board mounting structure of a multilayer ceramic capacitor.

In general, an electronic component using a ceramic material such as a capacitor, an inductor, a piezoelectric element, a varistor or a thermistor includes a ceramic body made of a ceramic material, internal electrodes formed inside the body, and external electrodes provided on the surface of the ceramic body to be connected to the internal electrodes Respectively.

A multilayer ceramic capacitor in a ceramic electronic device includes a plurality of laminated dielectric layers, an inner electrode disposed opposite to the dielectric layer with one dielectric layer interposed therebetween, and an outer electrode electrically connected to the inner electrode.

The multilayer ceramic capacitor is widely used as a component of a mobile communication device such as a computer, a PDA, and a mobile phone due to its small size, high capacity, and ease of mounting.

In recent years, miniaturization and multifunctionalization of electronic products have led to the tendency of miniaturization and high functioning of chip components. Therefore, a multilayer ceramic capacitor is required to have a small-sized and high capacity high-capacity product.

In addition, the multilayer ceramic capacitor is usefully used as a bypass capacitor disposed in the power circuit of the LSI. In order to function as a bypass capacitor, the multilayer ceramic capacitor must be capable of effectively removing high frequency noise. Such a demand is further increased in accordance with a tendency toward high frequency of electronic devices. A multilayer ceramic capacitor used as a bypass capacitor is electrically connected to a mounting pad on a circuit board through soldering, and the mounting pad can be connected to another external circuit through a wiring pattern or a conductive via on the substrate.

Multilayer ceramic capacitors have both an equivalent series resistance (ESR) and an equivalent series inductance (ESL) component in addition to a capacitance component, and these equivalent series resistance (ESR) and equivalent series inductance (ESL) components impair the function of the bypass capacitor . In particular, the equivalent series inductance (ESL) increases the inductance of a capacitor at a high frequency, thereby deteriorating the high frequency noise removing characteristic.

Meanwhile, a low equivalent series inductance (ESL) is required in the case of a vertical stacked capacitor. To realize this, a method of forming a margin region in which the internal electrode is not formed is formed in the manufactured ceramic stacked body, In this case, short-circuit problems may occur.

Korean Published Patent 2010-0068056

The present invention relates to a multilayer ceramic capacitor and a circuit board mounting structure of a multilayer ceramic capacitor.

According to an embodiment of the present invention, there is provided a ceramic body including a ceramic body including a plurality of dielectric layers, first and second lead portions disposed inside the ceramic body and exposed to a first widthwise surface of the ceramic body at predetermined intervals, And a third internal electrode exposed through the third and fourth surfaces in the lengthwise direction and a third lead portion exposed by the first widthwise surface of the ceramic body and spaced apart from the first and second lead portions by a predetermined distance, A second internal electrode exposed in a third surface and a fourth surface in the longitudinal direction, first to third external electrodes disposed on a first surface in the width direction of the ceramic body and connected to the first to third lead portions, respectively, An electrode, and an insulating layer disposed on a first surface or a third surface and a fourth surface in the longitudinal direction of the ceramic body, wherein the insulating layer is formed of a ceramic slurry.

According to another aspect of the present invention, there is provided a ceramic body including a ceramic body including a plurality of dielectric layers, a ceramic body disposed inside the ceramic body and having a first surface and a second surface exposed to a first surface and a second surface, A first internal electrode exposed at a third surface and a fourth surface in a longitudinal direction and a first internal electrode exposed at a first surface and a second surface in the width direction of the ceramic body, A second internal electrode exposed at the third surface and the fourth surface in the longitudinal direction, and a second internal electrode disposed at the first surface and the second surface in the width direction of the ceramic body, First to sixth external electrodes respectively connected to the first to sixth lead portions, and an insulating layer disposed on the first and second surfaces in the width direction or the third and fourth longitudinal surfaces of the ceramic body, , The insulating layer is a ceramic slurry And it provides a monolithic ceramic capacitor.

Another embodiment of the present invention is a printed circuit board comprising: a printed circuit board having first to third electrode pads on the top; And a multilayer ceramic capacitor provided on the printed circuit board.

According to one embodiment of the present invention, the internal electrode can be formed as wide as possible, leaving a minimum margin or gap in the dielectric layer of the ceramic body. As a result, the overlap region of the first and second internal electrodes is widened, and a high-capacity multilayer ceramic capacitor can be formed.

In addition, the distance between the first and second internal electrodes to which the external polarity is applied is shortened, so that the current loop can be shortened, and the equivalent series inductance (ESL) can be lowered.

According to an embodiment of the present invention, the insulating layer formed on the ceramic body includes an end portion of the first and second internal electrodes exposed on one surface of the ceramic body, a portion between the end portions of the first and second internal electrodes, It is possible to prevent internal defects such as deterioration of moisture resistance and the like.

According to one embodiment of the present invention, when the height of the insulating layer can be adjusted and the height of the insulating layer is formed lower than the height of the first and second external electrodes, the multilayer ceramic capacitor is more reliably mounted on the circuit board .

According to an embodiment of the present invention, the current flow of the multilayer ceramic capacitor can be transmitted to the internal electrode through the plurality of external electrodes, and thus the magnitude of the component of the inductance connected in series to the capacitance component of the multilayer ceramic capacitor Can be made very small.

Further, since the lead portions of the first and second internal electrodes are formed so as not to overlap with each other, the short defects are reduced and the reliability is excellent.

1 is a schematic perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention.
2 is a cross-sectional view showing an internal electrode structure of the multilayer ceramic capacitor shown in FIG.
3 is a cross-sectional view taken along line A-A 'in Fig.
4 is a perspective view showing a multilayer ceramic capacitor according to another embodiment of the present invention.
5 is a cross-sectional view showing the internal electrode structure of the multilayer ceramic capacitor shown in FIG.
6 is a cross-sectional view taken along line A-A 'of FIG.
7 is a perspective view showing a multilayer ceramic capacitor according to another embodiment of the present invention.
8 is a perspective view showing a state in which the multilayer ceramic capacitor of FIG. 5 is mounted on a printed circuit board.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings may be exaggerated for clarity of description, and the elements denoted by the same reference numerals in the drawings are the same elements.

Multilayer Ceramic Capacitors

1 is a schematic perspective view showing a multilayer ceramic capacitor according to an embodiment of the present invention.

2 is a cross-sectional view showing an internal electrode structure of the multilayer ceramic capacitor shown in FIG.

3 is a cross-sectional view taken along line A-A 'in Fig.

The multilayer ceramic capacitor according to the present embodiment may be a three-terminal vertical stacked capacitor. The term " vertically laminated or vertical multilayer " means that the stacked internal electrodes in the capacitor are disposed perpendicular to the mounting area of the circuit board, and " 3-terminal " Terminal is connected to the circuit board.

1 and 2, the multilayer ceramic capacitor 100 according to the present embodiment includes a ceramic body 110; Internal electrodes (121, 122) formed inside the ceramic body; 142, 143, and 144 and external electrodes 131, 132, and 133, respectively, formed on one surface of the ceramic body.

In the present embodiment, the ceramic body 110 has a first surface 1 and a second surface 2 facing each other in the width direction, and a third longitudinal surface 3 connecting the first surface and the second surface. A fourth surface 4, a fifth surface 5 in the thickness direction, and a sixth surface 6. [

The shape of the ceramic body 110 is not particularly limited, but may be a hexahedron having first to sixth surfaces as shown in the figure.

According to one embodiment of the present invention, the third surface 3 and the fourth surface 4 are opposed to each other, and the fifth surface 5 and the sixth surface 6 are opposed to each other.

According to one embodiment of the present invention, the first surface 1 of the ceramic body may be a mounting surface arranged in the mounting region of the circuit board.

According to one embodiment of the present invention, the x-direction is a direction in which the first to third external electrodes are formed at a predetermined interval, the y-direction is a direction in which the internal electrodes are stacked with the dielectric layer sandwiched therebetween, Direction may be a direction in which the internal electrode is mounted on the circuit board.

According to an embodiment of the present invention, the ceramic body 110 may be formed by stacking a plurality of dielectric layers 111. The plurality of dielectric layers 111 constituting the ceramic body 110 are sintered so that the boundaries between adjacent dielectric layers can be unified so as not to be confirmed.

The longitudinal length of the ceramic body may be 1.0 mm or less, but is not limited thereto.

The dielectric layer 111 may be formed by firing a ceramic green sheet including a ceramic powder, an organic solvent, and an organic binder. The ceramic powder may be a material having a high dielectric constant, but not limited thereto, a barium titanate (BaTiO 3 ) -based material, a strontium titanate (SrTiO 3 ) -based material, or the like can be used.

According to an embodiment of the present invention, the first and second inner electrodes 121 and 122 may be disposed inside the ceramic body 110.

2 is a cross-sectional view showing a dielectric layer 111 constituting the ceramic body 110 and internal electrodes 121 and 122 arranged in the dielectric layer.

According to one embodiment of the present invention, the pair of the first inner electrode 121 of the first polarity and the second inner electrode 122 of the second polarity can be formed as a pair, Direction so as to face each other.

According to an embodiment of the present invention, the first and second internal electrodes 121 and 122 are disposed in a stacked state of the multilayer ceramic capacitor, that is, perpendicular to the first widthwise side 1 of the ceramic body 110 .

In the present invention, the first and second may mean different polarities, and the first and third may mean the same polarity.

According to an embodiment of the present invention, the first and second internal electrodes 121 and 122 may be formed of a conductive paste containing a conductive metal.

The conductive metal may be, but is not limited to, nickel (Ni), copper (Cu), palladium (Pd), or an alloy thereof.

The internal electrode layer can be printed with a conductive paste through a printing method such as a screen printing method or a gravure printing method on a ceramic green sheet forming a dielectric layer.

The ceramic green sheet on which the internal electrodes are printed may be alternately laminated and fired to form the ceramic body.

2 and 3, the first and second internal electrodes 121 and 122 have lead portions 121a, 121b and 122a, respectively, to be connected to external electrodes having different polarities, , 121b and 122a may be exposed on the first widthwise side 1 of the ceramic body.

According to one embodiment of the present invention, the multilayer ceramic capacitor is vertically stacked, and the lead portion of the first internal electrode and the lead portion of the second internal electrode can be exposed to the same side of the ceramic body.

According to an embodiment of the present invention, the lead-out portion of the internal electrode may be an area exposed to one surface of the ceramic body due to an increase in the width W of the conductor pattern forming the internal electrode.

According to an embodiment of the present invention, the first internal electrode may have two lead portions 121a and 121b.

The two lead portions 121a and 121b of the first internal electrode are disposed at predetermined intervals and can be exposed to the first surface 1 in the width direction of the ceramic body.

According to an embodiment of the present invention, the first lead portion 121a of the first internal electrode may be exposed to the first widthwise surface 1 of the ceramic body and simultaneously exposed to the third lengthwise surface 3 And the second lead portion 121b of the first internal electrode is exposed to the first widthwise surface 1 of the ceramic body and simultaneously exposed to the fourth longitudinally facing surface 4.

According to one embodiment of the present invention, the second internal electrode may have one lead portion 122a.

The third lead portion 122a of the second internal electrode is disposed at a predetermined distance from the third and fourth surfaces 3 and 4 in the longitudinal direction of the ceramic body, ). ≪ / RTI >

Means that the third lead portion 122a of the second internal electrode is not exposed to the third and fourth surfaces 3 and 4 in the longitudinal direction of the ceramic body, State.

The two lead portions 121a and 121b of the first internal electrode may be spaced apart from the lead portion 122a of the second internal electrode by a predetermined gap G, respectively.

The above-mentioned "spacing apart by the predetermined gap G" means an insulated state without overlapping with each other, and the same meaning is used in the following.

More specific details will be described later.

The end portions of the first and second internal electrodes 121 and 122 may be exposed to the third and fourth surfaces 3 and 4 in the longitudinal direction of the ceramic body 110. According to an embodiment of the present invention, have. An insulating layer is formed on the third and fourth longitudinal faces 3 and 4 of the ceramic body to prevent short-circuiting between the internal electrodes.

The first and second internal electrodes 121 and 122 may form a margin only on the second widthwise side 2 of the ceramic body 110, And the fourth surface (4) without a margin.

Generally, the first and second internal electrodes form an electrostatic capacitance by overlapping regions, and the lead portions connected to the external electrodes having different polarities do not have overlapping regions.

On the other hand, attempts have been made to increase the capacitance by forming the lead portions connected to the external electrodes having different polarities to overlap each other.

However, in this case, a short failure problem may occur in the overlapped region of the lead portion exposed to the outside.

According to an embodiment of the present invention, in order to solve the above problem, the two lead portions 121a and 121b of the first internal electrode are separated from the lead portion 122a of the second internal electrode by a predetermined distance .

If the predetermined spacing of the first and second lead portions 121a and 121b from the third lead portion 122a is G, 0? G? 50 占 퐉 can be satisfied.

By adjusting the gap G so that the first and second lead portions 121a and 121b are spaced apart from the third lead portion 122a by 0? G? 50 占 퐉, The problem of defects can be solved.

If the predetermined gap G between the first and second lead portions 121a and 121b is 0 占 퐉, the first and second lead portions 121a and 121b are separated from the third lead portion 122a, 121b and the third lead portion 122a are coincident with each other, there is no overlapping region, and no problem of short failure occurs. However, when the interval is less than 0 占 퐉 (defined as having a negative value) A short-circuit defect may occur in the chip cutting process.

On the other hand, when the predetermined gap G between the first and second lead portions 121a and 121b is different from the third lead portion 122a, The distance between the second internal electrodes increases and the current loop becomes longer, so that the equivalent series inductance (ESL) can be increased.

According to an embodiment of the present invention, when the width of the third lead portion 122a is W1 and the width of the third external electrode 133 connected to the third lead portion 122a is W2, 1.0? W1 / W2 < / = 2.0.

As described above, when the ratio of the width W1 of the third lead portion 122a to the width W2 of the third external electrode 133 connected to the third lead portion 122a is 1.0? W1 / W2? 2.0 It is possible to lower the equivalent series inductance (ESL), and it is possible to prevent a short failure and to have an excellent reliability.

The ratio W1 / W2 of the width W1 of the third lead portion 122a to the width W2 of the third external electrode 133 connected to the third lead portion 122a is less than 1.0 and 2.0 , A short failure may occur and an equivalent series inductance (ESL) may be increased, which is a problem.

According to an embodiment of the present invention, an external electrode may be disposed on one surface of the ceramic body so as to be connected to the internal electrode.

More specifically, the first external electrode 131 may be disposed so as to be connected to the first lead portion 121a of the first internal electrode 121 exposed in the first widthwise surface 1 of the ceramic body 110 And the second external electrode 132 may be disposed so as to be connected to the second lead portion 121b of the first internal electrode exposed on the first widthwise surface 1 of the ceramic body 110. [

The first and second external electrodes 131 and 132 may be connected to a part of the first and second lead portions 121a and 121b without being particularly limited.

The third external electrode 133 may be formed to be connected to the third lead portion 122a of the second internal electrode 122 extended to the first widthwise surface 1 of the ceramic body 110 .

According to an embodiment of the present invention, insulating layers 141, 142, 143, and 144 may be formed on one surface of the ceramic body 110.

More specifically, the first insulating layer 141 and the second insulating layer 142 may be formed on the first widthwise surface 1 of the ceramic body, and the third longitudinal surface 3 and fourth A third insulating layer 143 and a fourth insulating layer 144 may be formed on the surface 4, respectively.

The first insulating layer 141 formed on the first widthwise surface 1 of the ceramic body 110 may be formed between the first and third external electrodes 131 and 133 and the second insulating layer 142 May be formed between the second and third external electrodes 132 and 133.

The first and second insulating layers 141 and 142 may be formed to cover the lead portions 121a and 121b of the first internal electrode exposed at the first surface and the lead portion 122a of the second internal electrode .

The first and second insulating layers 141 and 142 may be formed so as to cover the exposed portions of the lead portions 121a and 121b of the first internal electrode and the lead portion 122a of the second internal electrode.

According to an embodiment of the present invention, as shown in FIG. 3, the first and second insulating layers 141 and 142 may be formed to completely fill the first widthwise surface 1 of the ceramic body.

Although not shown, according to an embodiment of the present invention, the first and second insulating layers 141 and 142 are formed to be spaced apart from the first to third external electrodes 131, 132, and 133 .

According to one embodiment of the present invention, a third insulating layer (not shown) is formed on the third surface and the fourth surface in the longitudinal direction of the ceramic body 110 where the ends of the first and second internal electrodes 121 and 122 are exposed, 143 and a fourth insulating layer 144 may be formed.

The third insulating layer 143 may be connected to the margin sub-dielectric layer 111 formed on the second widthwise side 2 of the ceramic body.

The fourth insulating layer 144 may be connected to the margin sub-dielectric layer 111 formed on the second widthwise side 2 of the ceramic body.

According to an embodiment of the present invention, the insulating layer may be formed of the same or similar material as the dielectric layer, and the bonding strength between the insulating layer and the ceramic body may be improved when the dielectric layer is connected to the dielectric layer.

According to one embodiment of the present invention, the insulating layers 141, 142, 143, and 144 may be formed of a ceramic slurry. The position and height of the insulating layer can be adjusted by adjusting the amount and shape of the ceramic slurry. The insulating layers 141, 142, 143, and 144 may be formed by forming a ceramic body by a firing process, applying a ceramic slurry to the ceramic body, and firing the ceramic body.

Or may be formed by firing together with a ceramic green sheet to form a ceramic slurry for forming an insulating layer on the ceramic green sheet forming the ceramic body.

The method of forming the ceramic slurry is not particularly limited, and for example, a spray method, a coating method using a roller, a coating method, and the like can be used.

According to an embodiment of the present invention, the insulating layers 141, 142, 143, and 144 include lead portions 121a, 121b, and 122a of the first and second internal electrodes exposed on one surface of the ceramic body, 2 It is possible to cover the end portions of the internal electrodes 121 and 122 to prevent short-circuiting between the internal electrodes and to prevent internal defects such as degradation of moisture resistance.

According to an embodiment of the present invention, the distance between the first and second internal electrodes to which the external polarity is applied is shortened, so that the current loop can be shortened, so that the equivalent series inductance (ESL) Can be lowered.

According to an embodiment of the present invention, the height of the first and second insulating layers 141 and 142 may be smaller than the height of the first, second, and third external electrodes 131, 132, and 133.

The heights of the insulating layers 141 and 142 and the external electrodes 131, 132, and 133 may be measured based on the first surface.

According to an embodiment of the present invention, the height of the first and second insulating layers 141 and 142 is lower than the height of the first to third external electrodes 131, 132, and 133 so that the multilayer ceramic capacitor As shown in Fig.

Although not shown, the height of the first and second insulating layers 141 and 142 may be different from each other.

4 is a perspective view showing a multilayer ceramic capacitor according to another embodiment of the present invention.

5 is a cross-sectional view showing the internal electrode structure of the multilayer ceramic capacitor shown in FIG.

6 is a cross-sectional view taken along line A-A 'of FIG.

The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown.

Referring to FIGS. 4 to 6, the multilayer ceramic capacitor according to the present embodiment may be a six-terminal vertical stacked capacitor.

&Quot; 6-terminal " means a terminal of a capacitor, and 6 terminals can be connected to a circuit board.

The multilayer ceramic capacitor 200 according to the present embodiment includes a ceramic body 210; Internal electrodes (221, 222) disposed inside the ceramic body; And may include insulating layers 241, 242, 243, 244, 245 and 246 and external electrodes 231, 232, 233, 234, 235 and 236 formed on one surface of the ceramic body 210.

5 is a cross-sectional view showing a dielectric layer 211 constituting the ceramic body 210 and internal electrodes 221 and 222 formed in the dielectric layer.

According to one embodiment of the present invention, the pair of the first internal electrode 221 of the first polarity and the second internal electrode 222 of the second polarity may be formed as a pair, Direction so as to face each other.

According to one embodiment of the present invention, the first and second internal electrodes 221 and 222 may be disposed perpendicular to the mounting surface of the multilayer ceramic capacitor.

According to the present embodiment, the mounting surface of the multilayer ceramic capacitor may be the first surface 1 of the ceramic body or the second surface 2 opposite thereto.

Referring to FIGS. 5 and 6, the first and second internal electrodes 221 and 222 are respectively connected to external electrodes having different polarities, such as lead portions 221a, 221b, 221c, 221d, 222a, and 222b Lt; / RTI >

According to one embodiment of the present invention, the multilayer ceramic capacitor is vertically stacked, and the lead portion of the first internal electrode and the lead portion of the second internal electrode can be exposed to the same side of the ceramic body.

According to an embodiment of the present invention, the first internal electrode 221 may have four lead portions 221a, 221b, 221c and 221d.

According to an embodiment of the present invention, the two lead portions 221a and 221b of the first internal electrode 221 are exposed at the first surface 1 in the width direction of the ceramic body at predetermined intervals, The other two lead portions 221c and 221d of the first internal electrode 221 can be exposed to the second surface 2 facing the first widthwise surface 1 of the ceramic body at a predetermined interval .

According to an embodiment of the present invention, the first lead portion 221a of the first internal electrode 221 is exposed to the first widthwise surface 1 of the ceramic body 210, And the second lead portion 221b of the first internal electrode 221 is exposed to the first widthwise surface 1 of the ceramic body 210 and is exposed to the fourth longitudinally facing surface 4). ≪ / RTI >

Similarly, the third lead 221c of the first internal electrode 221 is exposed to the second widthwise surface 2 of the ceramic body 210 and at the same time, And the fourth lead portion 221d of the first internal electrode 221 is exposed to the second widthwise surface 2 of the ceramic body 210 and exposed to the fourth longitudinally facing surface 4 .

According to an embodiment of the present invention, the second internal electrode 222 may have two lead portions 222a and 222b.

According to an embodiment of the present invention, the fifth lead portion 222a of the second internal electrode 222 is spaced apart from the third and fourth surfaces 3 and 4 in the longitudinal direction of the ceramic body And the sixth lead portion 222b of the second internal electrode 222 is exposed on the third surface in the lengthwise direction of the ceramic body 210 3 and the fourth surface 4 and may be exposed to the second surface 2 facing the first widthwise side 1 of the ceramic body 210. [

The first and second lead portions 221a and 221b of the first internal electrode may be spaced apart from the fifth lead portion 222a of the second internal electrode by a predetermined gap G, respectively.

In a similar manner, the third and fourth lead portions 221c and 221d of the first internal electrode may be spaced apart from the sixth lead portion 222b of the second internal electrode by a predetermined gap G, respectively.

The end portions of the first and second internal electrodes 221 and 222 are exposed to the third and fourth surfaces 3 and 4 in the longitudinal direction of the ceramic body 210 according to an embodiment of the present invention. .

An insulating layer is formed on the third and fourth longitudinal faces 3 and 4 of the ceramic body 210 to prevent a short circuit between the first and second internal electrodes.

Referring to FIG. 6, external electrodes may be formed on one surface of the ceramic body to be connected to internal electrodes.

More specifically, the first and second lead portions 221a and 221b of the first internal electrode 221 exposed in the widthwise first surface 1 of the ceramic body 210 are connected to the first and second lead portions 221a and 221b, 2 external electrodes 231 and 233 may be formed.

The fifth external electrode 235 may be formed to be connected to the fifth lead portion 222a of the second internal electrode 222 exposed in the widthwise first surface 1 of the ceramic body 210 .

Similarly, the third and fourth external electrodes 233 and 233 are connected to the third and fourth lead portions 221c and 221d of the first internal electrode exposed to the second surface 2 in the width direction of the ceramic body, respectively. And a sixth external electrode 236 may be formed to be connected to the sixth lead portion 222b of the second internal electrode exposed on the second surface of the ceramic body.

The first to fourth external electrodes 231, 232, 233, and 234 may be formed of a part of the first to fourth lead portions 221a, 221b, 221c, and 221d of the first internal electrode, Can be connected.

According to an embodiment of the present invention, insulating layers 241, 242, 243, 244, 245, and 246 may be formed on one surface of the ceramic body.

More specifically, the first insulating layer 241 and the second insulating layer 242 may be formed on the first surface in the width direction of the ceramic body, and the third insulating layer 242 and the second insulating layer 242 may be formed on the third surface and the fourth surface, A fourth insulating layer 244 and a fifth insulating layer 245 and a sixth insulating layer 246 may be formed on the second surface in the width direction of the ceramic body.

The first insulating layer 241 formed on the first widthwise surface of the ceramic body may be formed between the first and fifth external electrodes 231 and 235 and the second insulating layer 242 may be formed between the second and fifth And may be formed between the external electrodes 232 and 235.

The first and second insulating layers 241 and 242 may be formed to cover the lead portions 221a and 221b of the first internal electrode exposed at the first surface and the lead portion 222a of the second internal electrode . The first and second insulating layers 241 and 242 may be formed to cover the exposed portion of the first internal electrode and the exposed portion of the second internal electrode.

According to an embodiment of the present invention, the first and second insulating layers 241 and 242 may be formed to completely fill the first widthwise surface of the ceramic body.

Although not shown, according to one embodiment of the present invention, the first and second insulating layers 241 and 242 are spaced apart from the first, second, and fifth external electrodes 231, 232, and 235 by a predetermined distance .

In addition, a fifth insulating layer 245 and a sixth insulating layer 246 may be formed on the second surface of the ceramic body in a similar manner.

According to an embodiment of the present invention, a third insulating layer 243 and a fourth insulating layer 243 are formed on the third surface and the fourth surface of the ceramic body in which the ends of the first and second internal electrodes 221 and 222 are exposed, (244) may be formed.

According to an embodiment of the present invention, the insulating layer may be formed of the same or similar material as the dielectric layer, and the bonding strength between the insulating layer and the ceramic body may be improved when the dielectric layer is connected to the dielectric layer.

The insulating layer covers the end portions of the first and second internal electrodes exposed at one surface of the ceramic body and the lead portions of the first and second internal electrodes to prevent short-circuiting between the internal electrodes and to prevent internal defects such as degradation of moisture- .

According to the present embodiment, the distance between the first and second internal electrodes to which the external polarity is applied may be shortened so that the current loop may be shortened, thereby lowering the equivalent series inductance (ESL) .

Although not shown, the first internal electrode or the second internal electrode may have two or more lead portions, and the lead portions formed on the first internal electrode or the second internal electrode may be exposed to the same side of the ceramic body, Lt; / RTI > The number of lead portions of the internal electrode, the position of the lead portion, and the like may be variously changed by those skilled in the art.

7 is a perspective view showing a multilayer ceramic capacitor according to another embodiment of the present invention.

Referring to FIG. 7, in the multilayer ceramic capacitor according to another embodiment of the present invention, in the multilayer ceramic capacitor according to the embodiment of the present invention shown in FIG. 4, The fifth insulating layer 245 may be disposed in place of the third, fourth and sixth external electrodes 233, 234 and 236 and the fifth and sixth insulating layers 245 and 246 disposed in the second insulating layer 2.

In this case, the third and fourth lead portions 221c and 221d and the sixth lead portion 222b are exposed by the second surface 2 in the width direction of the ceramic body 210, 245 so that the problem of reliability deterioration does not occur.

Hereinafter, the present invention will be described in more detail by way of examples, but the present invention is not limited thereto.

Example

The embodiment is characterized in that the first and second lead portions of the first internal electrode of the vertical stacked capacitor are respectively spaced apart from the third lead portion of the second internal electrode by a predetermined gap G and a width W1 of the third lead portion, (W1 / W2) of the width (W2) of the third external electrode connected to the lead-out portion satisfies the numerical range of the present invention.

Comparative Example

In the comparative example, the first and second lead portions of the first internal electrode of the vertical stacked-type capacitor are spaced apart from the third lead portion of the second internal electrode by a predetermined gap G and a width W1 of the third lead portion, And the ratio (W1 / W2) of the width (W2) of the third external electrode connected to the lead-out portion deviates from the range of the present invention.

Table 1 below shows the relationship between the first and second lead portions of the first internal electrode of the vertical stacked capacitor according to the embodiment of the present invention at a predetermined gap G spaced from the third lead portion of the second internal electrode The equivalent series inductance (ESL) and the reliability according to the number of short circuits are compared.

The reliability evaluation according to the number of generated shorts was performed by measuring the number of shorts generated for 50 samples. The width W1 of the third lead portion and the width W2 of the third external electrode connected to the third lead portion And the ratio (W1 / W2) was fixed at 1.7.

Sample The gap (G) between the first and second draw-out portions and the third draw-
(μm)
Equivalent series inductance (ESL)
(pH)
Number of short occurrences
(dog)
*One -200 19.8 25 *2 -100 20.4 12 * 3 -50 20.8 6 *4 -20 21.1 2 5 0 22.8 0 6 20 23.6 0 7 50 24.7 0 *8 75 28.1 0 * 9 100 32.2 0 * 10 150 40.3 0

*: Comparative Example

Referring to Table 1, in the case of Samples 1 to 4 as comparative examples, the predetermined gap G between the first and second lead portions of the first internal electrode and the third lead portion of the second internal electrode is negative -), which means a case where the drawing units overlap each other.

 In this case, it can be seen that there is a problem in reliability due to a large number of short circuits.

Samples 8 to 10, which are comparative examples, are those in which the predetermined gap G between the first and second lead portions of the first internal electrode and the third lead portion of the second internal electrode exceeds 50 mu m, It can be seen that there is a problem because the series inductance (ESL) is high.

On the other hand, the samples 5 to 7 of the embodiments satisfy the numerical range of the present invention, and it is understood that the equivalent series inductance (ESL) is low and there is no occurrence of a short circuit, and therefore the reliability is excellent.

Table 2 below shows the ratio (W1 / W2) of the width W1 of the third lead portion of the vertical stacked capacitor to the width W2 of the third external electrode connected to the third lead portion according to the embodiment of the present invention. (Equivalent series inductance) and the reliability according to the number of short circuits.

The reliability evaluation according to the number of generated shorts was made by measuring the number of shorts generated for 50 samples. The first and second lead portions of the first internal electrode were each separated from the third lead portion of the second internal electrode The gap (G) was measured at 0, 20, and 50 μm.

Sample The gap (G) between the first and second draw-out portions and the third draw-
(μm)
W1 / W2 Equivalent series inductance (ESL)
(pH)
Number of short occurrences
(dog)
* 11 0 0.8 23.1 4 12 0 1.0 22.9 0 13 0 1.5 22.8 0 14 0 2.0 22.9 0 * 15 0 2.5 23.2 One * 16 20 0.8 24.1 3 17 20 1.0 23.8 0 18 20 1.5 23.6 0 19 20 2.0 23.7 0 * 20 20 2.5 23.9 3 * 21 50 0.8 25.3 One 22 50 1.0 24.8 0 23 50 1.5 24.6 0 24 50 2.0 24.7 0 * 25 50 2.5 25.4 5

*: Comparative Example

In the samples 11, 15, 16, 20, 21 and 25 of the comparative example, the width W1 of the third lead-out portion and the width W2 of the third external electrode connected to the third lead- (W1 / W2) is out of the numerical range of the present invention. As a result, there is a problem in terms of reliability due to a short defect, and there is a problem because the equivalent series inductance (ESL) is high.

On the other hand, the samples 12 to 14, 17 to 19 and 22 to 24, which are examples, satisfy the numerical range of the present invention and show that the equivalent series inductance (ESL) .

The mounting substrate of the multilayer ceramic capacitor

8 is a perspective view showing a state in which the multilayer ceramic capacitor of FIG. 5 is mounted on a printed circuit board.

8, the mounting substrate 300 of the multilayer ceramic capacitor 200 according to the present embodiment includes a printed circuit board 310 mounted so that the multilayer ceramic capacitor 200 is vertically aligned with the printed circuit board 310, And first and second electrode pads 321, 322, and 323 spaced apart from each other on the upper surface of the substrate.

At this time, the multilayer ceramic capacitor 200 is formed such that the first, second and fifth external electrodes 231, 232 and 235 are in contact with the first and second electrode pads 321 and 322 and the third electrode pad 323, And may be electrically connected to the printed circuit board 310 by solder.

Except for the above description, the overlapping description of the features of the multilayer ceramic capacitor according to the embodiment of the present invention described above will be omitted here.

The present invention is not limited to the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

100, 200; A multilayer ceramic capacitor 110, 210; Ceramic body
111, 211; Dielectric layer
121, 122, 221, 222; The first and second internal electrodes
121a, 121b, 122a, 221a, 221b, 221c, 221d, 222a, 222b; The first through sixth draw-
131, 132, 133, 231, 232, 233, 234, 235, 236; The first to sixth external electrodes
300; A mounting substrate 310; Printed circuit board
321, 322, 323; The first to third electrode pads

Claims (26)

  1. A ceramic body including a plurality of dielectric layers;
    A ceramic body having first and second lead portions exposed in a first widthwise direction of the ceramic body and spaced apart from each other by a predetermined distance, And a third lead portion exposed through the first surface in the width direction of the ceramic body and spaced apart from the first lead portion and the second lead portion by a predetermined distance, Internal electrodes;
    First to third external electrodes disposed on a first surface in a width direction of the ceramic body and connected to the first to third lead portions, respectively; And
    And an insulating layer disposed on the first surface or the third surface in the width direction of the ceramic body and on the fourth surface,
    Wherein the insulating layer is formed of a ceramic slurry and the width of the third lead portion is W1 and the width of the third external electrode connected to the third lead portion is W2, 1.0?? W1 / W2? Multilayer Ceramic Capacitors.
  2. delete
  3. delete
  4. The method according to claim 1,
    Wherein the insulating layer formed of the ceramic slurry is a first surface in the width direction of the ceramic body, a third surface in the longitudinal direction, and a fourth surface.
  5. The method according to claim 1,
    And the third lead portion is disposed between the first and second lead portions.
  6. The method according to claim 1,
    And G < / = 50 [mu] m, where G is the predetermined distance between the first and second lead portions spaced from the third lead portion.
  7. delete
  8. The method according to claim 1,
    Wherein the first and second internal electrodes are disposed perpendicular to a first width-wise surface of the ceramic body.
  9. The method according to claim 1,
    And the first and second external electrodes are connected to a part of the first and second lead portions.
  10. The method according to claim 1,
    Wherein the insulating layer is formed by applying and firing a ceramic slurry after firing the ceramic body.
  11. The method according to claim 1,
    Wherein the insulating layer is formed by firing simultaneously with the ceramic body.
  12. The method according to claim 1,
    Wherein an insulating layer formed on a first surface of the ceramic body is disposed smaller than a height of first and second external electrodes measured from a first surface of the ceramic body.
  13. The method according to claim 1,
    And fourth to sixth external electrodes are further disposed on the second surface in the width direction of the ceramic body.
  14. A ceramic body including a plurality of dielectric layers;
    The ceramic body has first to fourth lead portions exposed in the first and second surfaces in the width direction of the ceramic body with a predetermined interval therebetween. And a fifth and sixth lead portions exposed by the first and second surfaces in the width direction of the ceramic body and spaced apart from the first to fourth lead portions by a predetermined distance, A second internal electrode exposed in a third surface and a fourth surface;
    First to sixth external electrodes disposed on the first and second surfaces in the width direction of the ceramic body and connected to the first to sixth lead portions, respectively; And
    An insulating layer disposed on a first surface and a second surface in the width direction of the ceramic body or a third surface and a fourth surface in the longitudinal direction of the ceramic body,
    The insulating layer is formed of a ceramic slurry and the width of the fifth or sixth lead portion is W1 and the width of the fifth or sixth external electrode connected to the fifth or sixth lead portion is W2, W1 / W2 < / = 2.0.
  15. delete
  16. delete
  17. 15. The method of claim 14,
    Wherein the insulating layer formed of the ceramic slurry is a first surface in the width direction of the ceramic body, a second surface, a third surface in the length direction, and a fourth surface.
  18. 15. The method of claim 14,
    Wherein the fifth lead portion is disposed between the first lead portion and the second lead portion, and the sixth lead portion is disposed between the third lead portion and the fourth lead portion.
  19. 15. The method of claim 14,
    And G < / = 50 [mu] m, where G is the predetermined distance between the first and fourth lead portions spaced from the fifth and sixth lead portions, respectively.
  20. delete
  21. 15. The method of claim 14,
    Wherein the first and second internal electrodes are disposed perpendicular to a mounting surface of the ceramic body.
  22. 15. The method of claim 14,
    And the first to fourth external electrodes are connected to a part of the first to fourth lead portions.
  23. 15. The method of claim 14,
    Wherein the insulating layer is formed by applying and firing a ceramic slurry after firing the ceramic body.
  24. 15. The method of claim 14,
    Wherein the insulating layer is formed by firing simultaneously with the ceramic body.
  25. 15. The method of claim 14,
    Wherein the insulating layer formed on the first surface or the second surface in the width direction of the ceramic body is formed to be smaller than the height of the first through sixth external electrodes measured from the first surface or the second surface in the width direction of the ceramic body, Capacitor.
  26. A printed circuit board having first to third electrode pads on its upper surface; And
    And a multilayer ceramic capacitor according to any one of claims 1 to 14 provided on the printed circuit board.
KR1020160109349A 2013-07-17 2016-08-26 Multi-layered ceramic capacitor part and board for mounting the same KR101912279B1 (en)

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