JPH0653002A - Electronic element - Google Patents

Electronic element

Info

Publication number
JPH0653002A
JPH0653002A JP20125992A JP20125992A JPH0653002A JP H0653002 A JPH0653002 A JP H0653002A JP 20125992 A JP20125992 A JP 20125992A JP 20125992 A JP20125992 A JP 20125992A JP H0653002 A JPH0653002 A JP H0653002A
Authority
JP
Japan
Prior art keywords
main body
electrode
chip element
electrode terminal
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20125992A
Other languages
Japanese (ja)
Inventor
Zenichi Tamaki
善一 玉木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP20125992A priority Critical patent/JPH0653002A/en
Publication of JPH0653002A publication Critical patent/JPH0653002A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To directly recognize whether mounting is normal by forming through holes from electrode terminals to the opposite surface side, in the electrode terminals and a main body. CONSTITUTION:In a main body 11 and electrode terminals 12a, 12b, through holes 14 are formed from the electrode terminals 12a, 12b to the opposite surface of the main body 11. When a chip element is mounted on a circuit board 15, the electrode terminals 12a, 12b of the chip element are made to correspond with land electrodes 16a, 16b of the circuit board 15 by face down, the chip element is mounted on a circuit board 15, and soldering process is performed. Next the soldering state is visually observed from above. When the connection is perfect like the soldering part 13a between the electrode terminal 12a and the land electrode 16a, solder does not creep up in the through hole 14a. On the contrary, when the connection is imperfect like the soldering part 13b between the electrode terminal 12b and the land electrode 16b, the soldering part 13b creeps up as far as the upper part of the through hole 14b. Thereby whether mounting is normal can be discrimated and confirmed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、チップ抵抗、チップ
コンデンサ、半導体素子等の本体が板状をした電子素子
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic element such as a chip resistor, a chip capacitor and a semiconductor element whose main body is plate-shaped.

【0002】[0002]

【従来の技術】フェースダウン方式で回路基板等に実装
するチップ素子(電子素子)は、従来、図5に示すよう
に、板状の素子本体51の下面に設けた電極端子52
に、さらに半田バンプ53を形成し、この半田バンプ5
3部分を、フェースダウンにより、回路基板54上のラ
ンド電極55に載置し、半田処理して、回路基板54に
実装している。
2. Description of the Related Art A chip element (electronic element) mounted on a circuit board or the like by a face-down method has conventionally been provided with an electrode terminal 52 provided on a lower surface of a plate-shaped element body 51 as shown in FIG.
Solder bumps 53 are further formed on the
The three parts are placed face down on the land electrodes 55 on the circuit board 54, soldered, and mounted on the circuit board 54.

【0003】[0003]

【発明が解決しようとする課題】上記した従来のチップ
素子では、回路基板に実装した後の半田付け状態で、図
6に示すチップ素子51aのように、電極端子52がラ
ンド電極54に半田53で確実に接続された場合と、チ
ップ素子51bのように、電極端子52がランド電極5
4に接続されない場合が生じる。チップ素子51aは正
しく実装され、チップ素子51bは実装不良であり、実
装後、これが確実に視認識別できることが好ましいが、
従来のチップ素子は、本体で半田付け部が覆われてしま
うので、正常実装と不良実装を直接、確認することがで
きないという問題があった。
In the above-mentioned conventional chip element, the electrode terminal 52 is soldered to the land electrode 54 in the solder state after being mounted on the circuit board, like the chip element 51a shown in FIG. And the land electrode 5 is connected to the land electrode 5 like the chip element 51b.
There is a case where it is not connected to 4. It is preferable that the chip element 51a is correctly mounted and the chip element 51b is defectively mounted and that after mounting, it can be surely visually identified.
The conventional chip element has a problem in that the soldering portion is covered by the main body, so that normal mounting and defective mounting cannot be directly confirmed.

【0004】この発明は、上記問題点に着目してなされ
たものであって、回路基板等に実装した場合に、実装の
正常/不良の別を直接確認し得る電子素子を提供するこ
とを目的としている。
The present invention has been made in view of the above problems, and an object thereof is to provide an electronic element capable of directly confirming whether the mounting is normal or defective when mounted on a circuit board or the like. I am trying.

【0005】[0005]

【課題を解決するための手段及び作用】上記課題を解決
するために、請求項1記載の電子素子は、板状の本体の
一面に、半田バンプを形成した電極端子を設けたものに
おいて、前記電極端子及び本体に、電極端子から本体の
他面側にスルーホールを設けている。この電子素子で
は、回路基板に実装され、電極端子と回路基板のランド
電極が半田で正常に接続されると、半田が本体にスルー
ホールにほとんど入らない。これに対し、半田接続が不
良な状態では、半田がスルーホール内に入り、本体上面
付近に至る。本体上面より、スルーホールを目視するこ
とにより、スルーホール内の半田の上がり具合で、実装
の正常/不良を確認できる。
In order to solve the above-mentioned problems, the electronic element according to claim 1 is one in which an electrode terminal having a solder bump is provided on one surface of a plate-shaped main body. Through holes are provided in the electrode terminal and the main body from the electrode terminal to the other surface side of the main body. In this electronic element, when it is mounted on a circuit board and the electrode terminal and the land electrode of the circuit board are normally connected by solder, the solder hardly enters the through hole in the main body. On the other hand, when the solder connection is poor, the solder enters the through hole and reaches the vicinity of the upper surface of the main body. By visually observing the through hole from the top surface of the main body, it is possible to confirm normal / defective mounting by the degree of solder rising in the through hole.

【0006】請求項2記載の電子素子は、板状の本体の
一面に、電極端子を設けたものにおいて、前記電極端子
及び本体に、電極端子から本体の他面側にスルーホール
を設けている。この電子素子では、回路基板のランド電
極側に半田バンプが形成されるものであり、実装された
後は、請求項1記載の電子素子と全く同様の理由で、素
子本体上面より、直接、実装の正常/異常を確認するこ
とができる。
According to another aspect of the present invention, in the electronic element, the electrode terminal is provided on one surface of the plate-shaped main body, and the through hole is provided on the electrode terminal and the main body on the other surface side of the main body. . In this electronic element, solder bumps are formed on the land electrode side of the circuit board, and after mounting, the mounting is directly performed from the upper surface of the element body for the same reason as the electronic element according to claim 1. The normality / abnormality of can be confirmed.

【0007】[0007]

【実施例】以下、実施例により、この発明をさらに詳細
に説明する。図1は、この発明の一実施例を示す側面図
である。図1において、チップ素子10は、板状の本体
11の一面(下面)に電極端子12が設けられており、
この電極端子12の表面には、さらに半田バンプ13が
形成されている。以上の構成は図5に示したチップ素子
と特に変わるところはない。
The present invention will be described in more detail with reference to the following examples. FIG. 1 is a side view showing an embodiment of the present invention. In FIG. 1, a chip element 10 has an electrode terminal 12 provided on one surface (lower surface) of a plate-shaped main body 11,
Solder bumps 13 are further formed on the surfaces of the electrode terminals 12. The above structure is not different from that of the chip element shown in FIG.

【0008】この実施例チップ素子10の特徴は、本体
11、及び電極端子12に、電極端子12からチップ素
子本体11の他面(上面)にかけてスルーホール14を
設けたことである。このようなチップ素子10を、回路
基板に実装するには、フェースダウンにより、チップ素
子10の電極端子12部分を、回路基板15のランド電
極16に対応させて、回路基板15上に載置し、半田付
け処理を行う。
A feature of the chip element 10 of this embodiment is that a through hole 14 is provided in the main body 11 and the electrode terminal 12 from the electrode terminal 12 to the other surface (upper surface) of the chip element main body 11. To mount such a chip element 10 on a circuit board, the electrode terminal 12 portion of the chip element 10 is placed face down on the circuit board 15 so as to correspond to the land electrode 16 of the circuit board 15. , Perform soldering processing.

【0009】半田付け処理を行った後、チップ素子10
を、図2に示すように、上方から目視すると、図2の左
側の電極端子12aとランド電極16aの半田部13a
のように、完全な接続がなされていると、半田はスルー
ホール14aを上昇しない。したがって、上方から目視
すると、半田部13aは、スルーホール14aの深部に
見える。これに対し、図2の右側の電極端子12bとラ
ンド電極16bの半田部13bのように、完全な接続が
なされていず、半田部13bが上下に離隔していると、
この場合は、半田部13bがスルーホール14bの上部
まで上昇している。したがって、上方から目視すると半
田部13bが、スルーホール14bの上開口から近い浅
部に見える。これら両者を比較すると、半田部13aと
13bの見える深さにLの差があり、目視により、その
いずれであるかを確認することにより、つまり半田部1
3がスルーホール14の深部にある場合には、正常実
装、浅部にあれば、不良実装であることを確認すること
ができる。
After performing the soldering process, the chip element 10
When viewed from above as shown in FIG. 2, the solder portion 13a of the electrode terminal 12a and the land electrode 16a on the left side of FIG.
As described above, the solder does not rise in the through hole 14a when the connection is completely established. Therefore, when viewed from above, the solder portion 13a looks like a deep portion of the through hole 14a. On the other hand, unlike the solder portion 13b of the electrode terminal 12b and the land electrode 16b on the right side of FIG. 2, when the solder portion 13b is vertically separated from each other without being completely connected.
In this case, the solder part 13b has risen to the upper part of the through hole 14b. Therefore, when viewed from above, the solder portion 13b appears as a shallow portion near the upper opening of the through hole 14b. When these two are compared, there is a difference L in the visible depths of the solder portions 13a and 13b, and it is possible to visually confirm which one is the solder portion, that is, the solder portion 1
If 3 is in the deep part of the through hole 14, it can be confirmed that the mounting is normal, and if it is in the shallow part, the mounting is defective.

【0010】図3は、この発明の他の実施例を示す断面
図である。図3において、チップ素子20は、板状の本
体21の一面(下面)に電極端子22が設けられてお
り、またチップ素子本体21及び電極端子22に、電極
端子22からチップ素子本体21の他面(上面)にかけ
てスルーホール24を設けている。以上の構成は、図1
に示したチップ素子と同様である。しかしながら、この
実施例のチップ素子は、図1に示すものと相違して、電
極端子22には、半田バンプを形成していない。
FIG. 3 is a sectional view showing another embodiment of the present invention. In FIG. 3, the chip element 20 has an electrode terminal 22 provided on one surface (lower surface) of a plate-shaped main body 21, and the chip element main body 21 and the electrode terminal 22 are connected from the electrode terminal 22 to the other of the chip element main body 21. A through hole 24 is provided on the surface (upper surface). The above configuration is shown in FIG.
It is similar to the chip element shown in FIG. However, the chip element of this embodiment is different from that shown in FIG. 1 in that no solder bump is formed on the electrode terminal 22.

【0011】このチップ素子20は、自身に半田バンプ
を備えていない代わりに、回路基板25に実装する場合
に、回路基板25のランド電極26上面に、半田バンプ
27を形成しておき、チップ素子20の電極端子22
を、回路基板25の半田バンプ27に対応させて、回路
基板25上にフェースダウンにより載置し、半田付け処
理を行う。
This chip element 20 does not have solder bumps on its own. Instead, when it is mounted on the circuit board 25, solder bumps 27 are formed on the upper surfaces of the land electrodes 26 of the circuit board 25, and the chip element 20 is formed. 20 electrode terminals 22
Corresponding to the solder bumps 27 of the circuit board 25, is placed face down on the circuit board 25, and a soldering process is performed.

【0012】半田付け処理を行った後、チップ素子20
を図4に示すように、上方から目視すると、図4の左側
の電極端子22aとランド電極26aの半田部27aの
ように、完全な接続がなされていると、半田はスルーホ
ール24aを上昇しない。したがって、上方から目視す
ると、半田部27aはスルーホール24aの深部に見え
る。これに対し、図4の右側の電極端子22bとランド
電極26bの半田部27bのように、完全な接続がなさ
れていず半田部27bが上下に離隔していると、この場
合は、やはり半田部27bがスルーホール24bの上部
まで上昇している。そのため、上方から目視すると半田
部27bがスルーホール14bの上開口付近に見える。
したがって、図1の実施例の場合と同様に、半田付け処
理後にチップ素子の上方からスルーホールを目視し、ス
ルーホールに、半田部がどの程度しているかにより、正
常実装/不良実装の別を確認することができる。
After performing the soldering process, the chip element 20
As shown in FIG. 4, when viewed from above, the solder does not rise in the through hole 24a when the connection is made completely like the left side electrode terminal 22a of FIG. 4 and the solder portion 27a of the land electrode 26a. . Therefore, when viewed from above, the solder portion 27a looks like a deep portion of the through hole 24a. On the other hand, when the solder portion 27b is not completely connected and the solder portion 27b is vertically separated like the solder portion 27b of the electrode terminal 22b and the land electrode 26b on the right side in FIG. 27b has risen to the upper part of the through hole 24b. Therefore, when viewed from above, the solder portion 27b can be seen near the upper opening of the through hole 14b.
Therefore, as in the case of the embodiment shown in FIG. 1, after the soldering process, the through hole is visually inspected from above the chip element, and the normal mounting or the defective mounting is discriminated depending on how much the solder portion is in the through hole. You can check.

【0013】[0013]

【発明の効果】この発明によれば、電極端子及び本体
に、電極端子から本体の他面側にスルーホールを設けて
いるので、半田付け処理後に、チップ素子の上方から、
スルーホールを目視し、スルーホールに、半田がつまっ
ているか否かを確認することにより、実装後、直ちに、
実装の正常/異常を識別確認することができる。
According to the present invention, since the electrode terminal and the main body are provided with through holes on the other surface side of the main body from the electrode terminal, after the soldering process, from the upper side of the chip element,
By visually observing the through holes and checking if the through holes are clogged with solder, immediately after mounting,
The normality / abnormality of mounting can be identified and confirmed.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例を示す側面図である。FIG. 1 is a side view showing an embodiment of the present invention.

【図2】同実施例の実装状態の正常/異常の識別確認を
説明するための断面図である。
FIG. 2 is a cross-sectional view for explaining identification / confirmation of normality / abnormality in a mounting state of the embodiment.

【図3】この発明の他の実施例を示す断面図である。FIG. 3 is a sectional view showing another embodiment of the present invention.

【図4】同実施例の実装状態の正常/異常の識別確認を
説明するための断面図である。
FIG. 4 is a cross-sectional view for explaining confirmation of normality / abnormality of mounting state of the embodiment.

【図5】従来のチップ素子の実装を説明するための側面
図である。
FIG. 5 is a side view for explaining mounting of a conventional chip element.

【図6】同従来のチップ素子の実装状態の問題点を説明
するための側面図である。
FIG. 6 is a side view for explaining a problem of a mounting state of the conventional chip element.

【符号の説明】[Explanation of symbols]

10 チップ素子 11 チップ素子本体 12 電極端子 14 スルーホール 10 chip element 11 chip element body 12 electrode terminal 14 through hole

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】板状の本体の一面に、半田バンプを形成し
た電極端子を設けた電子素子において、 前記電極端子及び本体に、電極端子から本体の他面側に
スルーホールを設けたことを特徴とする電子素子。
1. An electronic device having electrode terminals having solder bumps formed on one surface of a plate-shaped main body, wherein through holes are provided on the electrode terminals and the main body from the electrode terminals to the other surface side of the main body. Characteristic electronic device.
【請求項2】板状の本体の一面に、電極端子を設けた電
子素子において、 前記電極端子及び本体に、電極端子から本体の他面側に
スルーホールを設けたことを特徴とする電子素子。
2. An electronic element in which an electrode terminal is provided on one surface of a plate-shaped body, wherein the electrode terminal and the body are provided with through holes on the other surface side of the body from the electrode terminal. .
JP20125992A 1992-07-28 1992-07-28 Electronic element Pending JPH0653002A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20125992A JPH0653002A (en) 1992-07-28 1992-07-28 Electronic element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20125992A JPH0653002A (en) 1992-07-28 1992-07-28 Electronic element

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2005135629A Division JP2005311387A (en) 2005-05-09 2005-05-09 Soldered joint checking method of electronic device

Publications (1)

Publication Number Publication Date
JPH0653002A true JPH0653002A (en) 1994-02-25

Family

ID=16437981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20125992A Pending JPH0653002A (en) 1992-07-28 1992-07-28 Electronic element

Country Status (1)

Country Link
JP (1) JPH0653002A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005008698A1 (en) * 2003-07-22 2005-01-27 Murata Manufacturing Co., Ltd. Surface mounting type part
JP2017037901A (en) * 2015-08-07 2017-02-16 株式会社村田製作所 Multilayer capacitor, and wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005008698A1 (en) * 2003-07-22 2005-01-27 Murata Manufacturing Co., Ltd. Surface mounting type part
US8059420B2 (en) 2003-07-22 2011-11-15 Murata Manufacturing Co., Ltd. Surface mountable device
JP2017037901A (en) * 2015-08-07 2017-02-16 株式会社村田製作所 Multilayer capacitor, and wiring board

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