JPS62257755A - Substrate for loading semiconductor - Google Patents
Substrate for loading semiconductorInfo
- Publication number
- JPS62257755A JPS62257755A JP10157186A JP10157186A JPS62257755A JP S62257755 A JPS62257755 A JP S62257755A JP 10157186 A JP10157186 A JP 10157186A JP 10157186 A JP10157186 A JP 10157186A JP S62257755 A JPS62257755 A JP S62257755A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- hole
- semiconductor
- conductor pin
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 57
- 229910000679 solder Inorganic materials 0.000 claims abstract description 33
- 230000004907 flux Effects 0.000 abstract description 7
- 238000007598 dipping method Methods 0.000 abstract description 4
- 238000002309 gasification Methods 0.000 abstract description 2
- 239000012466 permeate Substances 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 4
- 238000007654 immersion Methods 0.000 description 3
- 230000013011 mating Effects 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/306—Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
- H05K3/308—Adaptations of leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、各種の所謂゛ト導体素子、或は半導体チップ
を搭載するために用いられる半導体搭載用基板に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a semiconductor mounting substrate used for mounting various so-called conductor elements or semiconductor chips.
（従来の技術）
一般に導体ピンを有する半導体搭載用基板としては、ピ
ングリッドアレイ型半導体搭載用基板かあり、セラミッ
ク基板を基材としてＨｌいている。(Prior Art) Generally, as a semiconductor mounting board having conductor pins, there is a pin grid array type semiconductor mounting board, which uses a ceramic substrate as a base material.
しかしながら、基材としてセラミ・ンク基板を用いる半
導体搭載用基板は、セラミック自身が高価であり、耐衝
撃性１曲げ性に劣るという問題点を有していた。そこで
、基材にセラミック基板に代わるものとして、安価なプ
ラスチック酸のプリント配線板を用いたピングリッドア
レイ型半導体搭載用基板が開発されている。However, semiconductor mounting substrates using a ceramic ink substrate as a base material have had problems in that the ceramic itself is expensive and has poor impact resistance and bendability. Therefore, as an alternative to the ceramic substrate, a pin grid array type semiconductor mounting substrate using an inexpensive printed wiring board made of plastic acid has been developed.
この半導体搭載用基板には、半導体チップ４１部と導体
回路とスルーホールが形成されており、更にこのスルー
ホールに嵌合された導体ピンが設けられている。また、
この半導体搭載用基板に搭載される半導体素子は搭載部
に実装後、ワイヤーボンデインク等により導体回路に結
線される。従って、半導体素子からの電気信号は、基板
部とスルーホールに嵌合された導体ピンにより、効率よ
く外部・入出力されなければならない。更に、この導体
ピンは、外部接続端子として、マザーボートに形成され
た実装用スルーホールに固定されることにより、半導体
搭載用基板とマザーボードに形成された回路とを電気的
に接続する。This semiconductor mounting board has a semiconductor chip 41 portion, a conductor circuit, and a through hole formed therein, and is further provided with a conductor pin fitted into the through hole. Also,
After the semiconductor element mounted on this semiconductor mounting substrate is mounted on the mounting portion, it is connected to a conductive circuit using wire bonding ink or the like. Therefore, electrical signals from the semiconductor element must be efficiently input/output to/from the outside through the substrate portion and the conductor pins fitted into the through holes. Further, the conductor pins are fixed as external connection terminals to mounting through holes formed on the motherboard, thereby electrically connecting the semiconductor mounting board and the circuit formed on the motherboard.
一方、導体ピンは外部出力端子として実装時の仏頼性か
高くなければならないために、半導体搭載用基板との十
分な接合強度を必要とし、かつ半導体ｐ５佐川基板のス
ルーホールと導体ピンの嵌合部は、電気的にも確実に接
合されていなければならない。従って、導体ピンと基板
のスルーホールの嵌合部とをハンダ付けする場合があり
、この場合スルーポール内の嵌合部には、ハンダか充填
されて導体ピンと嵌合部とか完全に一体化されていなけ
ればならない。On the other hand, since the conductor pin must be highly reliable when mounted as an external output terminal, it requires sufficient bonding strength with the semiconductor mounting board, and the conductor pin must fit into the through hole of the semiconductor P5 Sagawa board. The joint must also be electrically connected reliably. Therefore, there are cases where the conductor pin and the mating part of the through-hole of the board are soldered. In this case, the mating part in the through-pole is filled with solder and the conductor pin and the mating part are completely integrated. There must be.
このような必要−ヒ、従来第８１′Ａ及び第９図に示す
ように、嵌合部（５１）及び嵌合部（５１）に近接した
部分に、その径かスルーホール（６１）の内径より大き
い略円形の鍔（５２）を有した導体ピン（５０）を、プ
リント配線板（６０）に形成したスルーホール（６１）
に嵌合し、導体ピン（５０）側より溶融ハンダに浸漬す
ることにより接合した半導体搭載用基板（８０）が知ら
れている。In order to meet this need, conventionally, as shown in FIG. 81'A and FIG. A through hole (61) in which a conductor pin (50) with a larger approximately circular flange (52) is formed in a printed wiring board (60).
There is known a semiconductor mounting board (80) which is fitted into the conductor pin (50) and bonded by being immersed in molten solder from the conductor pin (50) side.
（発明が解決しようとする問題点）
しかしながら、各導体ピン（５０）の嵌合部（５１）に
近接した部分に、その径がスルーホール（６］）の内径
より大きい略円形の鍔（５２）を設け、その導体ピン（
５０）をプリント配線板（６０）に形成したスルーホー
ル（６１）に嵌合するようにした従来の半導体搭載用基
板（８０）には、次のような問題点かあった。(Problem to be Solved by the Invention) However, in a portion of each conductor pin (50) close to the fitting portion (51), there is a substantially circular collar (52) whose diameter is larger than the inner diameter of the through hole (6). ), and its conductor pin (
The conventional semiconductor mounting board (80) in which the semiconductor mounting board (50) is fitted into a through hole (61) formed in a printed wiring board (60) has the following problems.
導体ピン（５０）は、嵌合部（５１）に近接した部分に
設けられる略円形の鍔（５２）により、プリント配線板
（５０）に確実に支持されており、また外部接続端子と
しての長さを規定している。しかし、この略円形の鍔（
５２）によって、プリント配線板（６０）に形成されて
いるスルーホール（６Ｉ）の導体ピン（５０）側が、密
閉に近い状態になってしまう。従って、導体ピン（５０
）とスルーホール（６１）を電気的及び機械的に強固な
接合とするために、導体ピン（５０）側より半導体搭載
用基板（８０）を溶融ハンダに浸漬した場合、ハンダ浸
漬前に導体ピン側に塗布したフラックス中の溶剤がガス
化してガス溜りを生じ、このガス溜りによってハンダ（
７０）がスルーホール（６１）内に容易に浸透すること
ができないため、導体ピン（５０）とスルーホール（６
１）との電気的接合は完全なものとはならず、また接合
強度の向上も認められないのである。The conductor pin (50) is reliably supported by the printed wiring board (50) by a substantially circular collar (52) provided in the vicinity of the fitting part (51), and also has a long length as an external connection terminal. It stipulates that However, this almost circular tsuba (
52), the conductor pin (50) side of the through hole (6I) formed in the printed wiring board (60) becomes almost sealed. Therefore, the conductor pin (50
) and the through hole (61), when the semiconductor mounting board (80) is immersed in molten solder from the conductor pin (50) side, the conductor pin The solvent in the flux applied to the side gasifies and creates a gas pool, which causes the solder (
70) cannot easily penetrate into the through hole (61), so the conductor pin (50) and the through hole (6
The electrical connection with 1) is not perfect, and no improvement in bonding strength is observed.
導体ピン（５０）とスルーホール（６１）の電気的接合
及び機械的接合を確実なものとするためには、半導体搭
載用基板（８０）の溶融ハンダ浸漬時Ｈｉを長くしなけ
ればならなくなり、この際の熱により半導体搭載用基板
（８０）かダメージを受けてしまうばかりか、溶融ハン
ダ浸漬時間を長くしても、導体ピン（５０）とスルーホ
ール（６１）の接合か確実なものとならない場合がある
という欠点を有していた。In order to ensure the electrical connection and mechanical connection between the conductor pin (50) and the through hole (61), it is necessary to increase Hi when the semiconductor mounting board (80) is immersed in molten solder. Not only will the semiconductor mounting board (80) be damaged by the heat at this time, but even if the molten solder immersion time is prolonged, the connection between the conductor pin (50) and the through hole (61) will not be reliable. It has the disadvantage that there are cases.
本発明は以上のような実状に鑑みてなされたもので、そ
の目的とするところは、導体ピン（５０）とこれが嵌合
されるスルーホール（６１）との電気的接合及び機械的
接合が確実になされた、ピングリッド′アレイ型半導体
搭載用基板のように導体ピンを有する基板を提供するこ
とにある。The present invention has been made in view of the above-mentioned circumstances, and its purpose is to ensure electrical and mechanical connection between the conductor pin (50) and the through hole (61) into which it is fitted. An object of the present invention is to provide a substrate having conductor pins, such as a pin grid array type semiconductor mounting substrate.
（問題点を解決するための手段）
以上の問題点を解決するために１本発明が採った手段は
。(Means for solving the problems) One of the measures taken by the present invention to solve the above problems is as follows.
導体ピン（１０）を有するプリント配線板に形成された
スルーホール（２１）に導体ピン（１０）か嵌合された
半導体搭載用基板において、
基板と鍔（１２）の間に一定の隙間を設けるため、前記
導体ピン（１０）の鍔（１２）の基板と接触する側に凸
部（３１）を形成させる。この隙間により導体ピン（５
０）側より半導体搭載用基板（８０）を溶融ハンダに浸
漬した場合、フラックス中の溶剤かガス化したガスが容
易にスルーホール（２１）上部に抜けるこ−とかでき、
又ハンダ（３０）も容易にスルーホール（６１）内に充
填される。In a semiconductor mounting board in which a conductor pin (10) is fitted into a through hole (21) formed in a printed wiring board having a conductor pin (10), a certain gap is provided between the board and the collar (12). Therefore, a convex portion (31) is formed on the side of the collar (12) of the conductor pin (10) that contacts the substrate. This gap allows the conductor pin (5
When the semiconductor mounting board (80) is immersed in molten solder from the 0) side, the solvent in the flux or gasified gas can easily escape to the upper part of the through hole (21).
Further, the solder (30) is also easily filled into the through hole (61).
上記の手段を講することにより、前記導体ピン（１０）
と基板のスルーホール（２１）とをハンダ接合したこと
を特徴とする半導体＃＆載用基板（４０）である。By taking the above measures, the conductor pin (10)
This is a semiconductor #& mounting board (40) characterized by soldering the through hole (21) of the board and the through hole (21) of the board.
（発明の作用）
上記ような手段を講じた本発明に係る半導体搭載用基板
（４０）にあっては、導体ピン（１０）とスルーホール
（２１）の接合は、半導体搭載用基板（４０）を導体ピ
ン（ｌＯ）側より溶融ハンダに浸漬することにより１行
なわれる。(Function of the Invention) In the semiconductor mounting board (40) according to the present invention that takes the above-described measures, the conductor pin (10) and the through hole (21) are bonded to each other in the semiconductor mounting board (40). This is done by immersing the conductor pin (lO) side into molten solder.
この際、導体ピン（ｌＯ）の鍔（１２）の基板と接触す
る側に凸部（３１）を設けて、ノ５板と鍔（１２）との
間に一定の隙間を形成することによって、溶融ハンダ浸
漬時に発生するフラックス中の溶剤分がガス化すること
により発生するガスか前記隙間を通して基板り面に抜け
、又ハンダ（３０）もスルーホール（２１）内にフラッ
クスの残渣を残すことなく容易に浸透し、より短時間で
スルーホール（２１）内かハンダで充填される。従って
、半導体搭載用基板（４０）は、これを溶融ハンダに浸
漬する時間が短くてすんでいるので、この浸透の際の熱
によっては、当該半導体搭載用基板（４０）はダメージ
を受けていないのである。また、この半導体搭載用基板
（４０）は、そのスルーホール（２１）と導体ピン（１
０）の嵌合部（１１）間にハンダ（３０）が確実に充填
されているから、その機械的接合が確実となっているた
けでなく、スルーホール（２１）と導体ピン（Ｉｎ）と
の電気的接合も完全なものとなっている。At this time, by providing a convex portion (31) on the side of the flange (12) of the conductor pin (lO) that contacts the substrate, and forming a certain gap between the No. 5 plate and the flange (12), The gas generated by the gasification of the solvent in the flux generated during immersion in molten solder escapes to the board surface through the gap, and the solder (30) also does not leave any flux residue in the through hole (21). It penetrates easily and fills the through holes (21) with solder in a shorter time. Therefore, since the time for immersing the semiconductor mounting board (40) in the molten solder is short, the semiconductor mounting board (40) is not damaged by the heat generated during this penetration. be. This semiconductor mounting board (40) also has through holes (21) and conductor pins (1).
Since the solder (30) is reliably filled between the fitting parts (11) of 0), not only is the mechanical connection reliable, but also the connection between the through hole (21) and the conductor pin (In) is ensured. The electrical connection is also perfect.
（実施例）
以下に本発明を、図面に示した実施例に従って、詳細に
説明する。(Example) The present invention will be described in detail below according to an example shown in the drawings.
第１図には、本発明に係る半導体ｐＳａ用基板基板０）
の一実施例を示す斜視図が、第２図には、第１図のＩＩ
−ＩＩ線に沿ってみた部分拡大縦断面図が、そし・て
第３図には、第２図の部分拡大上面図が示しである。こ
の半導体搭載用基板（４０）にあっては、プリント配線
板（２０）に形成されるスルーホール（２Ｉ）に導体ピ
ン（１０）が嵌合部（１１）によって嵌合されており、
この導体ピン（１０）とスルーホール（２１）の電気的
接合は、半導体搭載用基板（４０）を導体ピン（ｌＯ）
側より溶融ハンダに浸漬することによってなされている
。FIG. 1 shows a semiconductor pSa substrate 0) according to the present invention.
FIG. 2 is a perspective view showing one embodiment of FIG.
FIG. 3 shows a partially enlarged longitudinal sectional view taken along the line -II, and FIG. 3 shows a partially enlarged top view of FIG. 2. In this semiconductor mounting board (40), a conductor pin (10) is fitted into a through hole (2I) formed in a printed wiring board (20) by a fitting part (11),
The electrical connection between the conductor pin (10) and the through hole (21) is made by connecting the semiconductor mounting board (40) to the conductor pin (lO).
This is done by dipping it into molten solder from the side.
また各導体ピン（１０）にあっては、その嵌合部（１１
）に近接した部分に、基板と鍔（１２）の間に一定の隙
間を設ける目的て凸部（３１）を有した鍔（１２）が形
成されている。従って、半導体搭載用基板（４０）を導
体ピン（１０）側より溶融ハンダに浸漬すると、前記隙
間よりハンダ（３０）か浸透し、このハンダ（３０）て
スルーホール（２１）内が充填される。このようにして
、導体ピン（１０）とスルーホール（２１）は、′電気
的に接合されているのである。また、これらの作業は非
常に短時間でなされ、ハンダ浸漬時の熱により、半導体
搭載用基板（４０）がダメージを受けず、確実にハンダ
（３０）をスルーホール（２１）内に充填させることが
できる。In addition, each conductor pin (10) has a fitting portion (11).
) is formed with a flange (12) having a convex portion (31) for the purpose of providing a certain gap between the substrate and the flange (12). Therefore, when the semiconductor mounting board (40) is immersed in molten solder from the conductor pin (10) side, the solder (30) penetrates through the gap, and the inside of the through hole (21) is filled with this solder (30). . In this way, the conductor pin (10) and the through hole (21) are electrically connected. In addition, these operations can be performed in a very short time, and the semiconductor mounting board (40) will not be damaged by the heat during solder immersion, and the solder (30) can be reliably filled into the through holes (21). Can be done.
なお、本発明に係る半導体搭載用基板（４０）の有する
導体ピン（１０）の鍔の凸部（コ１）の形状として、第
２ＩＡ及び第３図の他に、第４図及び第４図の部分拡大
上面図として第５図、或いは第６図及び第６図の部分拡
大上面図として第７図を示す。In addition to FIG. 2IA and FIG. 3, FIGS. FIG. 5 is shown as a partially enlarged top view of FIG. 5, or FIG. 7 is shown as a partially enlarged top view of FIG. 6 and FIG.
さらに基板と鍔（１２）の間に一定の隙間を設けられる
ものてあれば、」１記以外のどんな形状であつてもよい
。Further, as long as a certain gap can be provided between the substrate and the flange (12), any shape other than those described in 1 may be used.
（発明の効果）
以丑に説明したように、本発明に係る半導体搭載用基ｉ
（４０）によれば、プリント配線板に形成したスルー
ホール（２１）に、嵌合部によって嵌合され、かつ前記
嵌合部（１１）に近接した部分に鍔（１２）を有する多
数の導体ピン（１０）からなる半導体搭載用基板であっ
て。(Effects of the Invention) As explained above, the semiconductor mounting base i according to the present invention
According to (40), a large number of conductors are fitted into through holes (21) formed in a printed wiring board by means of a fitting part, and have a flange (12) in a portion close to the fitting part (11). A semiconductor mounting board consisting of pins (10).
前記導体ピン（１０）の鍔（Ｉ２）の基板と接触する側
に凸部（コ１）を形成することにより、前記導体ピン（
１０）の鍔（１２）と前記基板との間に一定の隙間を設
けられることに特徴があり、これにより凸部によって各
導体ピン（１０）かプリント配線板（２０）にしっかり
支持されることは勿論、導体ピン（１０）とスルーホー
ル（２１）を電気的に接合するために、半導体搭載用基
板（４０）を導体ピン（１０）側より溶融ハンダに浸漬
した時、容易にハンダ（３０）がスルーホール（２１）
内に浸漬し、このハンダ（３０）により短時間にスルー
ホール（２１）内に充填される。By forming a protrusion (1) on the side of the collar (I2) of the conductor pin (10) that contacts the substrate, the conductor pin (
The feature is that a certain gap is provided between the flange (12) of 10) and the board, so that it is firmly supported by each conductor pin (10) or printed wiring board (20) by the convex part. Of course, in order to electrically connect the conductor pins (10) and through holes (21), when the semiconductor mounting board (40) is immersed in molten solder from the conductor pins (10) side, the solder (30 ) is a through hole (21)
The solder (30) fills the through hole (21) in a short time.
従って、・溶融ハンダ浸漬時に、スルーホール（２１）
内に短時間でハンダ（コ０）か揚がり、半導体搭載用基
板（４０）の溶融ハンダ浸漬時の熱によるダメージら少
なく、スルーホール（２１）内にフラックスの残渣も残
らない信頼性の高い接合状態のピングリットアレイ型半
導体搭載用基板（４０）を提供できるという効果を奏す
る。Therefore, when immersing in molten solder, the through hole (21)
The solder (0) rises within a short time, there is little damage caused by heat when the semiconductor mounting board (40) is immersed in molten solder, and there is no flux residue left inside the through hole (21), resulting in highly reliable bonding. This has the advantage that it is possible to provide a pin-grit array type semiconductor mounting substrate (40) in the same state.
第１ＶＡは本発明に係る半導体搭載用基板の一実施例を
示す斜視図、第２図は第１図のｎ−Ｕ線に沿ってみた部
分拡大縦断面図、第３図は第２図の部分拡大上面図、第
４図は本発明に係る半導体搭載用基板の別の実施例を示
す部分拡大縦断面図、第５図は第４図の部分拡大」−面
図、第６図は本発明に係る半導体搭載用基板の更に別の
実施例を示す部分拡大縦断面図、第７図は第６図の部分
拡大上面図である。
また、第８図は及び第９図は従来の例を示す図であって
、第８図はその部分拡大縦断面図、第９図は第８図の部
分拡大上面図である４
符号の説明
ｌＯ・・・導体ピン、 １１・・・嵌合部、１２・・・
鍔、１３・・・鍔。
２０・・・プリント配線板、２１・・−スルーホール、
３０−・・ハンダ、３１・−・凸部、４０・・・半導
体搭載用基板。1VA is a perspective view showing one embodiment of the semiconductor mounting board according to the present invention, FIG. 2 is a partially enlarged vertical sectional view taken along line n-U of FIG. 1, and FIG. FIG. 4 is a partially enlarged vertical sectional view showing another embodiment of the semiconductor mounting board according to the present invention, FIG. 5 is a partially enlarged top view of FIG. 4, and FIG. FIG. 7 is a partially enlarged longitudinal sectional view showing still another embodiment of the semiconductor mounting board according to the invention, and FIG. 7 is a partially enlarged top view of FIG. 6. Furthermore, FIGS. 8 and 9 are views showing a conventional example, in which FIG. 8 is a partially enlarged vertical sectional view thereof, and FIG. 9 is a partially enlarged top view of FIG. 8. lO...conductor pin, 11...fitting part, 12...
Tsuba, 13...Tsuba. 20...Printed wiring board, 21...-through hole,
30--Solder, 31--Convex portion, 40--Semiconductor mounting board.
Claims (1)
よって嵌合され、かつ前記嵌合部に近接した部分に鍔を
有する多数の導体ピンからなる半導体搭載用基板であっ
て、 前記導体ピンの鍔の基板と接触する側に凸部を形成する
ことにより、前記導体ピンの鍔と前記基板との間に一定
の隙間を設け、かつこの隙間内にハンダを浸入させるこ
とにより、前記導体ピンと基板のスルーホールとをハン
ダ接合したことを特徴とする半導体搭載用基板。 ２）前記スルーホールに嵌合された導体ピンのいくつか
が、前記鍔の下部に別の鍔を有する導体ピンであること
を特徴とする特許請求の範囲第１項に記載の半導体搭載
用基板。[Scope of Claims] 1) A semiconductor mounting board consisting of a large number of conductor pins that are fitted into through-holes formed in a printed wiring board by a fitting part and have a flange in a portion close to the fitting part. By forming a convex portion on the side of the flange of the conductor pin that contacts the substrate, a certain gap is provided between the flange of the conductor pin and the substrate, and the solder is allowed to infiltrate into this gap. A board for mounting a semiconductor, characterized in that the conductor pins and the through holes of the board are soldered together. 2) The semiconductor mounting board according to claim 1, wherein some of the conductor pins fitted into the through holes are conductor pins having another flange below the flange. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61101571A JPH0719857B2 (en) | 1986-04-30 | 1986-04-30 | Semiconductor mounting board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61101571A JPH0719857B2 (en) | 1986-04-30 | 1986-04-30 | Semiconductor mounting board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62257755A true JPS62257755A (en) | 1987-11-10 |
| JPH0719857B2 JPH0719857B2 (en) | 1995-03-06 |
Family
ID=14304089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61101571A Expired - Lifetime JPH0719857B2 (en) | 1986-04-30 | 1986-04-30 | Semiconductor mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719857B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04107863U (en) * | 1991-03-02 | 1992-09-17 | 株式会社堀場製作所 | infrared detector |
| CN111541113A (en) * | 2017-04-18 | 2020-08-14 | 株式会社藤仓 | Coaxial connector |
| EP4113589A3 (en) * | 2021-06-29 | 2023-05-03 | Shinko Electric Industries Co., Ltd. | Header for semiconductor package, and semiconductor package |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48104072A (en) * | 1972-04-14 | 1973-12-26 | ||
| JPS5346558U (en) * | 1976-09-24 | 1978-04-20 | ||
| JPS5970352U (en) * | 1982-10-28 | 1984-05-12 | 京セラ株式会社 | Plug-in semiconductor package |
| JPS6095944A (en) * | 1983-10-31 | 1985-05-29 | Ibiden Co Ltd | Plug-in package and manufacture thereof |
| JPS60140374U (en) * | 1984-02-28 | 1985-09-17 | 住友電気工業株式会社 | connector terminal |
| JPS614456U (en) * | 1984-06-13 | 1986-01-11 | イビデン株式会社 | Plug-in package board |
| JPS617692A (en) * | 1984-06-21 | 1986-01-14 | イビデン株式会社 | Method of securing conductor pin and printed circuit board secured with conductor pin |
-
1986
- 1986-04-30 JP JP61101571A patent/JPH0719857B2/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS48104072A (en) * | 1972-04-14 | 1973-12-26 | ||
| JPS5346558U (en) * | 1976-09-24 | 1978-04-20 | ||
| JPS5970352U (en) * | 1982-10-28 | 1984-05-12 | 京セラ株式会社 | Plug-in semiconductor package |
| JPS6095944A (en) * | 1983-10-31 | 1985-05-29 | Ibiden Co Ltd | Plug-in package and manufacture thereof |
| JPS60140374U (en) * | 1984-02-28 | 1985-09-17 | 住友電気工業株式会社 | connector terminal |
| JPS614456U (en) * | 1984-06-13 | 1986-01-11 | イビデン株式会社 | Plug-in package board |
| JPS617692A (en) * | 1984-06-21 | 1986-01-14 | イビデン株式会社 | Method of securing conductor pin and printed circuit board secured with conductor pin |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04107863U (en) * | 1991-03-02 | 1992-09-17 | 株式会社堀場製作所 | infrared detector |
| CN111541113A (en) * | 2017-04-18 | 2020-08-14 | 株式会社藤仓 | Coaxial connector |
| EP4113589A3 (en) * | 2021-06-29 | 2023-05-03 | Shinko Electric Industries Co., Ltd. | Header for semiconductor package, and semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0719857B2 (en) | 1995-03-06 |
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