JP2012146880A - Circuit board, method of manufacturing the same, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an adhesion force between wiring layers bonded together.SOLUTION: A circuit board 1a and a circuit board 1b include a first wiring layer 2, and a second wiring layer 3 arranged in opposition to the first wiring layer 2. A resin layer 4 and an irregular layer 5 with irregularities 5a are disposed between the first wiring layer 2 and the second wiring layer 3. The irregular layer 5 is disposed on at least either or both of the opposite surfaces of the first wiring layer 2 and the second wiring layer 3. The irregular layer 5 is buried in the resin layer 4, and the resin layer 4 with the irregular layer 5 buried bonds the first wiring layer 2 and the second wiring layer 3 together.

Description

  The present invention relates to a circuit board, a manufacturing method thereof, and an electronic device.

  A build-up multilayer board is known as one type of circuit board. The build-up multilayer substrate is manufactured, for example, by repeatedly forming an insulating layer and a conductive pattern (via and wiring) on the core layer. In that case, if a defect occurs even at one place, the entire substrate becomes defective, or the process becomes longer as the number of layers increases, leading to an increase in cost. From such a viewpoint, there has been proposed a method in which a build-up layer having no defect is prepared in advance and this is bonded to the core layer with a resin.

  As for the circuit board, a wiring transfer sheet in which a wiring of a predetermined pattern is formed on the surface of the protective base material is heated and pressed on the electric insulating base material, whereby the wiring is transferred to the surface of the electric insulating base material. A method of obtaining (wiring layer) is known. Also, from the viewpoint of improving the contact area with the resin used when laminating another wiring layer, a recess is formed on the surface of the protective substrate of the wiring transfer sheet, and the surface of the electrically insulating substrate and the transferred wiring surface Also known is a method for forming a convex part complementary to the concave part on the surface of the protective substrate.

Japanese Patent No. 4413522

  For example, in a circuit board produced by bonding different wiring layers together with a resin, such as a build-up layer and a core layer, due to differences in the material of each wiring layer, generation of stress due to heat, deformation due to stress, etc. In some cases, peeling, disconnection, or the like occurred at the bonded portion. As a result, there is a risk of reducing the adhesion between the laminated wiring layers and the quality of the circuit board.

  In addition, in the method of making the surface of the wiring layer in contact with the resin uneven, it is possible to damage the internal structure (wiring, etc.) of the wiring layer when forming the unevenness, and to sufficiently improve the contact area and adhesion with the resin. There were times when it was not possible.

  According to an aspect of the present invention, the first wiring layer, the second wiring layer disposed opposite to the first wiring layer, and the first wiring layer and the second wiring layer are provided. There is provided a circuit board including a resin layer and a concavo-convex layer provided on at least one of the opposing surfaces of the first wiring layer and the second wiring layer and embedded in the resin layer.

  According to the disclosed circuit board, it is possible to improve the adhesion between the wiring layers to be bonded and to improve the quality of the circuit board.

It is a figure which shows the structural example of a circuit board. It is a figure which shows an example of the circuit board which concerns on 1st Embodiment. It is a figure which shows an example of the A section enlarged view of FIG. It is a figure which shows an example of the 1st formation process of a buildup layer. It is a figure which shows an example of the 2nd formation process of a buildup layer. It is a figure which shows an example of the 3rd formation process of a buildup layer. It is a figure which shows an example of the 4th formation process of a buildup layer. It is a figure which shows an example of the 5th formation process of a buildup layer. It is a figure which shows an example of the 6th formation process of a buildup layer. It is a figure which shows an example of the 7th formation process of a buildup layer. It is a figure which shows an example of the 8th formation process of a buildup layer. It is a figure which shows an example of the 9th formation process of a buildup layer. It is a figure which shows an example of the 1st formation process of a core layer. It is a figure which shows an example of the 2nd formation process of a core layer. It is a figure which shows an example of the 3rd formation process of a core layer. It is a figure which shows an example of the 4th formation process of a core layer. It is a figure which shows an example of the 1st process of the bonding which concerns on 1st Embodiment. It is a figure which shows an example of the 2nd process of the bonding which concerns on 1st Embodiment. It is a figure which shows an example of the 3rd process of the bonding which concerns on 1st Embodiment. It is a figure which shows an example of the 4th process of bonding which concerns on 1st Embodiment. It is a figure which shows an example of the 5th process of bonding which concerns on 1st Embodiment. It is a figure which shows an example of the 6th process of bonding which concerns on 1st Embodiment. It is a figure (the 1) which shows an example of a plasma processing. It is a figure (the 2) which shows an example of a plasma processing. It is a figure which shows an example of the circuit board which concerns on 2nd Embodiment. It is a figure which shows an example of the 1st formation process of a metal mold | die. It is a figure which shows an example of the 2nd formation process of a metal mold | die. It is a figure which shows an example of the 1st process of the bonding which concerns on 2nd Embodiment. It is a figure which shows an example of the 2nd process of the bonding which concerns on 2nd Embodiment. It is a figure which shows an example of the 3rd process of the bonding which concerns on 2nd Embodiment. It is a figure which shows an example of the 4th process of the bonding which concerns on 2nd Embodiment. It is a figure which shows an example of the 5th process of bonding which concerns on 2nd Embodiment. It is a figure which shows an example of the 6th process of bonding which concerns on 2nd Embodiment. It is a figure which shows an example of the 7th process of the bonding which concerns on 2nd Embodiment. It is a figure which shows an example of the 8th process of bonding which concerns on 2nd Embodiment. It is a figure which shows an example of the circuit board which concerns on 3rd Embodiment. It is FIG. (1) which shows an example of the electronic device which concerns on 4th Embodiment. It is FIG. (2) which shows an example of the electronic device which concerns on 4th Embodiment.

FIG. 1 is a diagram illustrating a configuration example of a circuit board.
The circuit boards 1a and 1b shown in FIGS. 1A and 1B have a structure in which a first wiring layer 2 and a second wiring layer 3 are bonded together through a resin layer 4 and an uneven layer 5. .

  The first wiring layer 2 includes an insulating part (insulating layer) and a conductive part (wiring, via, etc.). Similarly, the second wiring layer 3 includes an insulating portion and a conductive portion. For example, each of the first wiring layer 2 and the second wiring layer 3 can be a buildup layer in which an insulating layer, wiring, and the like are repeatedly formed, and one of them is such a buildup layer and the other is a core. It can also be a core layer in which wiring or the like is formed on the substrate.

  Here, the concavo-convex layer 5 is formed on either one of the opposing surfaces of the first wiring layer 2 and the second wiring layer 3, here as an example, as shown in FIG. 2 on the surface facing the second wiring layer 3. Moreover, the uneven | corrugated layer 5 can also be each arrange | positioned on both surfaces of the opposing surface of the 1st wiring layer 2 and the 2nd wiring layer 3, as shown in FIG.1 (B). The uneven layer 5 is formed so that the unevenness 5a is provided on the surface on the resin layer 4 side. In addition, the detail of the unevenness | corrugation 5a of the uneven | corrugated layer 5 is mentioned later. The resin layer 4 is provided so as to bury the unevenness 5 a of the uneven layer 5.

  Thus, in the circuit boards 1a and 1b, the uneven layer 5 is provided on either or both of the first wiring layer 2 and the second wiring layer 3. And the resin layer 4 is provided so that the uneven | corrugated layer 5 may be embedded, and the 1st wiring layer 2 and the 2nd wiring layer 3 are bonded together. This increases the contact area between the resin layer 4 and the concavo-convex layer 5 and improves the adhesion between the first wiring layer 2 and the second wiring layer 3 bonded together via the resin layer 4 and the concavo-convex layer 5. ing.

Hereinafter, the circuit board will be described in more detail.
First, the first embodiment will be described.
FIG. 2 is a diagram illustrating an example of a circuit board according to the first embodiment. FIG. 2 schematically shows a cross-section of the main part of an example of the circuit board according to the first embodiment.

  A circuit board 100 according to the first embodiment shown in FIG. 2 includes a core layer 10 as a wiring layer, and a first buildup layer 20 and a second buildup layer 20 provided on the front side and the back side of the core layer 10, respectively. It has a buildup layer 30. An uneven layer 40 and a resin layer 50 are provided between the core layer 10 and the first buildup layer 20. Similarly, an uneven layer 40 and a resin layer 50 are provided between the core layer 10 and the second buildup layer 30. The first buildup layer 20 and the second buildup layer 30 are electrically connected to the core layer 10 using a joining member 60 such as solder.

  The first buildup layer 20 has an insulating layer 21 and a conductive pattern 22. For the insulating layer 21, for example, a resin or a resin containing glass fiber or the like is used. For the conductive pattern 22, for example, a conductive material such as copper (Cu) is used. The conductive pattern 22 includes a wiring 22a, a via 22b, an electrode 22c on the core layer 10 side, and an electrode 22d for external connection. A protective film 23 such as a solder resist is provided on the surface side (upper layer side) of the first buildup layer 20 opposite to the core layer 10 so that the electrode 22d is exposed. In addition, a plated layer 24 having a two-layer structure is provided on the surfaces of the electrodes 22c and 22d as an example. The first buildup layer 20 has a multilayered structure by alternately forming the insulating layers 21 and the conductive patterns 22.

  Here, the second buildup layer 30 has the same structure as the first buildup layer 20. That is, the second buildup layer 30 has an insulating layer 31 using a resin, and a conductive pattern 32 including a wiring 32a, a via 32b, and electrodes 32c and 32d. A protective film 33 such as a solder resist is provided on the surface side (upper layer side, electrode 32d side) of the second buildup layer 20, and a plated layer 34 having a two-layer structure as an example on the surfaces of the electrodes 32c and 32d. Is provided.

  In the first buildup layer 20, a predetermined pattern of wiring can be provided on the uppermost layer (on the side opposite to the core layer 10 side), and a part thereof can be used as the electrode 22d. In the second buildup layer 30, a predetermined pattern of wiring can be provided on the uppermost layer (opposite side of the core layer 10), and a part of the wiring can be used as the electrode 32d.

  The core layer 10 includes a core substrate 11 and a conductive pattern 12. As the core substrate 11, for example, a glass epoxy substrate, a metal core substrate in which a metal plate such as 42 alloy is coated with an insulating layer, a substrate using carbon fiber reinforced plastic (CFRP), or a ceramic substrate is used. . The core substrate 11 is provided with a through hole 11a penetrating between the front and back surfaces. For the conductive pattern 12, for example, a conductive material such as copper is used. The conductive pattern 12 includes electrodes 12 a and 12 b provided on the first buildup layer 20 side (front surface side) and the second buildup layer 30 side (back surface side) of the core substrate 11, respectively. As an example, a plating layer 13 having a two-layer structure is provided on the surfaces of the electrodes 12a and 12b. Furthermore, the conductive pattern 12 includes a via 12 c provided in the through hole 11 a of the core substrate 11. Here, the via 12c is provided on the side wall of the through hole 11a, and a resin 14 is provided in the center of the through hole 11a on the inner side of the via 12c.

  In the core layer 10, a predetermined pattern of wiring may be provided on the front and back surfaces of the core substrate 11 in addition to the electrodes 12 a and 12 b. In the core layer 10, a predetermined pattern of wiring can be provided on the front and back surfaces of the core substrate 11, and a part of them can be used as the electrodes 12 a and 12 b.

  The concavo-convex layer 40 has an adhesive layer 41 and a plurality of fibers 42 bonded and fixed to the adhesive layer 41. The adhesive layer 41 is formed on the insulating layer 21 on the lowermost layer (core layer 10 side) of the first buildup layer 20, on the insulating layer 31 on the lowermost layer (core layer 10 side) of the second buildup layer 30, and the core substrate. 11 is provided so as to avoid the arrangement area of the electrodes 22c, 32c, 12a, 12b. A plurality of fibers 42 are bonded to such an adhesive layer 41 so as to stand, for example.

  Depending on the materials used for the insulating layers 21 and 31 and the core substrate 11, an adhesive having good adhesion to these materials is used for the adhesive layer 41. Further, an adhesive having heat resistance against heat applied when the circuit board 100 is formed or when components are mounted on the circuit board 100 is used for the adhesive layer 41. For the fiber 42, a material having such heat resistance against applied heat is used.

  As the fiber 42, for example, a polyamide-based synthetic fiber such as nylon (registered trademark) or aramid, a fiber such as polyethylene terephthalate (PET), polypropylene (PP), polyethylene (PE), or acrylic is used. As the plurality of fibers 42 bonded to the adhesive layer 41, one type of fiber can be used, or a plurality of types of fibers can be mixed and used. For example, fibers having a diameter of 10 μm to 15 μm can be used as the fiber 42. Further, for example, the fibers 42 extending from the adhesive layer 41 are opposed to the fibers 42 based on the distance between the first buildup layer 20 and the core layer 10 and the distance between the second buildup layer 30 and the core layer 10. A length that does not reach the wiring layer can be used. For example, fibers 42 having a length of 80 μm to 100 μm can be used.

Such an adhesive layer 41 and the plurality of fibers 42 function as the unevenness of the uneven layer 40. Here, FIG. 3 shows an example of an enlarged view of part A in FIG.
For example, in the case of the concavo-convex layer 40 disposed on the insulating layer 21 of the first buildup layer 20, the fibers 42 adhered to the adhesive layer 41 stand to extend toward the facing core layer 10 side. Each of these fibers 42 stands as a convex portion in the uneven layer 40, and a region between the adjacent fibers 42 functions as a concave portion in the uneven layer 40. That is, the concavo-convex layer 40 has a convex portion having a width corresponding to the diameter of the fiber 42 bonded to the adhesive layer 41 and a height corresponding to the length of the portion extending from the adhesive layer 41. A recess having a width corresponding to the interval between adjacent fibers 42 is provided.

  Similarly, in the case of the concavo-convex layer 40 disposed on the core substrate 11 of the core layer 10 facing the first buildup layer 20, the convex portions and the concave portions are formed by the plurality of fibers 42 standing on the adhesive layer 41. Yes.

  A resin layer 50 is provided between the first buildup layer 20 and the core layer 10 provided with such an uneven layer 40. In the concavo-convex layer 40, the concavo-convex formed by the adhesive layer 41 and the fibers 42 are embedded by the resin layer 50. Therefore, compared with the case where the resin layer 50 is provided between the first buildup layer 20 and the core layer 10 in which the uneven layer 40 is not provided, the resin layer 50 is on the first buildup layer 20 side and the core layer 10. The area that comes into contact with the side increases, and the force to bring them into close contact with each other increases. That is, the anchor effect by the concavo-convex layer 40 is exhibited, and the adhesion between the first buildup layer 20 and the core layer 10 can be improved.

  Similarly, when the resin layer 50 is provided between the second buildup layer 30 provided with the uneven layer 40 and the core layer 10 as shown in FIG. The adhesion between the second buildup layer 30 and the core layer 10 can be improved.

  The uneven layer 40 (in the example of FIG. 3, the uneven layer 40 provided in the first buildup layer 20 and the uneven layer 40 provided in the core layer 10) provided in different wiring layers, for example, in regions facing each other. Provided. In this case, if the lengths of the fibers 42 of the opposing concavo-convex layer 40 are adjusted in advance, as shown in FIG. 2 and FIG. Thus, by making the front-end | tip part of the fiber 42 of an opposing area | region complicated, the resin layer 50 is provided so that the complicated fiber 42 may be embedded, and it becomes possible to implement | achieve high adhesiveness.

  By the way, as one method for increasing the contact area between the wiring layer and the resin layer, there is a method of forming irregularities by roughening the surface of the wiring layer itself. As a method for roughening the surface of the wiring layer, a method of etching the surface of the wiring layer, a method of forming the surface of the wiring layer using a predetermined mold, and the like can be considered. However, when the surface of the wiring layer itself is roughened, the size of the unevenness that can be formed may be limited depending on the internal structure of the wiring layer. For example, by roughening the surface of the wiring layer, irregularities are formed at such a depth that the underlying wiring close to the surface is not exposed or damaged.

  On the other hand, the uneven layer 40 as described above is provided on wiring layers such as the first buildup layer 20, the second buildup layer 30, and the core layer 10. Since the uneven layer 40 is provided on the wiring layer in this way, the size of the unevenness is not limited by the internal structure of the wiring layer, and the internal structure of the wiring layer is not damaged because the uneven layer 40 is provided. In the concavo-convex layer 40, by adjusting the thickness of the adhesive layer 41, the diameter and length of the fibers 42, the concavo-convex corresponding to those sizes can be formed. In the uneven layer 40, for example, deep unevenness and unevenness with a narrow interval (period) can be formed as compared with the case where the surface of the wiring layer is roughened.

  2 and 3 show a state in which all the fibers 42 of the uneven layer 40 stand upright from the adhesive layer 41. However, the fibers 42 do not necessarily need to be all upright, and may tilt or fall. Some of them may be included.

  2 and 3 show the state in which the fibers 42 stand at regular intervals. However, the fibers 42 do not necessarily have to stand at regular intervals, and stand at different intervals. A plurality of fibers 42 may be included.

  Here, the case where the first buildup layer 20 and the second buildup layer 30 having the same structure are used has been described as an example. In addition, a build-up layer having a different structure may be bonded to the front and back sides of the core layer 10. In addition to the core layer 10 having the above-described structure, the structure can be changed according to the structure of the build-up layer to be bonded.

Next, an example of a circuit board forming method according to the first embodiment will be described.
First, an example of the formation method of a buildup layer is demonstrated in order with reference to FIGS. Here, a method of forming a buildup layer on the front and back sides of one substrate (support) and dividing the two buildup layers from the substrate will be described.

FIG. 4 is a diagram illustrating an example of a first formation process of the buildup layer.
First, as shown in FIG. 4A, a support 200 having a copper layer 202 provided on the front and back surfaces of a substrate 201 is prepared. For the support 200, for example, a double-sided copper-clad plate is used. As the support 200, for example, one having a planar size of 340 mm × 510 mm and a thickness of 1.0 mm is used.

  A resin 203 is laminated on the copper layers 202 on the front and back surfaces of the support 200 as shown in FIG. For the resin 203 to be laminated, for example, a semi-cured (B stage) resin sheet is used.

Next, as shown in FIGS. 4B and 4C, a copper foil 204 and a three-layer foil 205 are sequentially laminated on the resin 203 provided on the front and back surfaces of the support 200.
The copper foil 204 having a plane size smaller than the plane size of the support 200 is used, and such a copper foil 204 is laminated on the central portion of the substrate after the resin 203 is laminated. For example, a copper foil 204 having a planar size of 330 mm × 500 mm is laminated above the center part of the support 200 on which the resin 203 is laminated so that the resin 203 is exposed to a width of about 10 mm on the outer peripheral part.

  As the three-layer foil 205, for example, a layer in which three layers of a copper layer 205a, a nickel layer 205b, and a copper layer 205c are sequentially stacked is used. For the three-layer foil 205, for example, the same plane size as that of the support 200 is 340 mm × 510 mm.

  Such a three-layer foil 205 is laminated on the resin 203 and the copper foil 204, and a structure as shown in FIG. 4C is obtained by applying pressure and heating. For example, a copper foil 204 and a three-layer foil 205 are laminated on the resin 203 and heat-treated at 180 ° C. while being pressurized at 0.5 MPa in a vacuum press.

FIG. 5 is a diagram illustrating an example of a second formation process of the buildup layer.
After the step of FIG. 4 (C), as shown in FIG. 5 (A), a resist is laminated on each of the three-layer foils 205 on the front and back surfaces, and exposure and development are performed, and electrodes (electrical connection with the core layer) The resist pattern 206 is formed so that the resist remains in the region where the electrode is to be formed. For example, a dry film resist is used as the resist for forming the resist pattern 206.

  After the resist pattern 206 is formed, the copper layer 205c thereon is etched so that the nickel layer 205b of the three-layer foil 205 is exposed using the resist pattern 206 as a mask. Etching of the copper layer 205c is performed by wet etching, for example. After etching, the resist pattern 206 is peeled off to obtain a state as shown in FIG. The copper layer 205c remaining after etching serves as an electrode for electrical connection with the core layer in each build-up layer formed on the front and back surfaces of the support 200.

  After the etching of the copper layer 205c, as shown in FIG. 5C, a resin 207 is laminated so as to cover the copper layer 205c and the nickel layer 205b on the front and back surfaces. For example, an epoxy sheet material having a thickness of 50 μm is pressure-bonded at 130 ° C. for 2 minutes using a vacuum laminator, and then heated at 180 ° C. for 30 minutes to laminate the resin 207 on the front and back surfaces. The resin 207 becomes a first insulating layer (first insulating layer) in each build-up layer formed on the front and back sides of the support 200.

FIG. 6 is a diagram illustrating an example of a third formation process of the buildup layer.
After the formation of the resin 207 (first insulating layer), as shown in FIG. 6A, via holes 208 reaching the copper layers 205c (electrodes) on the front and back sides are formed. The via hole 208 is formed by laser drilling using a carbon dioxide laser or the like, for example. The via hole 208 is formed with a diameter of 60 μm, for example.

  After the via hole 208 is formed, a desmear process is performed, and then a seed layer 209 for electrolytic plating described later is formed on the front and back surfaces as shown in FIG. 6B. For example, a copper seed layer 209 having a thickness of 0.5 μm is formed by electroless copper plating.

FIG. 7 is a diagram illustrating an example of a fourth formation process of the buildup layer.
After the seed layer 209 is formed, resist is laminated on the front and back surfaces, exposed, and developed to form a resist pattern 210 having an opening 210a in a region where a wiring is to be formed, as shown in FIG. For example, a dry film resist is used as the resist at this time.

After the formation of the resist pattern 210, electrolytic plating is performed using the seed layer 209 to form a copper layer 211 in the opening 210a as shown in FIG.
FIG. 8 is a diagram illustrating an example of a fifth formation process of the buildup layer.

  After the formation of the copper layer 211, the resist pattern 210 shown in FIG. 7 is peeled off, and the seed layer 209 under the resist pattern 210 is removed by etching. Thereafter, heat treatment is performed at 180 ° C. for 60 minutes. Thus, as shown in FIG. 8A, a wiring 211a and a via 211b connected to the copper layer 205c to be an electrode are formed. The wirings 211a and vias 211b are wirings and vias connected to electrodes (copper layer 205c) in each buildup layer formed on the front and back surfaces of the support 200.

  After the formation of the wiring 211a and the via 211b, a predetermined pretreatment is performed on the surface of the wiring 211a to form a resin 207 in the same manner as in FIG. 5C, and in the via hole 208 in the same manner as in FIG. Form. Thereby, a state as shown in FIG. 8B is obtained. From this state, the upper layer wiring 211a and the via 211b are formed by performing the processing of FIG. 6B to FIG. 8A. Thereafter, the same processing is repeated according to the number of build-up layers to be formed, and wirings 211a and vias 211b corresponding to the number of layers are formed.

FIG. 9 is a diagram illustrating an example of a sixth build-up layer forming step.
After forming the predetermined number of wirings 211a and vias 211b, a protective film 212 such as a solder resist is formed on the front and back surfaces. The protective film 212 is formed so that a part of the uppermost layer wiring 211a is exposed. A part of the wiring 211a exposed from the protective film 212 becomes an electrode (an electrode for external connection of a buildup layer to be formed).

  After the formation of the protective film 212, as shown in FIG. 9, cutting is performed at a predetermined width from the outer peripheral end. For example, as shown by a dotted line in FIG. 9, cutting is performed at a position of a width of about 10 mm from the outer peripheral edge or a position slightly larger than that so that the copper foil 204 appears on the cut surface.

FIG. 10 is a diagram illustrating an example of the seventh formation process of the buildup layer.
After cutting as shown in FIG. 9, the structure 220 after the cutting is divided between the copper foil 204 and the three-layer foil 205 as shown in FIG. As a result, the structure 220 after being cut is divided into a structure part 220a in which the resin 203 and the copper foil 204 remain on the front and back sides of the support 200, and two structure parts 220b laminated on the three-layer foil 205. . The structure part 220b divided from the structure part 220a is used for the build-up layer.

FIG. 11 is a diagram illustrating an example of the eighth formation process of the buildup layer.
For one of the divided structure portions 220b, first, as shown in FIG. 11A, a protective film 213 is attached to the protective film 212 side (surface side). Then, as shown in FIG. 11B, the copper layer 205a of the three-layer foil 205 exposed on the three-layer foil 205 side (rear surface side) is removed by etching to expose the nickel layer 205b. . After that, as shown in FIG. 11C, the nickel layer 205b is removed by etching to obtain a state in which the copper layer 205c of the electrode and the resin 207 of the first insulating layer are exposed on the back surface side.

FIG. 12 is a diagram illustrating an example of a ninth formation process of the buildup layer.
After the removal up to the removal of the nickel layer 205b, the protective film 213 is peeled off as shown in FIG. Then, as shown in FIG. 12B, a part of the uppermost layer wiring 211a exposed from the protective film 212 on the front surface side and serving as an electrode, on the copper layer 205c exposed to the back surface side and serving as an electrode, A nickel (Ni) layer 214a and a gold (Au) layer 214b are sequentially plated by electroless plating. For example, a nickel layer 214a having a thickness of 5 μm and a gold layer having a thickness of 0.1 μm are sequentially plated. Thereby, the plating layer 214 is formed.

Similarly, the processing shown in FIGS. 11 and 12 can be performed on the other structural portion 220b divided from the structural portion 220a as shown in FIG.
Through the above steps, two build-up layers are obtained. Here, the case where the same structure is formed on the front and back sides of the support 200 and two buildup layers having the same structure are formed has been described as an example. In addition, according to the above example, it is also possible to form separate structures on the front and back surfaces of the support 200 to form two types of buildup layers.

The first buildup layer 20 and the second buildup layer 30 of the circuit board 100 shown in FIG. 2 can be formed according to the examples shown in FIGS.
Then, an example of the formation method of a core layer is demonstrated in order with reference to FIGS.

FIG. 13 is a diagram illustrating an example of the first formation process of the core layer.
First, as shown in FIG. 13A, a support 300 having a copper layer 302 provided on the front and back surfaces of a core substrate 301 is prepared. For the support 300, for example, a double-sided copper-clad plate is used. For example, a support having a plane size of 340 mm × 510 mm and a thickness of 1.0 mm is used as the support 300.

  As shown in FIG. 13B, a through-hole 303 is formed in such a support 300 using a drill or the like. The through hole 303 corresponds to the electrodes 22c and 32c (corresponding to the copper layer 205c of the buildup layer formed according to the example of FIGS. 4 to 12) of the first buildup layer 20 and the second buildup layer 30 to be bonded together. In position, form.

  After the formation of the through-hole 303, a copper seed layer 304 is formed by electroless plating as shown in FIG. 13C, and the electrolytic plating using the seed layer 304 is performed as shown in FIG. 13D. Thus, the copper layer 305 is formed. Here, the copper layer 305 is formed on the seed layer 304 so that a hollow portion penetrating between the front and back surfaces remains in the center of the through hole 303. Hereinafter, the copper layer 302, the seed layer 304, and the copper layer 305 are referred to as a copper layer 305a.

FIG. 14 is a diagram illustrating an example of the second formation process of the core layer.
After the formation up to the copper layer 305a, the resin 306 is filled in the hollow portion remaining in the center of the through hole 303 as shown in FIG. After the resin 306 is formed, a copper layer 307 is formed on the front and back surfaces as shown in FIG.

FIG. 15 is a diagram illustrating an example of the third formation step of the core layer.
After the formation of the copper layer 307, as shown in FIG. 15A, a resist is laminated on the front and back surfaces, and exposure and development are performed to form an electrode (electrode for electrical connection with the buildup layer). A resist pattern 308 is formed so that the resist remains on the substrate. For example, a dry film resist is used as the resist for forming the resist pattern 308.

After the resist pattern 308 is formed, the copper layers 307 and 305a are etched using the resist pattern 308 as a mask to expose the core substrate 301, as shown in FIG.
FIG. 16 is a diagram illustrating an example of a fourth core layer forming step.

After the etching of the copper layers 307 and 305a using the resist pattern 308 as a mask, the resist pattern 308 is peeled off as shown in FIG.
Then, as shown in FIG. 16B, a nickel layer 309a and a gold layer 309b are sequentially plated on the surface of the electrode, that is, the copper layer 305a by electroless plating. Thereby, the plating layer 309 is formed.

The core layer can be formed by the above steps. The core layer 10 of the circuit board 100 shown in FIG. 2 can be formed according to the example shown in FIGS.
Subsequently, an example of a method of bonding the core layer and the buildup layer with the uneven layer interposed therebetween will be described in order with reference to FIGS. Here, description will be made by taking as an example the bonding of the core layer 10 of FIG. 2 to the first buildup layer 20 and the second buildup layer 30. The uneven layer 40 according to the first embodiment can be formed in the process of bonding the core layer 10, the first buildup layer 20, and the second buildup layer 30 together.

FIG. 17 is a diagram illustrating an example of a first step of bonding according to the first embodiment.
First, the uneven layer 40 is formed on each of the core layer 10 to be bonded and the first buildup layer 20, for example.

  When forming the concavo-convex layer 40, as shown in FIG. 17A, the adhesive layer 41 is formed on the insulating layer 21 of the first buildup layer 20 excluding the formation region of the electrode 22c. In addition, as shown in FIG. 17B, the adhesive layer 41 is also formed on the core substrate 11 of the core layer 10 excluding the formation region of the electrode 12a. The adhesive layer 41 formed on the core layer 10 and the first buildup layer 20 can be formed using, for example, a screen printing method.

FIG. 18 is a diagram illustrating an example of a second step of bonding according to the first embodiment.
After forming the adhesive layer 41, as shown in FIGS. 18A and 18B, fibers 42 having a predetermined diameter and length are adhered to the adhesive layer 41 on the insulating layer 21 and the core substrate 11. For example, an aramid fiber having a diameter of 10 μm to 15 μm and a length of 80 μm to 100 μm is bonded as the fiber 42 to the adhesive layer 41 formed on the insulating layer 21 and the core substrate 11. The fibers 42 can be disposed on the adhesive layer 41 using, for example, an electrostatic coating method. That is, the core layer 10 and the first buildup layer 20 on which the adhesive layer 41 is formed, and the fibers 42 are charged to predetermined charges, respectively, and the fibers 42 are dispersed and attached on the adhesive layer 41 by electrostatic force. After the fibers 42 are attached, heat treatment for curing the adhesive layer 41 is performed. For example, the adhesive layer 41 to which the fibers 42 are attached is heat-treated at 150 ° C. and cured, and the fibers 42 are bonded onto the adhesive layer 41.

In this way, the uneven layer 40 is formed on the surface of the core layer 10 facing the first buildup layer 20 and on the surface of the first buildup layer 20 facing the core layer 10.
FIG. 19 is a diagram illustrating an example of a third step of bonding according to the first embodiment.

  Also on the surface of the core layer 10 on which the second buildup layer 30 is bonded and on the surface of the second buildup layer 30 on which the core layer 10 is bonded, as shown in FIGS. 17 and 18. As shown in FIGS. 19A and 19B, the concavo-convex layer 40 is formed. That is, the concavo-convex layer 40 is formed on the core substrate 11 excluding the formation region of the electrode 12b of the core layer 10, and the insulating layer 31 of the second buildup layer 30 excluding the formation region of the electrode 32c. The uneven layer 40 is formed.

FIG. 20 is a diagram illustrating an example of a fourth step of bonding according to the first embodiment.
After the uneven layer 40 is formed on the core layer 10 and the first buildup layer 20 and the second buildup layer 30, the first buildup layer 20 of the first buildup layer 20 is formed as shown in FIGS. The joining member 60 is formed on the electrode 22 c and on the electrode 32 c of the second buildup layer 30. For example, a tin (Sn) -bismuth (Bi) solder paste is formed as the joining member 60. The solder paste can be formed using a screen printing method.

FIG. 21 is a diagram illustrating an example of a fifth process of bonding according to the first embodiment.
As described above, the bonding member 60 is formed on the first buildup layer 20 and the second buildup layer 30, while the regions excluding the electrodes 12 a and 12 b, that is, the uneven layer 40 is formed on the front and back surfaces of the core layer 10. A resin layer 50 is formed in the region. For the resin layer 50, for example, an uncured resin film in which an opening is provided in a region excluding the electrodes 12a and 12b of the core layer 10 is used. In this step, such a resin film is temporarily attached to the core layer 10.

FIG. 22 is a diagram illustrating an example of a sixth step of bonding according to the first embodiment.
Next, as shown in FIG. 22, the first buildup layer 20 and the second buildup layer 30 on which the bonding member 60 is formed are formed on the front and back sides of the core layer 10 on which the resin layer 50 is formed, and the uneven layer 40 is formed on each other. The formed surfaces are opposed to each other and stacked. Then, for example, using a positioning pin or the like, the core layer 10, the first buildup layer 20 and the second buildup layer 30 are set in a mold while maintaining their laminated state, and heated while being pressed. . For example, in a vacuum press machine, heat treatment is performed at 180 ° C. while pressurizing at 1 MPa.

  During the heating and pressurizing process, the joining member 60 is melted and solidified, and the electrodes 12a and 22c and the electrodes 12b and 32c are electrically connected. Further, in the process of heating and pressing, the resin layer 50 is solidified by spreading over the surface of the fibers 42 of the uneven layer 40 and between the fibers 42 and 42, and the core layer 10 and the first buildup layer 20, and The core layer 10 and the second buildup layer 30 are bonded to each other.

Thereby, the circuit board 100 as shown in FIG. 2 can be obtained.
In addition, after performing such pressurization and heating, protective films 23 and 33 having openings at the positions of the electrodes 22d and 32d are formed, and a nickel layer and a gold layer are formed on the electrodes 22d and 32d by electroless plating. The layers may be sequentially plated to form plated layers 24 and 34.

  Further, before forming the adhesive layer 41 on the core substrate 11 of the core layer 10 and on the insulating layer 21 of the first buildup layer 20 (FIG. 17), and on the insulating layer 31 of the second buildup layer 30 Prior to the formation of the adhesive layer 41 (FIG. 19), plasma treatment may be performed. An example of the plasma treatment is shown in FIG. For example, as shown in FIGS. 23A, 23B, and 23C, oxygen plasma treatment (shown by thick arrows) is performed on the surfaces of the insulating layer 21, the core substrate 11, and the insulating layer 31. Thereby, the surfaces of the core substrate 11 and the insulating layers 21 and 32 are cleaned. As shown in FIGS. 17 to 19, the adhesive layer 41 is formed on the cleaned surface, and the fibers 42 are adhered thereto, whereby the uneven layer firmly adhered to each surface. 40 will be obtained.

  In addition, after the formation of the uneven layer 40, plasma treatment can be performed. An example of the plasma treatment is shown in FIG. For example, as shown in FIGS. 24A, 24B, and 24C, after the formation of the concavo-convex layer 40, the surface of the concavo-convex layer 40 is similarly subjected to plasma treatment such as oxygen plasma (illustrated by thick arrows). ) Can be implemented. Thereby, the surface of the uneven | corrugated layer 40 is cleaned. As shown in FIGS. 21 and 22, the resin layer 50 is formed on the cleaned surface, and the first buildup layer 20 and the second buildup layer 30 are pressure bonded to the core layer 10. At this time, the resin layer 50 wets the fine unevenness of the clean uneven layer 40, that is, the surface of each fiber 42, and enters a narrow region between the fibers 42. Therefore, the resin layer 50 and the uneven layer It is possible to suppress the generation of a gap between the gaps 40 and 40. As a result, it is possible to suppress a decrease in the contact area between the uneven layer 40 and the resin layer 50 and firmly bond both. In addition, by suppressing the generation of voids, it is possible to avoid a situation in which the gas in the voids expands due to the heat applied to the circuit board 100 and the separation between the wiring layers is promoted.

  Further, in the circuit board 100 described above, the resin layer 50 exists between the adjacent joining members 60, and the uneven layer 40 in which the fibers 42 stand is present. Therefore, the outflow to the side of the joining member 60 is effectively suppressed, and a short circuit between the adjacent joining members 60 can be avoided.

Next, a second embodiment will be described.
FIG. 25 is a diagram illustrating an example of a circuit board according to the second embodiment. FIG. 25 schematically illustrates a cross-section of an essential part of an example of a circuit board according to the second embodiment.

  A circuit board 400 according to the second embodiment shown in FIG. 25 includes the uneven layer 440 formed by an imprint method or the like, and the circuit board 100 according to the first embodiment. Is different. In the circuit board 400, the core layer 10 and the first buildup layer 20 are bonded together via the uneven layer 440 and the resin layer 50, and the core layer 10 and the second buildup layer 30 are interposed via the uneven layer 440 and the resin layer 50. It is pasted together. The first buildup layer 20 and the second buildup layer 30 are electrically connected using a joining member 60 such as solder.

  In the circuit board 400, the uneven layer 440 as described above is provided on the wiring layers such as the first buildup layer 20, the second buildup layer 30, and the core layer 10. Therefore, unlike the method of roughening the surface of the wiring layer, the size of the unevenness is not limited by the internal structure of the wiring layer, and the internal structure of the wiring layer is not damaged because the uneven layer 440 is provided. In the concavo-convex layer 440, for example, by adjusting the concavo-convex size of the mold used when forming by the imprint method, the concavo-convex layer 440 has deep concavo-convex and concavo-convex with a narrow interval (period) compared to the case of roughening the surface of the wiring layer Can be formed.

  In addition, as the 1st buildup layer 20 and the 2nd buildup layer 30, what has the same structure can be used like FIG. In addition, a build-up layer having a different structure may be bonded to the front and back sides of the core layer 10. In addition to the core layer 10 having the above-described structure, the structure can be changed according to the structure of the build-up layer to be bonded.

Next, an example of a circuit board forming method according to the second embodiment will be described.
Here, the first buildup layer 20, the second buildup layer 30, and the core layer 10 will be described as an example of bonding through the uneven layer 440 and the resin layer 50.

  The uneven layer 440 can be formed using, for example, an imprint method. Therefore, first, an example of a mold forming method used when forming the uneven layer 440 using the imprint method will be described in order with reference to FIGS.

FIG. 26 is a diagram showing an example of a first mold forming process.
In order to form a mold used for the imprint method, first, as shown in FIG. 26A, a resist 501 is formed on the surface (one surface) of a semiconductor substrate 500 such as a silicon (Si) substrate. For example, a photoresist is applied on the semiconductor substrate 500 and baked to be in a semi-cured state.

  After the formation of the resist 501, as shown in FIG. 26A, an exposure mask 502 in which a mask pattern is formed using a light shielding film such as a chromium (Cr) film is disposed above the semiconductor substrate 500. Then, using the exposure mask 502 as a mask, the resist 501 is exposed and developed to form an opening 501a in the resist 501 as shown in FIG. The mask pattern of the exposure mask 502 and the opening 501a of the resist 501 formed using the exposure mask 502 are formed in a shape and size based on the shape and size of the unevenness of the uneven layer 440 to be formed.

Instead of using the exposure mask 502 as described above, the opening 501a may be formed by exposing the resist 501 using an exposure apparatus such as a stepper and developing it.
After the opening 501a is formed in the resist 501, as shown in FIG. 26C, the semiconductor substrate 500 is etched using the resist 501 as a mask to form the unevenness 500a. For example, the unevenness 500a is formed on the semiconductor substrate 500 by RIE (Reactive Ion Etching).

The RIE conditions for forming the unevenness 500a are not particularly limited. For example, a mixed gas of a reactive gas and an inert gas is used as an etching gas. When a silicon substrate is used as the semiconductor substrate 500, the reactive gases include fluorine (F ₂ ), sulfur hexafluoride (SF ₆ ), carbon tetrafluoride (CF ₄ ), butane octafluoride (C ₄ F ₈ ). Fluorine-based gas can be used. Alternatively, chlorine (Cl ₂ ) or hydrogen (H ₂ ) may be used as the reactive gas. Moreover, as an inert gas, argon (Ar) gas can be used, for example.

  Further, the unevenness 500a can be formed by wet etching as well as dry etching such as RIE. When a silicon substrate is used as the semiconductor substrate 500, the unevenness 500a may be formed by wet etching using an etchant such as hydrofluoric acid or potassium hydroxide (KOH).

  After the formation of the unevenness 500a, the resist 501 is peeled off from the semiconductor substrate 500. As a result, a semiconductor substrate 500 (referred to as a mother die 500A) on which unevenness 500a is formed as shown in FIG.

FIG. 27 is a diagram illustrating an example of a second mold forming step.
After the formation of the mother die 500A, as shown in FIG. 27A, a metal layer 510 for embedding the unevenness 500a of the mother die 500A is formed. For example, as the metal layer 510, a nickel layer is formed using an electrolytic plating method.

  After the formation of the metal layer 510, the metal layer 510 is removed from the mother die 500A to obtain a metal layer 510 (referred to as a mold 510A) in which irregularities 510a complementary to the irregularities 500a of the mother die 500A are formed.

  Subsequently, an example of a method of bonding the core layer 10, the first buildup layer 20, and the second buildup layer 30 with the uneven layer 440 interposed therebetween will be sequentially described with reference to FIGS. 28 to 35. The concavo-convex layer 440 according to the second embodiment forms the concavo-convex layer 440 using a mold 510A having a predetermined concavo-convex 510a formed according to the example shown in FIGS. Can do. The uneven layer 440 can be formed in the process of bonding the core layer 10, the first buildup layer 20, and the second buildup layer 30 together.

FIG. 28 is a diagram illustrating an example of a first step of bonding according to the second embodiment.
First, the uneven layer 440 is formed on each of the core layer 10 to be bonded and the first buildup layer 20, for example.

  When the uneven layer 440 is formed, as shown in FIG. 28A, a thermosetting resin 441 is formed on the surface of the first buildup layer 20 to be bonded to the core layer 10. Further, as shown in FIG. 28B, a resin 441 is also formed on the surface of the core layer 10 to be bonded to the first buildup layer 20. For example, a resin film can be used as the resin 441 formed on the core layer 10 and the first buildup layer 20, and such a resin film is laminated on the core layer 10 and the first buildup layer 20. Thus, the resin 441 is formed.

Note that the electrode 12a of the core layer 10 and the electrode 22c of the first buildup layer 20 may be covered with a resin 441 at this stage as shown in FIG.
FIG. 29 is a diagram illustrating an example of a second step of bonding according to the second embodiment.

  After the resin 441 is formed, the mold 510A formed as shown in FIGS. 26 and 27 is used, and the mold 510A is pressurized while being heated to the resin 441. Thereby, as shown in FIGS. 29A and 29B, the unevenness 441a complementary to the unevenness 510a of the mold 510A is transferred to the surface of the resin 441.

FIG. 30 is a diagram illustrating an example of a third step of bonding according to the second embodiment.
After the unevenness 441a is transferred to the resin 441, the mold 510A is removed from the resin 441, and heat treatment is performed to cure the resin 441. Thus, a molded body of the resin 441 having the unevenness 441a provided on the core layer 10 and the first buildup layer 20 as shown in FIGS. 30A and 30B is obtained.

FIG. 31 is a diagram illustrating an example of a fourth step of bonding according to the second embodiment.
After the resin 441 on which the unevenness 441a is formed is cured, that is, after the molded body is formed, as shown in FIGS. 31A and 31B, the resin layer 441 side of the core layer 10 and the first buildup layer 20 is formed. On the other hand, plasma processing (illustrated by thick arrows) is performed. By this plasma treatment, the surface layer portion of the molded body of the resin 441 is removed, and the electrode 12a of the core layer 10 and the electrode 22c of the first buildup layer 20 are exposed. Thereby, the concavo-convex layer 440 provided on the core substrate 11 excluding the electrode 12a of the core layer 10, and the concavo-convex layer 440 provided on the insulating layer 21 excluding the electrode 22c of the first buildup layer 20, Each is formed.

FIG. 32 is a diagram illustrating an example of a fifth step of bonding according to the second embodiment.
The surface of the core layer 10 on which the second buildup layer 30 is bonded and the surface of the second buildup layer 30 on which the core layer 10 is bonded are the same as those shown in FIGS. As shown in FIGS. 32A and 32B, the uneven layer 440 is formed respectively.

FIG. 33 is a diagram illustrating an example of a sixth step of bonding according to the second embodiment.
After the uneven layer 440 is formed on the core layer 10 and the first buildup layer 20 and the second buildup layer 30, respectively, the first buildup layer 20 is formed as shown in FIGS. The joining member 60 is formed on the electrode 22 c and the electrode 32 c of the second buildup layer 30. For example, a tin-bismuth solder paste is formed as the joining member 60 by using a screen printing method.

FIG. 34 is a diagram illustrating an example of a seventh step of bonding according to the second embodiment.
As described above, the bonding member 60 is formed on the first buildup layer 20 and the second buildup layer 30, while the resin layer 50 is formed on the front and back surfaces of the core layer 10 in the region excluding the electrodes 12 a and 12 b. . For the resin layer 50, for example, an uncured resin film in which an opening is provided in a region excluding the electrodes 12a and 12b of the core layer 10 is used.

FIG. 35 is a diagram illustrating an example of the eighth step of bonding according to the second embodiment.
Next, as shown in FIG. 35, the first buildup layer 20 and the second buildup layer 30 on which the bonding member 60 is formed are formed on the front and back sides of the core layer 10 on which the resin layer 50 is formed, and the uneven layer 440 is formed on each other. The formed surfaces are opposed to each other and stacked. And the core layer 10, the 1st buildup layer 20, and the 2nd buildup layer 30 hold | maintain those lamination states, set to a metal mold | die, and heat it, pressurizing.

  During the heating and pressurizing process, the joining member 60 is melted and solidified, and the electrodes 12a and 22c and the electrodes 12b and 32c are electrically connected. Further, in the process of heating and pressing, the resin layer 50 is solidified by embedding the unevenness 441a of the unevenness layer 440, and the core layer 10 and the first buildup layer 20, and the core layer 10 and the second buildup layer 30 are formed. , Each will be glued.

Thereby, the circuit board 400 as shown in FIG. 25 can be obtained.
Note that plasma treatment using oxygen or the like may be performed before the formation of the resin 441 (FIGS. 28 and 32) and before the formation of the resin layer 50 (FIG. 34).

  Although the case where the uneven layer 440 is formed by the imprint method is described as an example here, the uneven layer 440 can also be formed using other methods. For example, after the resin 441 is formed (FIGS. 28 and 32), the unevenness 441a may be formed using a lithography technique and an etching technique without using the above-described mold 510A. Even with such a method, it is possible to avoid damage to the internal structure of the wiring layer, which may occur when the surface of the wiring layer is roughened, and to form deep irregularities and irregularities with a narrow period.

Next, a third embodiment will be described.
In the first and second embodiments, the circuit boards 100 and 400 in which the core layer 10, the first buildup layer 20, and the second buildup layer 30 are bonded using the uneven layers 40 and 440 have been described. . In addition, the build-up layers can be bonded to each other using the uneven layers 40 and 440 as described above.

FIG. 36 shows an example of a circuit board according to the third embodiment. Note that FIG. 36 schematically illustrates a cross-section of an essential part of an example of a circuit board according to the third embodiment.
In the circuit board 600 according to the third embodiment shown in FIG. 36, the first buildup layer 20 and the second buildup layer 30 are bonded to the front and back surfaces of the third buildup layer 610. Here, as an example, the third buildup layer 610 and the first buildup layer 20 are bonded together via the uneven layer 40 and the resin layer 50, and the third buildup layer 610 and the second buildup layer 30 are combined with the uneven layer 40 and The form bonded through the resin layer 50 is illustrated.

  In the third buildup layer 610, for example, first, the formation of the resin layer 611 and the conductive pattern 612 is alternately repeated for a predetermined number of layers. Thereafter, the through hole 613 is formed using a drill or the like, and the via 613a in the through hole 613 and the electrodes 614a and 614b on the front and back surfaces are formed.

  As described above, the unevenness layer 40 is provided on the bonding surfaces of the third buildup layer 610 and the first buildup layer 20 and the second buildup layer 30, thereby improving the adhesion of each buildup layer. It becomes possible.

  In addition, although the case where the uneven | corrugated layer 40 containing the contact bonding layer 41 and the fiber 42 was used as illustrated in 1st Embodiment was illustrated here, it replaced with such an uneven | corrugated layer 40, and 2nd implementation. The uneven layer 440 formed using an imprint method or the like as described in the embodiment can also be used.

Next, a fourth embodiment will be described.
As described above, an electronic component such as a semiconductor element can be mounted on the circuit board using the uneven layers 40 and 440 for bonding the wiring layers (core layer and build-up layer). In addition, the circuit board on which the electronic component is mounted can be mounted on another circuit board such as a mother board.

  FIG. 37 and FIG. 38 are diagrams illustrating an example of an electronic device according to the fourth embodiment. FIG. 37 and FIG. 38 schematically show a cross section of an essential part of an example of an electronic apparatus according to the fourth embodiment.

  The electronic device 700 shown in FIG. 37 has a structure in which a semiconductor element 710 is mounted as an electronic component on the circuit board 100a, for example, on the first buildup layer 20 here. The semiconductor element 710 is flip-chip connected to the electrode 22d of the circuit board 100a by using, for example, a bump 711 such as a solder ball and reflowing it at a predetermined temperature.

  As described above, the circuit board 100a is provided with the uneven layer 40 on each wiring layer of the core layer 10, the first buildup layer 20, and the second buildup layer 30, so that the adhesion by the resin layer 50 is improved. It is possible. Therefore, even if stress is generated in the circuit board 100a due to heat applied when the semiconductor element 710 is flip-chip connected or heat generated during operation of the semiconductor element 710, peeling between opposing wiring layers or It becomes possible to suppress the disconnection by it.

  An electronic device 700 as shown in FIG. 37 can be further mounted on a mother board 720, for example, as shown in FIG. The electronic device 700 can be mounted on the mother board 720 using bumps 721 such as solder balls. Even when the circuit board 100a is mounted on the mother board 720 as described above, the concavo-convex layer 40 of the circuit board 100a suppresses the separation between the wiring layers facing each other and the disconnection caused thereby.

Although the electronic device 700 using the circuit board 100a is illustrated here, an electronic device using the circuit board including the concavo-convex layers 40 and 440 can obtain the same effect as described above.
The circuit board using the concavo-convex layers 40 and 440 has been described above. However, it is possible to adopt a form in which both the concavo-convex layers 40 and 440 are mixed in one circuit board.

  The uneven layers 40 and 440 are not necessarily provided on both surfaces of the wiring layers to be bonded, and may be provided on the surface of any one of the wiring layers to be bonded. Is possible.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Appendix 1) a first wiring layer;
A second wiring layer disposed opposite to the first wiring layer;
A resin layer provided between the first wiring layer and the second wiring layer;
A circuit board comprising: an uneven layer provided on at least one surface of the opposing surface of the first wiring layer and the second wiring layer and embedded in the resin layer.

(Additional remark 2) The said uneven | corrugated layer is
An adhesive layer disposed on the surface on which the uneven layer is provided;
The circuit board according to claim 1, further comprising a plurality of fibers bonded to the adhesive layer.

(Supplementary note 3) The circuit board according to supplementary note 2, wherein the plurality of fibers are forested and adhered to the adhesive layer.
(Additional remark 4) The said uneven | corrugated layer is a molded object by which the unevenness | corrugation was formed in the opposite side to the said surface side in which the said uneven | corrugated layer is provided, The circuit board of Additional remark 1 characterized by the above-mentioned.

(Supplementary note 5) The circuit board according to any one of supplementary notes 1 to 4, wherein the first wiring layer and the second wiring layer are electrically connected within the resin layer.
(Additional remark 6) The said uneven | corrugated layer is provided except the area | region which electrically connects a said 1st wiring layer and a said 2nd wiring layer, The additional description 1 thru | or 5 characterized by the above-mentioned. Circuit board.

(Appendix 7) a first wiring layer;
A second wiring layer disposed to face the first surface side of the first wiring layer;
A third wiring layer disposed to face the second surface side of the first wiring layer;
A first resin layer provided between the first wiring layer and the second wiring layer;
A first concavo-convex layer provided on at least one of the opposing surfaces of the first wiring layer and the second wiring layer and embedded in the first resin layer;
A second resin layer provided between the first wiring layer and the third wiring layer;
A circuit board comprising: a second concavo-convex layer provided on at least one of opposing surfaces of the first wiring layer and the third wiring layer and embedded in the second resin layer.

(Additional remark 8) The process of providing an uneven | corrugated layer on the at least one surface of a 1st wiring layer and a 2nd wiring layer,
Disposing the first wiring layer and the second wiring layer opposite to each other with the uneven layer and the resin layer interposed therebetween;
A step of bonding the first wiring layer and the second wiring layer using the resin layer.

(Supplementary Note 9) The step of providing the uneven layer includes
Arranging an adhesive layer on the surface on which the uneven layer is provided;
The method for manufacturing a circuit board according to appendix 8, further comprising: bonding a plurality of fibers to the adhesive layer.

(Supplementary note 10) The method for manufacturing a circuit board according to supplementary note 9, wherein the plurality of fibers are dispersed and adhered to the adhesive layer by electrostatic force and adhered to the adhesive layer.
(Supplementary Note 11) The step of providing the uneven layer includes
Arranging a resin on the surface on which the uneven layer is provided;
The method for manufacturing a circuit board according to appendix 8, wherein the resin includes a step of forming irregularities using a mold.

  (Supplementary Note 12) The step of bonding the first wiring layer and the second wiring layer includes a step of electrically connecting the first wiring layer and the second wiring layer within the resin layer. 12. The method for manufacturing a circuit board according to any one of appendices 8 to 11, which is characterized in that

  (Additional remark 13) The said uneven | corrugated layer and the said resin are provided except the area | region which electrically connects a said 1st wiring layer and a said 2nd wiring layer, The additional description 8 thru | or 12 characterized by the above-mentioned. A method of manufacturing a circuit board.

(Supplementary Note 14) a first wiring layer;
A second wiring layer disposed opposite to the first wiring layer;
A resin layer provided between the first wiring layer and the second wiring layer;
A circuit board having an uneven layer provided on at least one of the opposing surfaces of the first wiring layer and the second wiring layer and embedded in the resin layer;
An electronic device comprising: a semiconductor element mounted on the circuit board.

1a, 1b, 100, 100a, 400, 600 Circuit board 2 First wiring layer 3 Second wiring layer 4, 50, 611 Resin layer 5, 40, 440 Uneven layer 5a, 441a, 500a, 510a Uneven 10 Core layer 11, 301 Core substrate 11a, 303, 613 Through hole 12, 22, 32, 612 Conductive pattern 12a, 12b, 22c, 22d, 32c, 32d, 614a, 614b Electrode 12c, 22b, 32b, 211b, 613a Via 13, 24, 34 , 214, 309 Plating layer 14, 203, 207, 306, 441 Resin 20 First build-up layer 21, 31 Insulating layer 22a, 32a, 211a Wiring 23, 33, 212 Protective film 30 Second build-up layer 41 Adhesive layer 42 Fiber 60 Joining member 200,300 Support body 201 Substrate 202,205 , 205c, 211, 302, 305, 305a, 307 Copper layer 204 Copper foil 205 Three layer foil 205b, 214a, 309a Nickel layer 206, 210, 308 Resist pattern 208 Via hole 209, 304 Seed layer 210a, 501a Opening 213 Protective film 214b, 309b Gold layer 220 Structure 220a, 220b Structure 500 Semiconductor substrate 500A Master mold 501 Resist 502 Exposure mask 510 Metal layer 510A Mold 610 Third buildup layer 700 Electronic device 710 Semiconductor element 711, 721 Bump 720 Motherboard

Claims (8)

A first wiring layer;
A second wiring layer disposed opposite to the first wiring layer;
A resin layer provided between the first wiring layer and the second wiring layer;
A circuit board comprising: an uneven layer provided on at least one surface of the opposing surface of the first wiring layer and the second wiring layer and embedded in the resin layer. The uneven layer is
An adhesive layer disposed on the surface on which the uneven layer is provided;
The circuit board according to claim 1, further comprising: a plurality of fibers bonded to the adhesive layer.   The circuit board according to claim 1, wherein the concavo-convex layer is a molded body having concavo-convex formed on a side opposite to the surface side on which the concavo-convex layer is provided. A first wiring layer;
A second wiring layer disposed to face the first surface side of the first wiring layer;
A third wiring layer disposed to face the second surface side of the first wiring layer;
A first resin layer provided between the first wiring layer and the second wiring layer;
A first concavo-convex layer provided on at least one of the opposing surfaces of the first wiring layer and the second wiring layer and embedded in the first resin layer;
A second resin layer provided between the first wiring layer and the third wiring layer;
A circuit board comprising: a second concavo-convex layer provided on at least one of opposing surfaces of the first wiring layer and the third wiring layer and embedded in the second resin layer. Providing an uneven layer on at least one surface of the first wiring layer and the second wiring layer;
Disposing the first wiring layer and the second wiring layer opposite to each other with the uneven layer and the resin layer interposed therebetween;
A step of bonding the first wiring layer and the second wiring layer using the resin layer. The step of providing the uneven layer includes
Arranging an adhesive layer on the surface on which the uneven layer is provided;
The method for manufacturing a circuit board according to claim 5, further comprising: bonding a plurality of fibers to the adhesive layer. The step of providing the uneven layer includes
Arranging a resin on the surface on which the uneven layer is provided;
The method for manufacturing a circuit board according to claim 5, further comprising: forming irregularities on the resin using a mold. A first wiring layer;
A second wiring layer disposed opposite to the first wiring layer;
A resin layer provided between the first wiring layer and the second wiring layer;
A circuit board having an uneven layer provided on at least one of the opposing surfaces of the first wiring layer and the second wiring layer and embedded in the resin layer;
An electronic device comprising: a semiconductor element mounted on the circuit board.

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