JP2012099769A - Manufacturing method of wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new manufacturing method which eliminates the need of posterior processes such as CMP in wiring formation process when manufacturing a wiring board having at least one conductor layer and one resin insulation layer.SOLUTION: A manufacturing method of a wiring board formed by laminating at least one conductor layer and one resin insulation layer includes a groove formation process in which a groove is formed on at least one resin insulation layer and a Cu paste filling process in which the groove is filled with Cu paste forming the conductor layer with an ink jet device.

Description

  The present invention relates to a method for manufacturing a wiring board.

  In recent years, with the higher integration and speeding up of LSIs, the multilayering and miniaturization of wiring are progressing. In particular, in logic devices, it is essential to reduce the minimum pitch of wiring to match the gate length in order to achieve high performance in transistor characteristics. It has become a matter.

  As such a fine wiring formation technique, a damascene method that does not require etching has become the mainstream in place of the dry etching technique used in the conventional Al wiring technique. The damascene method includes a single damascene method and a dual damascene method.

  In the single damascene method, a groove serving as a wiring is formed in an interlayer insulating film by laser light irradiation, a metal layer as a base film is further deposited, and a Cu film is deposited thereon by plating to form a wiring. Since the plating method is performed on the entire interlayer insulating film, the Cu film deposited on the interlayer insulating film must be removed by chemical mechanical polishing (CMP) or the like (see Patent Document 1).

  On the other hand, in the dual damascene method, via holes that make electrical contact with the lower wiring layer are formed simultaneously with the wiring grooves, and a metal layer as a base layer, a Cu film, and CMP are performed once, and wiring and vias are performed once.・ This is a method of forming plugs simultaneously. However, in this case as well, since the plating method is performed on the entire interlayer insulating film, the Cu film deposited on the interlayer insulating film must be removed by CMP or the like as described above (see Patent Document 2). .

  As described above, in the damascene method, the Cu film, that is, the wiring is formed by using the plating method in both the single damascene method and the dual damascene method, and thus the Cu film deposited on the interlayer insulating film is removed. Therefore, a grinding operation such as CMP, which is a subsequent process, is indispensable, and there is a problem that the wiring formation process, that is, the wiring board formation process becomes complicated.

JP 2007-116135 A JP 2006-49804 A

  An object of the present invention is to provide a novel manufacturing method that does not require post-processing such as CMP in a wiring formation process when manufacturing a wiring board having at least one conductor layer and a resin insulating layer.

In order to achieve the above object, the present invention provides:
A method of manufacturing a wiring board in which at least one conductor layer and a resin insulating layer are laminated,
A groove forming step of forming a groove in the at least one resin insulating layer;
A Cu paste filling step of filling the groove portion with a Cu paste to be the conductor layer using an inkjet device;
It is related with the manufacturing method of a wiring board characterized by providing.

  According to the present invention, after forming a groove portion in the resin insulating layer constituting the wiring board, the groove portion is filled with Cu paste by an ink jet method, and a conductor layer constituting the wiring or the like is formed from this Cu paste. Like to do. According to the ink jet method, by appropriately adjusting the size of the opening formed at the tip of the ink jet device to be used and the discharge amount of the Cu paste, a necessary amount of Cu paste can be applied to a necessary portion. Or can be filled.

  Therefore, if an ink jet system having such characteristics is used, an amount of Cu paste can be filled according to the size, width, depth, etc. of the groove, so that the Cu paste can be filled just inside the groove. As a result, a conductor layer such as a wiring can be formed. As a result, the Cu film or the like is not deposited on the resin insulating layer as in the case of using the plating method, so that a post-process such as CMP for removing the deposited Cu film becomes unnecessary.

  As will be described in detail below, when the groove is formed, that is, when the groove penetrates the resin insulating layer and exposes the lower wiring layer, the conductor formed by filling the Cu paste described above. The layer will constitute both wiring and vias. On the other hand, when the groove is formed without penetrating the resin insulating layer, the conductor layer formed by filling the Cu paste described above constitutes only the wiring.

  When both the wiring and the via are formed by filling the Cu paste, it is preferable to first fill the via hole and then fill the wiring groove. This improves the uniformity of the wiring made of the conductor layer.

  Further, when the Cu paste is ejected by the ink jet method, it is difficult to form a complete continuous body in which the coating thickness cannot be ensured as it is or the coating shape is connected with spots. However, in the present invention, since the Cu paste is discharged into the groove by the ink jet method, the discharged Cu paste is held by the wall surface of the groove. For this reason, as described above, by appropriately adjusting the discharge amount of the Cu paste, the discharged Cu paste is held by the wall surface of the groove, and a predetermined thickness can be ensured. Similarly, the Cu paste discharged into the groove due to the pressing force from the wall surface of the groove is formed not as a spot but as a substantially complete continuous body.

  As a result, the discharge of Cu paste by the ink jet method having the above-described defects is also suitable for wiring and the like when the same is used for filling the groove portion as in the present invention. A conductor layer having a thickness and shape can be formed.

  Note that at least one of a thermal ink jet apparatus and a piezo ink jet apparatus can be used as the ink jet apparatus. These ink jet devices are inexpensive and easily available, and the above-described filling of the Cu paste into the grooves can be performed in a good state.

  In one example of the present invention, in the Cu paste filling step, the filling of the Cu paste can be started in a state where the ejection hole located at the tip of the ink jet apparatus is disposed in the groove. In this case, scattering of the Cu paste to be filled can be prevented, and the target groove can be filled accurately with the Cu paste.

  As described above, according to the present invention, when manufacturing a wiring substrate having at least one conductor layer and a resin insulating layer, a novel manufacturing method that does not require post-processing such as CMP in the wiring formation process is provided. can do.

It is a top view of the wiring board in an embodiment. Similarly, it is a top view of the wiring board in an embodiment. It is a figure which expands and shows a part of cross section at the time of cutting the wiring board shown to FIG. 1 and 2 along the II line. It is a figure which expands and shows a part of cross section at the time of cutting the wiring board shown to FIG. 1 and 2 along the II-II line. It is one process figure in the manufacturing method of the wiring board in embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment. Similarly, it is one process figure in the manufacturing method of the wiring board in an embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Wiring board)
First, the configuration of the wiring board used in the method of the present invention will be described. However, the wiring board shown below is merely an example, and is not particularly limited as long as it has at least one conductor layer and a resin insulating layer.

  1 and 2 are plan views of the wiring board according to the present embodiment. FIG. 1 shows a state when the wiring board is viewed from the upper side, and FIG. 2 shows a case when the wiring board is viewed from the lower side. Shows the state. 3 is an enlarged view showing a part of a cross section when the wiring board shown in FIGS. 1 and 2 is cut along the line II, and FIG. 4 is shown in FIGS. It is a figure which expands and shows a part of cross section at the time of cutting the said wiring board along the II-II line.

  A wiring board 1 shown in FIGS. 1 to 4 has both surfaces of a plate-like core 2 made of a heat-resistant resin plate (for example, bismaleimide-triazine resin plate), a fiber-reinforced resin plate (for example, glass fiber-reinforced epoxy resin), or the like. In addition, core conductor layers M1 and M11 (also simply referred to as conductor layers) forming metal wiring 7a in a predetermined pattern are formed. These core conductor layers M1 and M11 are formed as a plane conductor pattern that covers most of the surface of the plate-like core 2, and are used as a power supply layer or a ground layer.

  On the other hand, a through-hole 12 drilled by a drill or the like is formed in the plate-like core 2, and a through-hole conductor 30 that connects the core conductor layers M 1 and M 11 to each other is formed on the inner wall surface thereof. The through hole 12 is filled with a resin filling material 31 such as an epoxy resin.

  Further, on the upper layers of the core conductor layers M1 and M11, first via layers (build-up layers: insulating layers) V1 and V11 made of a thermosetting resin composition 6 containing silica filler or the like as necessary. Are formed respectively. Further, the first conductor layers M2 and M12 forming the metal wiring 7b are respectively embedded in the surface portion. However, the plane level of the upper surface of the first via layers V1 and V11 is the same as the plane level of the upper surface of the metal wiring 7b, and the upper surface of the metal wiring 7b is exposed from the first via layers V1 and V11. .

  On the upper layer of the first via layers V1 and V11 and the first conductor layers M2 and M12, second via layers (build-up layers: insulating layers) V2 and V12 using the thermosetting resin composition 6 are provided. Each is formed.

  Also, second conductor layers M3 and M13 having metal terminal pads 10 and 17 are formed on the second via layers V2 and V12, respectively.

  The core conductor layers M1, M11 and the first conductor layers M2, M12 are connected to each other by filled vias 34-1. The via 34-1 includes a via hole 34-1h, a via conductor 34-1s provided so as to fill the via hole 34-1, and a via pad provided so as to be electrically connected to the via conductor 34-1s on the bottom surface side. 34-1p and via land 34-1l projecting outward from the peripheral edge of the opening of via conductor 34-1s on the side opposite to via pad 34-1p.

  The first conductor layers M2 and M12 (metal wiring 7b), the via conductors 34-1s and the via lands 34-1l are each manufactured according to the manufacturing method of the present invention described below.

  The via 34-1 is embedded in the first via layers V1 and V11. However, the planar level of the upper surface of the via land 34-1l and the planar level of the upper surfaces of the first via layers V1, V11 are the same, and the upper surface of the via land 34-1l is exposed from the first via layers V1, V11. ing.

  The first conductor layers M2, M12 and the second conductor layers M3, M13 are connected to each other by filled vias 34-2. The via 34-2 includes a via hole 34-2h, a via conductor 34-2s provided on the inner peripheral surface thereof, and a via land 34-2l projecting outward from the peripheral edge of the opening of the via conductor 34-2s. The via conductor 34-2s is electrically connected to the via land 34-1l of the via 34-1 and the metal wiring 7b.

  The second conductor layers M3 and M13 (metal terminal pads 10 and 17), the via conductors 34-2s and the via lands 34-2l are each manufactured according to the manufacturing method of the present invention described below.

  As described above, on the first main surface MP1 of the plate-like core 2, the core conductor layer M1, the first via layer V1, the first conductor layer M2, the second via layer V2, and the second conductor. The layers M3 are sequentially stacked to form the first wiring stacked portion L1. Further, on the second main surface MP2 of the plate-like core 2, the core conductor layer M11, the first via layer V11, the first conductor layer M12, the second via layer V12, and the second conductor layer M13 are formed. The layers are sequentially stacked to form the second wiring stacked portion L2. A plurality of metal terminal pads 10 are formed on the first main surface CP1, and a plurality of metal terminal pads 17 are formed on the second main surface CP2.

  Further, a solder resist layer 8 having an opening 8a is formed on the first main surface CP1, and formed on the metal terminal pad 10 and the via land 34-2l exposed to the opening 8a by electroless plating. Thus, a laminated film 10a containing nickel and gold is formed. A solder resist layer 18 having an opening 18a is also formed on second main surface CP2, and nickel and gold are included on metal terminal pad 17 and via land 34-2l exposed in opening 18a. A laminated film 17a is formed. However, the metal terminal pad 17 and the via land 34-2l may be directly exposed to the opening 18a without forming the laminated film 17a.

  In addition, in the opening 8a, for example, solder bumps 11 made of solder that does not substantially contain Pb, such as Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Sb, are formed on the metal pads 10 and the via lands 34-. It is formed so as to be electrically connected to 2l. Furthermore, solder balls and pins (not shown) are formed in the opening 18a so as to be electrically connected to the metal pad 17 and the via land 34-2l.

  1 to 4, the wiring board 1 in the present embodiment has a substantially rectangular plate shape, and the size thereof can be, for example, about 35 mm × about 35 mm × about 1 mm.

(Method for manufacturing a wiring board)
Next, a method for manufacturing the wiring board shown in FIGS. 5 to 19 are process diagrams in the manufacturing method of the present embodiment. In addition, the process drawing shown below shows the sequential process when it sees in the cross section at the time of cutting along the II line of a wiring board corresponded to FIG.

  First, as shown in FIG. 5, a plate-shaped heat-resistant resin plate (for example, a bismaleimide-triazine resin plate) or a fiber reinforced resin plate (for example, a glass fiber reinforced epoxy resin) is prepared as a core 2, and drilling, etc. The through hole 12 is drilled by the method. Next, as shown in FIG. 6, the core conductor layers M <b> 1 and M <b> 11 and the through hole conductor 30 are formed by pattern plating, and the resin hole filling material 31 is filled in the through hole 12.

  Next, after roughening the core conductor layers M1 and M11, the resin film 6 is laminated and cured so as to cover the core conductor layers M1 and M11, as shown in FIG. Get V11. The resin film may contain a filler as necessary.

  Next, as shown in FIG. 8, the insulating layer V1, V11 (via layer) is irradiated with a carbon dioxide laser or a UV gas laser from its main surface to form a via hole 34-1h in a predetermined pattern. A roughening process is performed on the insulating layers V1 and V11 including 1h. In addition, the intensity | strength (output) of a carbon dioxide laser and UV gas laser shall be 10W-200W, for example. When the insulating layers V1 and V11 include a filler, when the roughening process is performed on the insulating layers V1 and V11 as described above, the filler is released and remains on the insulating layers V1 and V11. Therefore, water washing is appropriately performed to remove the free filler.

  Next, desmear processing and outline etching are performed to clean the inside of the via hole 34-1h. In addition, in this example, since water washing is implemented, the aggregation of the said filler can be suppressed in the case of water washing in a desmear process.

  Moreover, in this example, an air blow can be performed between the water washing by the high water pressure mentioned above and the said desmear process. Thereby, even when the filler liberated by the water washing described above is not completely removed, the removal of the filler can be supplemented in the air blow.

  Next, as shown in FIG. 9, a first mask 41 having openings 41a and 41b and a second mask 42 having openings 42a and 42b are arranged on the insulating layers V1 and V11, respectively. Excimer laser irradiation is performed through 41 and the second mask 42. Then, as shown in FIG. 10, the insulating layers V1 and V11 have wiring grooves 6a for the metal wiring 7b corresponding to the opening 41a of the first mask 41 and the opening 42a of the second mask 42, respectively. Grooves 6b for via lands 34-1l corresponding to the opening 41b of the first mask 41 and the opening 42b of the second mask 42 are formed. In addition, the intensity | strength (output) of an excimer laser shall be 10W-200W, for example.

  Since the wiring groove 6a and the groove 6b are collectively formed by excimer laser surface irradiation, the shape of the processing edge portion based on point processing varies as in the case of spot irradiation with a UV laser or the like, or by multiple irradiation. Problems such as variations in the depths of the wiring grooves 6a and the grooves 6b due to a plurality of point processings do not occur. As a result, fluctuations in the shape and thickness of the metal wiring 7b formed in the wiring groove 6a and the via land 34-1l formed in the groove 6b can be suppressed. In particular, the metal wiring 7b to be formed in the wiring substrate 1 can be suppressed. It is possible to prevent the impedance from becoming different from the design value, and to suppress a decrease in the manufacturing yield of the wiring board 1.

  However, when the size of the wiring substrate 1 to be formed is relatively large and a large number of wiring grooves 6a and grooves 6b must be formed, an excimer laser, a first mask 41, and a second mask 42 are used. Are appropriately moved, and the wiring trench 6a and trench 6b are sequentially formed at the locations where the insulating layers V1 and V11 are to be formed.

  The wiring groove 6a and the groove 6b are formed so as not to penetrate the insulating layers V1 and V11.

  In the present embodiment, after forming the via hole 34-1h with a carbon dioxide laser or a UV gas laser, the wiring grooves 6a and 6b are formed by surface irradiation with an excimer laser. At this time, the bottom of the via hole 34-1l is also irradiated with the excimer laser, so that the processing residues of the insulating layers V1 and V11 remaining on the bottom can be removed and cleaned by surface irradiation with the excimer laser. Therefore, for example, operations such as water washing in the desmear process and subsequent air blow can be omitted.

  The via hole 34-1h can be formed by a general-purpose wet or dry etching process instead of the carbon dioxide laser or the UV gas laser. Further, the wiring groove 6a and the groove 6b can be formed by a general-purpose wet or dry etching process instead of excimer laser surface irradiation.

  Next, as shown in FIG. 11, the tip 51A of the inkjet device 51 is arranged in the via hole 34-1h and the Cu paste 52 is discharged, and as shown in FIG. 12, the via conductor 34 is placed in the via hole 34-1h. −1s is formed. Next, as shown in FIG. 13, the tip 51 </ b> A of the inkjet device 51 is similarly disposed in the wiring grooves 6 a and 6 b (only 6 b is shown in the figure), and the Cu paste 52 is ejected. As shown, the metal wiring 7b is formed in the wiring groove 6a, and the via land 34-1l is formed in the groove 6b. As a result, patterned conductor layers M2 and M12 can be obtained.

  In this case, since the wiring trench 6a and the trench 6b are formed so as not to penetrate the insulating layers V1 and V11, the metal wiring 7b may be formed in such a manner as to be embedded in the insulating layers V1 and V11. it can. Therefore, even when the metal wiring 7b is miniaturized, it can be prevented from dropping off.

  The via land 34-1l formed in the groove 6b is electrically connected to the via pad 34-1p, and the via pad 34-1p is electrically connected to a wiring (not shown). Part of the pattern). Therefore, from this viewpoint, in this embodiment, the groove 6b is also included in the category of the wiring groove.

  11 and 13, the tip 51A of the ink jet device 51 is disposed in the via hole 34-1h and the wiring groove 6a and the groove 6b so that the Cu paste 52 protrudes. The Cu paste 52 need not be discharged in a state where 51A is disposed in the via hole 34-1h or the like. However, by disposing the tip 51A of the ink jet device 51 in the via hole 34-1h or the like and causing the Cu paste 52 to protrude, the Cu paste to be filled can be prevented from being scattered, and the target groove portion can be prevented. That is, the Cu paste can be accurately filled in the via hole 34-1h and the like.

  Further, as the ink jet device 51, at least one of a thermal ink jet device and a piezo ink jet device can be used. These ink jet devices are inexpensive and easily available, and the Cu paste 52 can be filled in the above-described via holes 34-1h in a good state.

  Furthermore, in the process shown in FIGS. 11 to 14, the Cu paste 52 is filled in the via hole 34-1h first, and then the Cu paste 52 is filled in the wiring grooves 6a and 6b. In this case, the uniformity of the via land 34-1l and the metal wiring 7b is improved.

  In the present embodiment, a Cu paste is ejected into the via hole 34-1h and the wiring groove 6a and the groove 6b by the ink jet method using the ink jet device 51 to form the via conductor 34-1s, the via land 34-1l, and the metal wiring 7b. Like to do. According to the ink jet method, by appropriately adjusting the size of the opening formed in the tip 51A and the discharge amount of the Cu paste 52, a necessary amount of the Cu paste 52 is applied or filled in a necessary portion. You can do it.

  Therefore, if an ink jet system having such characteristics is used, an amount of Cu paste can be filled according to the size of the groove, that is, the width, depth, etc., so that the via hole 34-1h, the wiring groove 6a, the groove A Cu paste 52 that can just fill the inside of 6b can be supplied. As a result, a Cu film or the like is not deposited on the insulating layer V1 as in the case of using the plating method, so that a post-process such as CMP for removing the deposited Cu film becomes unnecessary. For this reason, the formation of the via conductor 34-1s, the via land 34-1l, and the metal wiring 7b, that is, the manufacture of the wiring board can be simplified.

  In general, when Cu paste is ejected by an ink jet method, it is difficult to ensure a sufficient coating thickness as it is, or it is difficult to form the coating shape as a complete continuous body in which spots are connected. However, in the present embodiment, since the Cu paste is discharged into the groove by the ink jet method, the discharged Cu paste is held by the groove, for example, the wall surface of the via hole 34-1h.

  For this reason, as described above, by appropriately adjusting the discharge amount of the Cu paste, the discharged Cu paste is held by the wall surface of the groove, and a predetermined thickness can be ensured. Similarly, the Cu paste discharged into the groove due to the pressing force from the wall surface of the groove is formed not as a spot but as a substantially complete continuous body. As a result, the via conductor 34-1s, the via land 34-1l, and the metal wiring 7b are formed as a continuous body, and no electrical failure occurs.

  Next, after roughening the first conductor layers M2 and M12, the resin film 6 is laminated and cured so as to cover the first conductor layers M2 and M12 as shown in FIG. Layers V2 and V12 are obtained. This resin film may also contain a filler as necessary, as described above.

  Next, as shown in FIG. 16, the insulating layers V2 and V12 (via layer) are irradiated with laser from the main surface to form via holes 34-2h in a predetermined pattern, and insulation including the via holes 34-2h. A roughening process is performed on the layers V2 and V12. When the insulating layers V2 and V12 include a filler, when the roughening process is performed on the insulating layers V2 and V12 as described above, the filler is released and remains on the insulating layers V2 and V12. Therefore, water washing and air blowing are appropriately performed as described above. Next, the via hole 34-2h is cleaned by performing desmear processing and outer shape etching (outline etching).

  Next, as shown in FIG. 17, via conductors 34-2 s, via lands 34-2 l, metal terminal pads 10, and metal terminal pads 10, by a method similar to the method described in FIGS. 9 to 14 and paragraphs [0043] to [0057]. 17 is formed, and patterned second conductor layers M3 and M13 are formed.

  Thereafter, as shown in FIG. 18, resist layers 8 and 18 are formed on the second conductor layers M3 and M13, respectively, and resist coating and exposure and development are performed, thereby opening the openings as shown in FIG. Portions 8a and 18a are formed.

  Next, after forming the laminated films 10a and 17a as conductor layers, for example, on the metal terminal pads 10 and 17 and the via land 34-2l exposed in the openings 8a and 18a by electroless plating, the openings 8a are laminated. Solder bumps 11 are formed on the film 10a through the laminated film 10a so as to be in electrical contact with the metal terminal pads 10 and the via lands 34-2l, thereby obtaining the wiring board 1 as shown in FIGS.

  The present invention has been described in detail with specific examples. However, the present invention is not limited to the above contents, and various modifications and changes can be made without departing from the scope of the present invention.

  For example, in the present embodiment, as shown in FIGS. 8 to 10, the wiring groove 6 a and the groove 6 b are formed after the via hole 34-1 h is formed, but after the wiring groove 6 a and the groove 6 b are formed. A via hole 34-1h may be formed. However, in this case, the processing residues of the insulating layers V1 and V11 remaining at the bottom of the via hole 34-1h that are generated when the via hole 34-1h is formed cannot be removed and cleaned by surface irradiation with an excimer laser. Therefore, it is difficult to omit operations such as water washing and subsequent air blow in the desmear process, and the manufacturing process becomes somewhat complicated.

1 Wiring board,
M1 Core conductor layer V1 First via layer M2 First conductor layer V2 Second via layer M11 Core conductor layer V11 First via layer M12 First conductor layer V12 Second via layer 6a Wiring groove 6b Groove 7a 7b Metal wiring 8, 18 Solder resist layer 8a, 18a Opening 10a, 17a Nickel / gold laminated film 34-1 and 34-2 Via 34-1h, 34-2h Via hole 34-1l, 34-2l Via land 34-1p Via pad 34-1s, 34-2s Via conductor 41 First mask 42 Second mask 51 Inkjet device

Claims (4)

A method of manufacturing a wiring board in which at least one conductor layer and a resin insulating layer are laminated,
A groove forming step of forming a groove in the at least one resin insulating layer;
A Cu paste filling step of filling the groove portion with a Cu paste to be the conductor layer using an inkjet device;
A method of manufacturing a wiring board, comprising:   In the Cu paste filling step, the Cu paste serving as the conductor layer is filled in a state in which the ejection holes for ejecting the Cu paste serving as the conductor layer located at the tip of the ink jet device are disposed in the groove portion. The method for manufacturing a wiring board according to claim 1, wherein the method starts. The groove includes a via hole and a conductor layer groove having different depths,
In the Cu paste filling step, the Cu paste serving as the conductor layer is filled in the conductor layer groove after filling the via hole with the Cu paste by the ink jet apparatus. The manufacturing method of the wiring board as described.   The method of manufacturing a wiring board according to claim 1, wherein the ink jet device is at least one of a thermal ink jet device and a piezo ink jet device.

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