JP2012084781A - Field-effect transistor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field-effect transistor having high reproducibility of transistor characteristics, high speed, and high power, and to provide a method of manufacturing the same.SOLUTION: A field-effect transistor 10 comprises a diamond substrate 11, a second electrode 13 and a third electrode 14 that are formed apart from each other on one surface 11a side of the diamond substrate 11, and a first electrode 15 formed between the two electrodes 13 and 14 so as to be spaced apart from the electrodes. A group III nitride semiconductor layer 12 is provided between the first electrode 15 and the diamond substrate 11, and a hole conduction channel region 16 is formed in a region near an interface 17 between the diamond substrate 11 and the group III nitride semiconductor layer 12.

Description

The present invention relates to a field effect transistor and a manufacturing method thereof.

A field effect transistor (hereinafter also abbreviated as FET) is an element having three electrodes, a gate electrode, a source electrode, and a drain electrode, and operates the voltage applied to the gate electrode to control the source. It is an element for controlling the current flowing between the electrode and the drain electrode.

Diamond is the ultimate material with extremely good mechanical, electrical, thermal, chemical, and optical properties. By fully exploiting the excellent properties of this material, it can be applied to various devices. Is possible. And it has the characteristic that the mobility of the carrier (electron and hole) in a diamond film is very high.
Therefore, the development of high-speed, high-power field-effect transistors that can operate stably, with high frequency, large current, and high withstand voltage in harsh environments is expected using diamond.
The structure of the current field effect transistor mainly composed of diamond can be roughly classified into four structures.

The first structure is a structure in which carriers are controlled by an electric field using a carrier conductive layer in diamond doped with acceptors and donors as impurities and using a rectifying (Schottky) metal electrode as a gate electrode. This structure has the same principle as that used in conventional silicon and gallium arsenide semiconductors.
However, in this structure, the ionization energy of the dopant inside the diamond is large, that is, the activation rate is small, and it is not easy to ensure a sufficient electron and hole concentration for driving as a field effect transistor at room temperature. Realization of high-speed, high-power field effect transistors is impossible.

The second structure uses a surface conductive layer made of hole carriers on the diamond hydrogen terminated surface formed spontaneously by performing hydrogen plasma treatment on the diamond surface by microwave plasma vapor deposition, as a channel, and Similarly, the carrier is controlled by the electric field of the gate electrode (Non-Patent Document 1). This structure is based on the principle of operation characteristic of diamond, and is the most experimentally advanced field effect transistor structure.
However, this structure has a problem that the device characteristics greatly depend on the operating environment due to thermal instability of the diamond hydrogen termination surface.

In the third structure, in order to overcome the disadvantage that the ionization energy of the dopant in diamond is large, boron, which is an acceptor impurity, is delta (local) doped at a concentration of about 10 ²⁰ cm ⁻³ within a depth of 1 nm from the surface. By doing so, the electric field controllability by the gate electrode is made possible while ensuring a sufficient hole concentration, and at the same time, it has a channel structure (Non-Patent Document 2).
However, in this structure, nano-scale local doping technology is difficult, and it is difficult to improve device performance.

The fourth structure is a structure using a heterojunction structure of a group III nitride semiconductor (for example, a semiconductor such as aluminum nitride) described in Patent Document 1 and Patent Document 2 and diamond.
In Patent Document 1, in the aluminum nitride / diamond laminated structure, by doping silicon into the aluminum nitride film as a donor, the potential energy difference between the silicon level in the film and the diamond conduction band edge energy level is obtained. A structure is disclosed that utilizes modulation doping to utilize and supply electrons into diamond. Here, the channel of the transistor is a two-dimensional electron in diamond.

On the other hand, Patent Document 2 discloses a two-dimensional electron in diamond in the vicinity of an interface generated to compensate for positive fixed charges generated by spontaneous polarization and piezoelectric polarization effects caused by residual strain such as aluminum nitride and boron nitride. A structure is disclosed in which is used as a channel.
Both of them operate using electrons as carriers, and variations in device performance and reproducibility pose problems due to non-uniformity of impurity dopant concentration and non-uniformity of residual strain distribution. Furthermore, since the potential barrier between n-type diamond and metal is 4 eV or more, it is extremely difficult to obtain a low-resistance ohmic electrode.
As described above, there has been no report on a high-speed / high-power diamond heterojunction field effect transistor with high reproducibility of transistor characteristics.

JP 2002-324812 A JP 2008-186936 A

H. Kawarada, M .; Aoki, and M.A. Ito, Appl. Phys. Letter 65 (1994) 1563-1565. “ENHANCEMENT-MODE METAL-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS USING HOMOEPITIAL DIAMONDS.” A. Aleksov, A.M. Vescan, M.M. Kunze, P.M. Gluche, W.M. Ebert, E .; Kohn, A .; Bergmaier, G.A. Dollinger: Diamond Relat. Mat. 8 (1999) 941. “Diamond junction FETs based on delta-doped channels.”

An object of the present invention is to provide a high-speed, high-power diamond heterojunction field effect transistor with high reproducibility of transistor characteristics and a method for manufacturing the same.

In view of the above circumstances, the present inventors have researched and developed a new operation in which a channel is a two-dimensional hole conduction layer that naturally appears on the diamond side of the diamond / III nitride semiconductor heterojunction interface. The present invention was completed by elucidating that the above problem can be solved by the FET of the principle.
The special point of the present invention is that (1) a low-resistance ohmic electrode for a hole channel in diamond can be easily produced by controlling the film thickness of the group III nitride semiconductor, (2) Since the hole channel exists under the group III nitride semiconductor, the channel is automatically protected and excellent in operational stability, and (3) no intentional impurity doping is required.
Further, in the present technology, for example, when AlN is used as a group III nitride semiconductor, holes are operated as carriers, and the structure differs from the energy band diagrams described in Patent Document 1 and Patent Document 2.
In addition, a group III nitride semiconductor thin film grown on a diamond single crystal substrate has a crystallographic structure including high-concentration dislocations and crystal grain boundaries, and the residual strain in the thin film is almost relaxed. The mechanism of pore development is different from the mechanism described in Patent Document 2.
Furthermore, in order to differentiate it from a diamond field effect transistor having a hydrogen termination surface, aluminum nitride was grown on diamond having an oxygen termination surface, and field effect transistor operation was demonstrated.

In this way, this technology dramatically improves the characteristics of field-effect transistors by using a combination of diamond and a group III nitride semiconductor, enabling stable, high-frequency, high-current, and high-voltage operation, and transistor characteristics. Therefore, the high-speed, high-power field effect transistor is put to practical use.
The present invention has the following configuration.

The field effect transistor of the present invention includes a diamond substrate, a second electrode and a third electrode formed on one side of the diamond substrate, and a second electrode formed between the two electrodes. A group III nitride semiconductor layer provided between the first electrode and the diamond substrate, and the diamond substrate and the group III nitride semiconductor layer. A hole conduction channel region is formed in a region near the interface.

In the field effect transistor of the present invention, the hole conduction channel region is preferably provided in the diamond substrate.
In the field effect transistor of the present invention, a group III nitride semiconductor layer is preferably provided between the second electrode and / or the third electrode and the diamond substrate.
In the field effect transistor of the present invention, the thickness of the group III nitride semiconductor layer between the second electrode and / or the third electrode and the diamond substrate is such that the first electrode, the diamond substrate, It is preferable that the thickness of the group III nitride semiconductor layer is less than the thickness of the intermediate layer.

In the field effect transistor of the present invention, it is preferable that the first electrode is a gate electrode, the second electrode is a source electrode, and the third electrode is a drain electrode.
In the field effect transistor of the present invention, the group III nitride semiconductor layer is preferably made of a polycrystalline body having hexagonal crystal grains.
In the field effect transistor of the present invention, the group III nitride semiconductor layer is preferably made of any one compound selected from the group consisting of AlN, BN, GaN, and InN.

In the field effect transistor of the present invention, it is preferable that the diamond substrate is a single crystal substrate, and one surface thereof is parallel to the (111) crystal surface.
In the field effect transistor of the present invention, it is preferable that one surface of the diamond substrate is oxygen-modified.

The field effect transistor manufacturing method of the present invention includes a step of heat-treating a diamond substrate in a hydrogen / ammonia atmosphere under a high pressure condition of 800 ° C. under reduced pressure, and a high pressure condition of 1200 ° C. or higher using a MOVPE method. A step of forming a group III nitride semiconductor layer on one surface of the diamond substrate, a step of partially removing the group III nitride semiconductor layer, a second electrode and a third surface on the one surface side of the diamond substrate. Forming an electrode, and forming a first electrode on one surface of the group III nitride semiconductor layer.

In the field effect transistor manufacturing method of the present invention, the film formation condition of the MOVPE method is 1 to 760 Torr in a state where trimethylaluminum gas, ammonia gas, and hydrogen gas are circulated in a container in which a diamond substrate is disposed. It is preferable to heat the diamond substrate to a temperature of 1200 ° C. to 2000 ° C. while reducing the pressure.

In the method for producing a field effect transistor of the present invention, it is preferable that the first electrode, the second electrode, and the third electrode are formed by a vapor deposition method and / or a sputtering method.
In the method for producing a field effect transistor of the present invention, it is preferable that one surface of the diamond substrate is subjected to an acid solution treatment or a heat treatment before the formation of the group III nitride semiconductor layer.
In the method for producing a field effect transistor of the present invention, it is preferable that the group III nitride semiconductor layer is partially removed by a lithography method.

In the method of manufacturing a field effect transistor according to the present invention, it is preferable that the group III nitride semiconductor layer is partially removed to form two stepped portions having a thinner group III nitride semiconductor layer. .
In the method of manufacturing a field effect transistor according to the present invention, it is preferable that the group III nitride semiconductor layer is partially removed to form two removed portions from which the group III nitride semiconductor layer is removed.

The field effect transistor of the present invention includes a diamond substrate, a second electrode and a third electrode formed on one side of the diamond substrate, and a second electrode formed between the two electrodes. A group III nitride semiconductor layer provided between the first electrode and the diamond substrate, and the diamond substrate and the group III nitride semiconductor layer. Since the hole conduction channel region is formed in the vicinity of the interface, the hole can be operated as a carrier. (2) Since the hole conduction channel region exists under the group III nitride semiconductor layer, The channel is automatically protected and has excellent operation stability, stable, high frequency, large current, and high voltage operation capability, high reproducibility of transistor characteristics, high speed and high power It can be a field effect transistor.
In particular, a group III nitride semiconductor layer such as a group III nitride semiconductor thin film grown on a diamond single crystal substrate has a crystallographic structure including a high concentration of dislocations and grain boundaries, and residual strain in the thin film Since the transistor characteristics can be controlled only by controlling the film thickness of the group III nitride semiconductor layer and the device size, the reproducibility is good.
As described above, stable, high frequency, large current, and high withstand voltage operation is possible, transistor characteristics are highly reproducible, and a high-speed, high-power field effect transistor can be obtained.

The field effect transistor manufacturing method of the present invention includes a step of heat-treating a diamond substrate in a hydrogen / ammonia atmosphere under a high pressure condition of 800 ° C. under reduced pressure, and a high pressure condition of 1200 ° C. or higher using a MOVPE method. A step of forming a group III nitride semiconductor layer on one surface of the diamond substrate, a step of partially removing the group III nitride semiconductor layer, a second electrode and a third surface on the one surface side of the diamond substrate. And a step of forming a first electrode on one surface of the group III nitride semiconductor layer. (1) A low-resistance ohmic electrode for a hole channel in diamond can be produced. It is easy and (3) does not require intentional impurity doping, operates as a hole, and is stable, high frequency, large current, high A pressure operation possible, it is possible to reproducibility of the transistor characteristic is high, to easily manufacture a high-speed, high-power field-effect transistor.

FIG. 1A is a schematic diagram illustrating an example of a field effect transistor according to the present invention, FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line A-A ′ of FIG. It is process drawing which shows an example of the manufacturing process of the field effect transistor of this invention. It is process drawing which shows an example of the manufacturing process of the field effect transistor of this invention. FIG. 4A is a schematic view showing another example of the field effect transistor of the present invention, FIG. 4A is a plan view, and FIG. 4B is a cross-sectional view taken along the line BB ′ of FIG. is there. It is a graph which shows the profile result of 2 (theta) -omega scan of the X-ray-diffraction method of the heterojunction structure (AlN and diamond) of Example 1. FIG. Cross-sectional transmission electron microscope image (FIG. 6 (a)) and transmission electron diffraction pattern (FIG. 6 (b), FIG. 6 (c)) in the vicinity of the aluminum nitride and diamond interface (hetero interface) of the heterojunction structure of Example 1. ). FIG. 7 is a surface optical microscope image (a), (b) and a schematic cross-sectional view (c) of the field effect transistor of Example 1, FIG. 7 (a) being a plan view, and FIG. 7 (b) being an enlarged view. FIG. 7C is a schematic sectional view. It is measurement arrangement | positioning of transistor characteristic evaluation of the field effect transistor of this invention. It is a graph which shows an example of the graph which shows the current voltage characteristic of the field effect transistor of this invention, Comprising: It is a graph which shows the current voltage characteristic of the field effect transistor of gate width (Wg) 30 micrometers and gate length (Lg) 160 micrometers, 9 (a) is a graph showing the gate voltage dependency of drain current (Id) −drain voltage (Vd), and FIG. 9 (b) is the gate voltage dependency of gate current (Ig) −drain voltage (Vd). It is a graph which shows. It is a graph which shows an example of the C-Vg characteristic of the field effect transistor of this invention, Comprising: The electrostatic capacitance between the source electrode and gate electrode of a field effect transistor with a gate width (Wg) of 30 micrometers and a gate length (Lg) of 160 micrometers -It is a graph which shows a voltage characteristic (C-Vg characteristic). It is a graph which shows the value of the hole concentration p with respect to the depth from the interface of the field effect transistor of this invention. FIG. 12A is a diagram illustrating an example of a band structure of a field effect transistor according to the present invention. FIG. 12A is a depleted band structure of the field effect transistor of the present invention, and FIG. FIG. 12C shows a band structure in a hole accumulation state.

(First embodiment of the present invention)
Hereinafter, a field effect transistor and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the accompanying drawings.

<Field effect transistor>
First, the field effect transistor according to the first embodiment of the present invention will be described.
1A and 1B are diagrams showing an example of a field effect transistor according to the first embodiment of the present invention, in which FIG. 1A is a plan view, and FIG. 1B is A in FIG. It is sectional drawing in the -A 'line.
As shown in FIG. 1A, a field effect transistor 10 according to a first embodiment of the present invention includes a diamond substrate 11 having a substantially rectangular shape in plan view and a group III nitride semiconductor layer 12 having a substantially rectangular shape in plan view. And a first electrode 15, a second electrode 13, and a third electrode 14 having a substantially rectangular shape in plan view.

As shown in FIG. 1B, the group III nitride semiconductor layer 12 is formed on the one surface 11 a of the diamond substrate 11.
The group III nitride semiconductor layer 12 is provided with two step portions 12e and 12f, and a protrusion 12d protruding from one surface 12c of the two step portions 12e and 12f, and one surface 12a of the protrusion 12d. A first electrode 15 is provided thereon.
A second electrode 13 and a third electrode 14 are provided on one surface 12c of the two step portions 12e and 12f, respectively.
The other surface 12 b of group III nitride semiconductor layer 12 is in contact with one surface 11 a of diamond substrate 11, and serves as interface 17 between group III nitride semiconductor layer 12 and diamond substrate 11. The diamond substrate 11 and the group III nitride semiconductor layer 12 are heterojunction through the interface 17.

The diamond substrate 11 is a single crystal diamond substrate. A transparent single crystal diamond substrate with a small amount of added impurities is preferred. For example, a type IIa insulating diamond single crystal substrate can be mentioned. The IIa type insulating substrate is a substrate having an impurity concentration (boron or nitrogen) of 1 ppm or less. Thereby, when a heterojunction with group III nitride semiconductor layer 12 is formed, hole conduction channel region 16 can be formed in a region near interface 17.

However, the diamond substrate 11 only needs to be able to generate holes in the hole conduction channel region 16 in the vicinity of the interface 17 when the heterojunction with the group III nitride semiconductor layer 12 is formed. May be added. The impurity concentration and type are preferably those that increase the concentration of holes in the hole conduction channel region 16 in the region near the interface 17 when a heterojunction with the group III nitride semiconductor layer 12 is formed.

The one surface 11a of the diamond substrate 11 is preferably a (111) plane or a plane parallel to the (111) crystal plane. Thereby, the highly stable group III nitride semiconductor layer 12 can be formed, and the reproducibility of the transistor characteristics of the field effect transistor can be improved. However, other stable index surfaces may be used.

Instead of the diamond substrate 11, a substrate obtained by growing diamond on a substrate made of another material (for example, silicon having the same crystal structure) may be used. By forming the group III nitride semiconductor layer 12 on the diamond single crystal growth film, a field effect transistor in which the hole conduction channel region 16 is formed in the region near the interface 17 can be formed. The method for growing the diamond is not particularly limited.

The diamond substrate 11 is preferably subjected to an oxygen-terminated surface treatment in which one surface is oxygen-modified by a treatment of dipping one surface in a strong acid or a heat treatment. Thereby, when the diamond substrate 11 and the group III nitride semiconductor layer 12 are heterojunctioned, the hole conduction channel region 16 can be more easily formed in the region near the interface 17. At this time, the method for producing the oxygen-terminated surface is not particularly limited.
Note that the diamond substrate 11 may be obtained by subjecting one surface 11a to a hydrogen termination surface treatment or a termination surface treatment in which hydrogen and oxygen are mixed.

As shown in FIG. 1B, it is preferable that a group III nitride semiconductor layer 12 is provided between the second electrode 13 and the third electrode 14 and the diamond substrate 11. By forming a heterojunction structure composed of the diamond substrate 11 and the group III nitride semiconductor layer 12, the hole conduction channel region 16 is formed in the vicinity of the interface 17 between the diamond substrate 11 and the group III nitride semiconductor layer 12. The formed field effect transistor can be formed.

The group III nitride semiconductor layer 12 is preferably made of any one compound selected from the group consisting of AlN, BN, GaN, and InN, and more preferably AlN. Thereby, a field effect transistor in which the hole conduction channel region 16 is formed in the region near the interface 17 between the diamond substrate 11 and the group III nitride semiconductor layer 12 can be formed.

The group III nitride semiconductor layer 12 is preferably made of a polycrystal having hexagonal crystal grains, more preferably hexagonal aluminum nitride (AlN). Thus, when the group III nitride semiconductor layer 12 is formed on the (111) plane of the diamond single crystal substrate, the (0001) plane of the hexagonal crystal grains is brought into close contact with the (111) plane of the diamond single crystal substrate. A field effect transistor in which the hole conduction channel region 16 is formed in the vicinity of the interface 17 between the diamond substrate 11 and the group III nitride semiconductor layer 12 can be formed.
A hexagonal group III nitride semiconductor and a cubic group III nitride semiconductor can also be used. Moreover, the growth method of both materials is also arbitrary.

As shown in FIGS. 1A and 1B, the second electrode 13 and the third electrode 14 are formed on the one surface 12 c of the group III nitride semiconductor layer 12 so as to be separated from each other.
Further, the first electrode 15 is provided between the second electrode 13 and the third electrode 14 with the protruding portion 12 d of the group III nitride semiconductor layer 12 interposed therebetween.

It is preferable that the first electrode 15 is a gate electrode, the second electrode 13 is a source electrode, and the third electrode 14 is a drain electrode. Thus, a general three-terminal field effect transistor having a source electrode (S) -drain electrode (D) -gate electrode (G) can be formed.

As the material of the first electrode 15, the second electrode 13, and the third electrode 14, a conductive material such as a metal or an alloy is used. It should be noted that any material other than the metal material may be used as long as ohmic characteristics and Schottky characteristics are obtained.
In particular, it is preferably formed as a laminated structure made of a plurality of metals. Thereby, the current injection characteristics from the second electrode 13 and the third electrode 14 to the hole conduction channel region 16 can be improved, and the carriers in the hole conduction channel region 16 from the first electrode 15 are controlled. A possible voltage can be efficiently applied, and the stability of each electrode with respect to external water or air can be improved.
Examples of the laminated structure include a four-layer structure in which titanium with a thickness of 25 nm, aluminum with a thickness of 100 nm, titanium with a thickness of 50 nm, and gold with a thickness of 250 nm are formed in this order and thickness on the substrate side. Examples thereof include a two-layer structure in which 200 nm of nickel and 200 nm of gold are formed in this order from the substrate side.

As shown in FIG. 1B, a hole conduction channel region 16 is formed in a region in the vicinity of the interface 17 between the diamond substrate 11 and the group III nitride semiconductor layer 12. More specifically, the hole conduction channel region 16 is provided in the diamond substrate 11. As a result, a current can flow in the hole conduction channel region 16 between the second electrode 13 that is the source electrode and the third electrode 14 that is the drain electrode. The current can be controlled by the first electrode 15 which is a gate electrode.

As shown in FIG. 1B, the layer thickness t _{1 of the} group III nitride semiconductor layer 12 between the first electrode 15 and the diamond substrate 11 is equal to the second electrode 13 and the third electrode 14 and diamond. it is preferably greater than the thickness _{t 2} of the group III nitride semiconductor layer 12 between the substrate 11. Thereby, the resistance between the second electrode 13 and the third electrode 14 and the group III nitride semiconductor layer 12 can be reduced, and the second electrode 13 as the source electrode and the first electrode as the drain electrode can be reduced. A current can be efficiently passed in the hole conduction channel region 16 between the three electrodes 14. The current can be controlled by the first electrode 15 which is a gate electrode.
In FIG. 1 (b), the layer thickness t ₂ of the group III nitride semiconductor layer 12 between the second electrode 13 and third electrode 14 and the diamond substrate 11 is the same thickness, the The layer thickness of the group III nitride semiconductor layer 12 between the second electrode 13 and the third electrode 14 and the diamond substrate 11 may be different. In that case, the thicker the layer thickness as t _2, it is preferred that this is thinner than t _1.
The layer thickness t ₁ of the group III nitride semiconductor layer 12 between the first electrode 15 and the diamond substrate 11 is preferably 70 nm or more and 500 nm or less, and more preferably 100 nm or more and 350 nm or less. When it is less than 70 nm, a leakage current is generated, which is not preferable.
Thickness _{t 2} of the group III nitride semiconductor layer 12 between the second electrode 13 and third electrode 14 and the diamond substrate 11 is preferably set to 70nm or less, and more preferably to 10nm or less. If it exceeds 70 nm, it becomes difficult to inject carriers from the second electrode 13 and the third electrode 14 into the hole conduction channel region 16 to cause a current to flow.
The group III nitride semiconductor layer 12 may be eliminated between the second electrode 13 and the third electrode 14 and the diamond substrate 11. Even in this case, the resistance between the second electrode 13 and the third electrode 14 and the diamond substrate 11 can be reduced, and the second electrode 13 that is the source electrode and the third electrode that is the drain electrode. 14, current can flow efficiently in the hole conduction channel region 16.

<Method of manufacturing field effect transistor>
Next, the manufacturing method of the field effect transistor which is the 1st Embodiment of this invention is demonstrated.
The field effect transistor manufacturing process according to the first embodiment of the present invention includes a step of forming a group III nitride semiconductor layer on one surface of a diamond substrate by a MOVPE method (group III nitride semiconductor layer forming step), A step of partially removing the group III nitride semiconductor layer (group III nitride semiconductor layer pattern forming step), forming a second electrode and a third electrode on one surface side of the diamond substrate, and the group III And a step of forming a first electrode on one surface of the nitride semiconductor layer (first electrode, second electrode and third electrode forming step).
A method of forming a plurality of field effect transistors at once using aluminum nitride (AlN) as the material of the group III nitride semiconductor layer will be described as an example.
2 and 3 are process diagrams showing an example of the manufacturing process of the field effect transistor according to the first embodiment of the present invention.

{Group III nitride semiconductor layer forming step}
First, a single crystal diamond substrate is prepared by high-temperature and high-pressure synthesis. A commercially available diamond single crystal substrate may be used.
Next, the diamond substrate is boiled in a mixed solution of nitric acid and sodium chlorate (NaClO ₃ ) for 1 hour, and then boiled in a mixed solution of nitric acid and hydrofluoric acid for 1 hour. Thus, impurities on the surface of the diamond substrate can be removed, and a diamond substrate having one surface that is an oxygen-terminated surface can be obtained.
Note that only the acidic solution treatment or the heat treatment may be performed. Thereby, it can be set as the diamond substrate which one side is an oxygen termination surface.
Note that after obtaining a diamond having an oxygen-terminated surface, the diamond substrate may be subjected to hydrogen annealing treatment (heat treatment) in a hydrogen atmosphere. Further, annealing (heat treatment) may be performed in a mixed atmosphere of hydrogen and ammonia. The annealing time is, for example, 5 minutes.
The heating temperature of the heat treatment is preferably 800 ° C to 2000 ° C, more preferably 1000 ° C to 1500 ° C, and still more preferably 1200 ° C to 1400 ° C.

Next, the diamond substrate is carried into a metal organic vapor phase epitaxy apparatus, and aluminum nitride is grown on one surface of the diamond substrate by a metal organic vapor phase epitaxy method (MOVPE method).
The deposition conditions for the metal organic chemical vapor deposition method (MOVPE method) are as follows: trimethylaluminum gas (TMAI gas), ammonia gas (NH ₃ gas), and hydrogen gas (H ₂ gas) are circulated in the metal organic vapor phase growth apparatus. In this state, the diamond substrate is heated to a temperature of 1200 ° C. to 2000 ° C. under a reduced pressure condition of 1 to 760 Torr or less.
Note that the heating temperature of the heat treatment in the MOVPE film formation is more preferably 1220 ° C to 1500 ° C, and still more preferably 1240 ° C to 1400 ° C.
Further, the reduced pressure condition of the heat treatment in the MOVPE film formation is more preferably 10 Torr to 500 Torr, and further preferably 20 Torr to 300 Torr.
For example, the flow rate of TMAI gas is set to 10 to 1000 sccm, and the flow rate of NH ₃ gas is set to 0.01 to 1 slm.
Note that it is preferable to continue supplying NH ₃ gas until the growth temperature falls to 600 ° C. or lower even after the growth of aluminum nitride.
The thickness of the group III nitride semiconductor layer is preferably 100 to 2000 nm, and more preferably 300 to 1600 nm.

Through the above steps, a group III nitride semiconductor layer 12 made of AlN is formed on one surface 11a of the diamond substrate 11, as shown in FIG. A heterojunction is formed at the interface between the diamond substrate and the group III nitride semiconductor layer 12 made of AlN. Thereby, a hole conduction channel region can be formed in a region near the interface between diamond substrate 11 and group III nitride semiconductor layer 12.

{Group III nitride semiconductor layer pattern forming step}
Next, AlN on the diamond substrate is patterned to leave AlN under the pattern, and AlN other than the pattern is completely etched and removed.
Next, a normal photolithography method is used for patterning, and an inductively coupled plasma etching apparatus is used for etching AlN. A dry etching process technique can be used using chlorine Cl ₂ as an etching gas. Thereby, the element isolation structure shown in FIG. 2B can be formed.
The patterning process of AlN is not limited to a normal photolithography method, and electron beam lithography or laser lithography may be used. Similarly, electrode patterning and other thin film layer patterning shown in the following steps are not limited to ordinary photolithography, and electron beam lithography or laser lithography may be used.
In the etching process such as element isolation described above, a selective growth technique during crystal growth or a wet etching technique may be used.

Next, in order to reduce the contact resistance of the source-drain (SD) electrode, the aluminum nitride just under the metal used for the source-drain (SD) electrode is thinned by the same method as described above.
Specifically, as shown in FIG. 2C, the group III nitride semiconductor layer 12 at a predetermined position is partially removed to make the group III nitride semiconductor layer 12 thinner. Two step portions 12e and 12f are formed to form a convex structure AlN having a protruding portion 12d.

{First electrode, second electrode and third electrode forming step}
Next, a vapor deposition method or a sputtering method is used to form a metal film or a laminated structure of a plurality of metals on the one surface 11a side of the diamond substrate 11, and this is then patterned to form the first electrode 15, The electrode 13 and the third electrode 14 are formed.

Specifically, first, titanium with a thickness of 25 nm, aluminum with a thickness of 100 nm, titanium with a thickness of 50 nm, and gold with a thickness of 250 nm are formed in this order and thickness to form a four-layer structure. For this film formation, for example, an electron beam evaporation method is used.
Next, a pattern is produced by lift-off by a photolithography method.
Next, heat treatment of the four-layer structure is performed. The heat treatment time is preferably 400 ° C. to 1400 ° C., more preferably 600 ° C. to 1200 ° C. The heat treatment time is preferably 10 sec to 10 min, and more preferably 30 sec to 5 min. For example, the conditions are 900 ° C. and 1 min.
Thereby, as shown in FIG. 3A, the second electrode 13 and the third electrode 14 used as the source electrode and the drain electrode are formed.

Next, for the first electrode, nickel having a thickness of 200 nm and gold having a thickness of 200 nm are formed in this order to form a two-layer structure. For film formation, for example, an electron beam evaporation method is used.
Next, a pattern is produced by lift-off by a photolithography method.
Next, heat treatment of the two-layer structure is performed. The heat treatment time is preferably 400 ° C. to 1400 ° C., more preferably 600 ° C. to 1200 ° C. The heat treatment time is preferably 10 sec to 10 min, and more preferably 30 sec to 5 min. For example, the conditions are 900 ° C. and 1 min.
Thereby, as shown in FIG.3 (b), the 1st electrode 15 used as a gate electrode is formed.

Next, for example, the diamond substrate is divided for each field effect transistor element, and element isolation is performed.
Through the above steps, a field effect transistor 10 according to an embodiment of the present invention can be manufactured as shown in FIG.

(Second embodiment of the present invention)
Next, a field effect transistor according to a second embodiment of the present invention will be described.
4A and 4B are diagrams showing another example of the field effect transistor according to the embodiment of the present invention. FIG. 4A is a plan view, and FIG. It is sectional drawing in a B 'line.
As shown in FIG. 4A, the field effect transistor 20 according to the second embodiment of the present invention includes a group III nitride semiconductor between the second electrode 13 and the third electrode 14 and the diamond substrate 11. The configuration is the same as that of the field effect transistor 10 according to the first embodiment of the present invention except that the layer 22 is not provided.

As shown in FIG. 4, the other surface 22 b of the group III nitride semiconductor layer 22 is in contact with the one surface 11 a of the diamond substrate 11 and serves as an interface 27 between the group III nitride semiconductor layer 22 and the diamond substrate 11. As a result, a hole conduction channel region 26 is formed in a region near the interface 27 between the diamond substrate 11 and the group III nitride semiconductor layer 22.

The field effect transistors 10 and 20 according to the embodiment of the present invention include a diamond substrate 11, a second electrode 13 and a third electrode 14 formed on the one surface 11 a side of the diamond substrate 11, and two electrodes. A field effect transistor having a first electrode 15 formed between the first electrode 15 and the diamond substrate 11, and a group III nitride semiconductor layer 12, 22 between the first electrode 15 and the diamond substrate 11. And the hole conduction channel regions 16 and 26 are formed in the vicinity of the interfaces 17 and 27 between the diamond substrate 11 and the group III nitride semiconductor layers 12 and 22, so that the holes are operated as carriers. Since the hole conduction channel region exists under the group III nitride semiconductor layer, the channel is automatically protected and has excellent operational stability, stable and high frequency. And large current and high breakdown voltage and operable, high reproducibility of the transistor characteristics can be a large field-effect transistor of the power at a high speed. In particular, a group III nitride semiconductor layer such as a group III nitride semiconductor thin film grown on a diamond single crystal substrate has a crystallographic structure including a high concentration of dislocations and grain boundaries, and residual strain in the thin film Can be almost alleviated and the reproducibility of transistor characteristics can be improved. As described above, stable, high-frequency, large current, and high withstand voltage operations are possible, transistor characteristics are highly reproducible, and a high-speed and high-power field effect transistor can be obtained.

In the field effect transistors 10 and 20 according to the embodiment of the present invention, since the hole conduction channel regions 16 and 26 are provided in the diamond substrate 11, the holes are operated as carriers and the channels are dynamically formed. It is protected, has excellent operational stability, is capable of stable, high frequency, large current, and high breakdown voltage operation, has high reproducibility of transistor characteristics, and can be a field effect transistor with high speed and high power.

The field effect transistors 10 and 20 according to the embodiment of the present invention have a configuration in which a group III nitride semiconductor layer 12 is provided between the second electrode 13 and / or the third electrode 14 and the diamond substrate 11. It operates with holes as carriers, the channel is dynamically protected, has excellent operational stability, is capable of stable, high frequency, large current, and high withstand voltage operation, has high reproducibility of transistor characteristics, and has high power at high speed. A large field effect transistor can be obtained.

In the field effect transistors 10 and 20 according to the embodiment of the present invention, the layer thickness t _{2 of the} group III nitride semiconductor layer 12 between the second electrode 13 and / or the third electrode 14 and the diamond substrate 11 is The structure is thinner than the layer thickness t _{1 of the} group III nitride semiconductor layer 12 between the first electrode 15 and the diamond substrate 11, so that the holes are operated as carriers, the channel is dynamically protected, and the operation stability is improved. It is excellent in stability, high frequency, large current, high withstand voltage operation, high reproducibility of transistor characteristics, high speed and high power field effect transistor.

In the field effect transistors 10 and 20 according to the embodiment of the present invention, the first electrode 15 is a gate electrode, the second electrode 13 is a source electrode, and the third electrode 14 is a drain electrode. Operates with holes as carriers, the channel is dynamically protected, excellent in operational stability, stable, high frequency, large current, and high withstand voltage operation, high reproducibility of transistor characteristics, high speed and high power It can be a field effect transistor.

In the field effect transistors 10 and 20 according to the embodiment of the present invention, the group III nitride semiconductor layers 12 and 22 are made of a polycrystal having hexagonal crystal grains, so that the diamond substrate 11 and the group III nitride semiconductor layer 12 are formed. Hole conduction channel regions 16 and 26 can be formed in the vicinity of the interfaces 17 and 27, and the layer structure of the group III nitride semiconductor layers 12 and 22 is stabilized, and the transistor characteristics are highly reproducible. It can be a transistor.

In the field effect transistors 10 and 20 according to the embodiment of the present invention, the group III nitride semiconductor layers 12 and 22 are composed of any one compound selected from the group consisting of AlN, BN, GaN, and InN. A field effect transistor that operates as a carrier, has a dynamically protected channel, has excellent operational stability, is capable of stable, high-frequency, large-current, and high-voltage operation, has high reproducibility of transistor characteristics, and high power at high speed It can be.

In the field effect transistors 10 and 20 according to the embodiment of the present invention, the diamond substrate 11 is a single crystal substrate, and one surface 11a thereof is parallel to the (111) crystal plane. The hole conduction channel regions 16 and 26 can be formed in the vicinity of the interfaces 17 and 27 with the layers 12 and 22, and the layer structure of the group III nitride semiconductor layers 12 and 22 is stabilized, so that the transistor characteristics are highly reproducible. It can be a field effect transistor.

Since the field effect transistors 10 and 20 according to the embodiment of the present invention have a structure in which one surface of the diamond substrate 11 is oxygen-modified, the vicinity of the interfaces 17 and 27 between the diamond substrate 11 and the group III nitride semiconductor layers 12 and 22. The hole conduction channel regions 16 and 26 can be easily formed in the region, can operate using holes as carriers, and can be a field effect transistor with high reproducibility of transistor characteristics.

The method of manufacturing the field effect transistors 10 and 20 according to the embodiment of the present invention includes a step of heat-treating the diamond substrate 11 in a hydrogen / ammonia atmosphere under a reduced pressure and a high temperature condition of 800 ° C. or more, and a reduced pressure by a MOVPE method. A step of forming group III nitride semiconductor layers 12 and 22 on one surface 11a of diamond substrate 11 under a high temperature condition of 1200 ° C. or higher; a step of partially removing group III nitride semiconductor layers 11 and 22; Forming the second electrode 13 and the third electrode 14 on the one surface 11a side of the diamond substrate 11, and forming the first electrode 15 on the one surface 12a, 22a of the group III nitride semiconductor layers 12, 22. Therefore, it is easy to produce a low-resistance ohmic electrode for the hole channel in diamond, Easily manufacture field effect transistors with high power at high speed, with high reproducibility of transistor characteristics, capable of stable, high frequency, large current, and high voltage operation with no need for doping. can do.

In the manufacturing method of the field effect transistors 10 and 20 according to the embodiment of the present invention, the film formation conditions of the MOVPE method are such that trimethylaluminum gas, ammonia gas, and hydrogen gas are circulated in a container in which the diamond substrate 11 is disposed. In this state, the diamond substrate 11 is heated to a temperature of 1200 ° C. to 2000 ° C. while reducing the pressure to 1 to 760 Torr. Therefore, the region near the interfaces 17 and 27 between the diamond substrate 11 and the group III nitride semiconductor layers 12 and 22 In addition, the hole conduction channel regions 16 and 26 can be easily formed.

Since the manufacturing method of the field effect transistors 10 and 20 according to the embodiment of the present invention is configured to form the first electrode 15, the second electrode 13, and the third electrode 14 by vapor deposition and / or sputtering, A field effect transistor having hole conduction channel regions 16 and 26 in the vicinity of the interfaces 17 and 27 between the diamond substrate 11 and the group III nitride semiconductor layers 12 and 22 can be easily manufactured.

Since the method for manufacturing the field effect transistors 10 and 20 according to the embodiment of the present invention has a configuration in which the one surface 11a of the diamond substrate 11 is subjected to an acid solution treatment or heat treatment before the group III nitride semiconductor layers 12 and 22 are formed. Hole conduction channel regions 16 and 26 can be easily formed in the vicinity of the interfaces 17 and 27 between the substrate 11 and the group III nitride semiconductor layers 12 and 22.

Since the method of manufacturing the field effect transistors 10 and 20 according to the embodiment of the present invention is configured to partially remove the group III nitride semiconductor layers 12 and 22 by lithography, the second electrode 13 and the third electrode The hole conduction channel region 16, 26 can be easily formed in the vicinity of the interface 17, 27 between the diamond substrate 11 and the group III nitride semiconductor layers 12, 22. Can be easily formed.

Method for manufacturing a field effect transistor 10 which is an embodiment of the invention, a group III nitride semiconductor layer 12 is partially removed, the two stages that thinner thickness t ₂ of the group III nitride semiconductor layer 12 Since the portions 12e and 12f are formed, the flow of current due to the movement of holes between the second electrode 13 and the third electrode 14 can be facilitated, and the diamond substrate 11 and the group III nitride semiconductor layer 12 Thus, the hole conduction channel region 16 can be easily formed in the region near the interface 17.

The manufacturing method of the field effect transistor 20 according to the embodiment of the present invention has a configuration in which the group III nitride semiconductor layer 22 is partially removed to form two removal portions from which the group III nitride semiconductor layer 22 is removed. The current flow due to the movement of holes between the second electrode 13 and the third electrode 14 can be facilitated, and holes are formed in the vicinity of the interface 27 between the diamond substrate 11 and the group III nitride semiconductor layer 22. The conductive channel region 26 can be easily formed.

The field effect transistor and the manufacturing method thereof according to the embodiment of the present invention are not limited to the above embodiment, and can be implemented with various modifications within the scope of the technical idea of the present invention. Specific examples of this embodiment are shown in the following examples. However, the present invention is not limited to these examples.

Example 1
<Production of heterojunction structure>
First, a type IIa insulating (111) oriented diamond substrate is boiled in a mixed solution of nitric acid and sodium chlorate (NaClO ₃ ) for 1 hour, and then boiled in a mixed solution of nitric acid and hydrofluoric acid for 1 hour. Processed.
Next, it was carried into a metal organic vapor phase epitaxy apparatus (MOVPE apparatus) and annealed (heat treatment) for 5 minutes under a condition of 100 Torr and 1250 ° C. in a mixed atmosphere of hydrogen and ammonia.
Next, as it is, in the MOVPE apparatus, aluminum nitride is deposited on one surface of the diamond substrate by a metal organic vapor phase epitaxy method (MOVPE method) under the growth conditions shown in Table 1 so that the layer thickness becomes 1.6 μm. Grown up. Although the conventional MOVPE apparatus has a growth temperature of about 1000 ° C., the apparatus of this embodiment has been improved so that it can be heated to 1250 ° C. or higher.
Note that NH ₃ was continuously supplied until the growth temperature dropped to 600 ° C. or less even after the aluminum nitride growth.

Through the above steps, a heterojunction structure (Example 1) composed of a diamond substrate and a group III nitride semiconductor layer (AlN) was formed.

<Crystallographic Evaluation of Heterojunction Structure of Example 1>
Next, crystallographic evaluation of the heterojunction structure of Example 1 was performed.
First, the aluminum nitride grown to 1.6 μm of the heterojunction structure of Example 1 was evaluated by the X-ray diffraction method.
FIG. 5 is a graph showing the 2θ-ω scan profile result of the AlN X-ray diffraction method of the heterojunction structure of Example 1. FIG. 5A is a graph showing the result of 2θ-ω scanning when 2θ is measured in the range of 30 ° to 90 °, which is a wide range, centering on diamond (111), and FIG. FIG. 5C is a graph showing the result of measuring 2θ in detail centering on (10-11) of AlN. FIG. 5C is a graph showing the result of measuring 2θ in detail centering on (0002) of AlN. .

From the peak of the (0002) plane of AlN in FIGS. 5 (a) and 5 (b), it was confirmed that the (0001) plane of aluminum nitride, that is, the c axis was oriented to the (111) plane of diamond. .
5B and 5C, the lattice constant of aluminum nitride was determined by the diffraction angle 2θ and Bragg's law. The c-axis lattice constant (c _AlN ) was 4.978 は, and the a-axis lattice constant (a _AlN ) Was 3.115cm.

6 shows a cross-sectional transmission electron microscope image (FIG. 5A) and a transmission electron diffraction pattern (FIG. 6B, FIG. 6) in the vicinity of the aluminum nitride and diamond interface (hetero interface) of the heterojunction structure of Example 1. 6 (c)).
As shown in FIG. 6 (a), the aluminum nitride of the heterojunction structure of Example 1 has a high density of defects (dislocations and crystal grain boundaries) and is relaxed, and is not a continuous film but a column (grain). It can be seen that the structure is very similar to the structure.
Further, from the transmission electron diffraction patterns shown in FIGS. 6B and 6C, it can be seen that aluminum nitride has two domain structures.
It can also be seen that (0001) aluminum nitride and (111) diamond are parallel in the orientation relationship. Further, it can be seen that (1-100) aluminum nitride and (11-20) aluminum nitride and (0-22) diamond are parallel.

<Fabrication of field effect transistor>
Next, the aluminum nitride of the heterojunction structure of Example 1 was patterned to form an element isolation structure in which a plurality of elements were isolated on a diamond substrate.
Note that patterning was performed using a photolithography method, AlN was etched using an inductively coupled plasma etching apparatus, and chlorine Cl ₂ was used as an etching gas. Further, during the etching, the aluminum nitride below the pattern formed by the photoresist was left, and the aluminum nitride other than the pattern was completely etched and removed.

Next, in order to lower the contact resistance of the source-drain (SD) electrode, aluminum nitride disposed immediately below the metal used for the source-drain (SD) electrode is formed by photolithography and induction in the same manner as described above. The film was thinned using a coupled plasma etching apparatus.
Thereby, a convex structure was formed.

Next, using electron beam evaporation, titanium (25 nm), aluminum (100 nm), titanium (50 nm), and gold (250 nm) are deposited in this order and film thickness on the thinned aluminum nitride, A four-layer structure was formed (hereinafter sometimes referred to as Ti (25 nm) / Al (100 nm) / Ti (50 nm) / Au (250 nm)).
Next, after applying a photoresist, the photoresist was patterned into the shape of a source electrode and a drain electrode by photolithography, and then the four-layer structure was patterned by lift-off.
Note that a plurality of square source and drain electrodes were formed on one diamond substrate. The square source electrode and drain electrode were 150 μm square.
Next, the metal of the four-layer structure was heat-treated at 900 ° C. for 1 min to form a source electrode and a drain electrode.

Next, using electron beam evaporation, nickel (200 nm) and gold (200 nm) were deposited in this order and film thickness on the thinned aluminum nitride to form a two-layer structure (hereinafter, referred to as “the two-layer structure”). Ni (200 nm) / Au (200 nm) may be indicated).
Next, after applying a photoresist, the photoresist was patterned into the shape of a gate electrode by photolithography, and then the two-layer structure was patterned by lift-off.
Between the pair of source and drain electrodes, the gate electrode length (gate length) Lg is 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, and the gate electrode width (gate width) Wg is 160 μm. Was made. Each gate has a square terminal on one end. The length of one side of the square terminal portion was 150 μm.
Next, the two-layer structure was heat-treated at 900 ° C. for 1 min to form a gate electrode.

Through the above-described steps, a diamond substrate (Example 1) having a plurality of field effect transistor elements each including a source electrode and a drain electrode and having a gate electrode length Lg of 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, and 60 μm, respectively. Formed.

<Evaluation of Field Effect Transistor Characteristics of Example 1>
The device characteristic evaluation results of the field effect transistor of Example 1 are described below.
7 is a surface optical microscopic image (a), (b) and a schematic cross-sectional view (c) of the field effect transistor of Example 1. FIG. Fig.7 (a) is a top view, FIG.7 (b) is an enlarged view, FIG.7 (c) is a cross-sectional schematic diagram. The numerical value shown in FIG. 7A is the size of the gate length of each transistor.

As shown in FIG. 7A, two square source / drain electrodes are arranged side by side on a diamond substrate (Example 1) having a plurality of field effect transistor elements.
As shown in FIGS. 7A and 7B, the length of one side of the square source electrode and drain electrode is 160 μm.
Further, the width Wg of the gate electrode of each field effect transistor is 160 μm, and the length Lg of the gate electrode is 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, and 60 μm. A square terminal portion is formed on one end side of each gate electrode.
Further, as shown in FIG. 7C, the gate electrode is formed on the convex structure AlN.

FIG. 8 shows a measurement arrangement for evaluating transistor characteristics of the field effect transistor of the present invention. With this measurement arrangement, the transistor characteristics of each field effect transistor on a diamond substrate (Example 1) having a plurality of field effect transistor elements were evaluated. This arrangement is an arrangement used for general p-channel measurement with the source (S) as the ground.

FIG. 9 is a graph showing the current-voltage characteristics of a field effect transistor having a gate width (Wg) of 160 μm and a gate length (Lg) of 30 μm. FIG. 9A shows the drain current (Id) −drain voltage (Vd). FIG. 9B is a graph showing the gate voltage dependency (a graph showing the Id-Vd characteristic), and FIG. 9B is a graph showing the gate voltage dependency of the gate current (Ig) −the drain voltage (Vd) (the Ig-Vd characteristic is shown). Graph). The gate voltage Vg was changed from 1V to -5V at 1V intervals, and Ig-Vd characteristics were measured.
The drain current (Id) is normalized by the gate width (Wg). The gate current (Ig) is a gate leakage current.

As shown in FIG. 9A, the drain current (Id) is controlled by the gate voltage (Vg). Furthermore, a pinch-off state can also be confirmed.
Further, since a negative drain current (Id) is obtained with respect to the negative drain voltage (Vd), it can be seen that the carriers are holes.
Furthermore, as shown in FIGS. 9A and 9B, the drain current (Id) is sufficiently larger than the gate leakage current (Ig).
From the results shown in FIG. 9, the maximum drain current (Id _max ) and the maximum transconductance (gm _max ) can be calculated, and Id _max = 6.8 mA / mm and gm _max = 2.9 mS / mm, respectively.

FIG. 10 is a graph showing capacitance-voltage characteristics (C-Vg characteristics) between a source electrode and a gate electrode of a field effect transistor having a gate width (Wg) of 160 μm and a gate length (Lg) of 30 μm.
As shown in FIG. 10, the spread of the depletion layer can be confirmed in the vicinity of Vg = 7 to 10V.
In the vicinity of Vg = −3 to 7V, the electrostatic capacity (depletion layer) due to the accumulation of carriers is constant (C = 6.8 × 10 ⁻¹³ F).
Furthermore, in the vicinity of Vg = −10 to −3 V, the gate leakage current (Ig) increased with the increase in carriers, and the capacitance decreased.

Next, after plotting the square root-gate voltage characteristics (Id ^1/2 -Vg characteristics) of the drain current and performing a linear fit, the gate voltage (Vg) was -2V and high linearity was shown.
Therefore, the effective mobility (μ) and the threshold voltage (Vt) at that time were calculated using the capacitance C = 6.8 × 10 ⁻¹³ F.
As a result, when Vd = −5 V, the effective mobility (μ) and threshold voltage (Vt) were estimated to be μ = 316 cm ² / Vs and Vt = 3 V, respectively. Further, when Vd was −5 V and Vg was −5 V, the mutual conductance (gm) was 3 mS / mm.
In a field effect transistor having a gate width (Wg) of 160 μm and a gate length (Lg) of 30 μm, when Vd = −5 V and Vg = −5 V are applied, drain current Id ≧ 6.8 mA / mm, effective mobility μ ≧ 300 cm ² / Vs and mutual conductance gm ≧ 2.5 mS / mm were obtained, and the high speed and high power were evaluated. Furthermore, the operation stability with respect to the measurement environment was also excellent.

Next, the carrier density Q / q was estimated from the capacitance-voltage characteristics based on the threshold voltage (Vt) value obtained from the square root of the drain current-gate voltage characteristics (Id ^1/2 -Vg characteristics). . As a result, when Abs (Vg) + Vt = 4V, Q / q = 3.9 × 10 ¹¹ cm ⁻² and the channel resistance R (ON resistance) was R = 4.55 kΩ.

Next, from the results of CV measurement, assuming that the channel carrier density distribution is distributed in diamond, the hole concentration p in the depth direction was calculated using the relative dielectric constant of diamond.

FIG. 11 is a graph showing the value of the hole concentration p with respect to the depth from the interface of the field effect transistor. This result suggests that holes are distributed two-dimensionally. Further, from the half width of the peak, this channel width is considered to be 1 nm or less.

From the above results, the change of the band structure with respect to the gate voltage of the field effect transistor was considered.
12A shows a band structure in a depletion state of the field effect transistor of the present invention, FIG. 12B shows a band structure in a flat band state, and FIG. 12C shows a band structure in a hole accumulation state. It is.
As shown in FIG. 12A, when Vg> Vt, the diamond-aluminum nitride interface is depleted.
Further, a flat band is formed at Vg = Vt. Furthermore, it was considered that hole carrier accumulation occurs when Vg <Vt.

(Example 2)
After the growth of AlN, a diamond substrate having a plurality of field effect transistor elements (Example 2) was formed in the same manner as in Example 1 except that hydrogen annealing treatment (heat treatment) was performed under the same conditions as the growth conditions.
The transistor characteristics were measured by the same method as in Example 1, and the presence or absence of carriers was investigated. As the current was below the detection limit of the device, it was confirmed that deposition of AlN was responsible for carrier generation. It was a result to prove.

From these results, significant improvements can be expected by optimizing the film thickness, film quality, and device scale of aluminum nitride, and there is sufficient potential for realizing high-speed, power field-effect transistors capable of high-frequency, large-current, and high-voltage operation. It is what you have.

The field effect transistor and the manufacturing method thereof according to the present invention relate to a field effect transistor having high reproducibility of transistor characteristics, high speed and high power, and a manufacturing method thereof, and may be used in the field effect transistor manufacturing industry and the like. .

DESCRIPTION OF SYMBOLS 10 ... Field effect transistor, 11 ... Diamond substrate, 11a ... One side, 12 ... Group III nitride semiconductor layer, 12a ... One side, 12b ... Other side, 12c ... One side, 12d ... Projection part, 12e, 12f ... Step part, 13 ... Second electrode, 14 ... Third electrode, 15 ... First electrode, 16 ... Hole conduction channel region, 17 ... Interface, 20 ... Field effect transistor, 22 ... Group III nitride semiconductor layer, 22a ... One side 22b ... the other side, 26 ... the hole conduction channel region, 27 ... the interface.

Claims (16)

An electric field having a diamond substrate, a second electrode and a third electrode formed separately on one surface side of the diamond substrate, and a first electrode formed separately between the two electrodes An effect transistor,
A group III nitride semiconductor layer is provided between the first electrode and the diamond substrate, and a hole conduction channel region is formed in the vicinity of the interface between the diamond substrate and the group III nitride semiconductor layer. A field effect transistor characterized by comprising: The field effect transistor according to claim 1, wherein the hole conduction channel region is provided in the diamond substrate. 3. The field effect transistor according to claim 1, wherein a group III nitride semiconductor layer is provided between the second electrode and / or the third electrode and the diamond substrate. . The group III nitride semiconductor layer between the second electrode and / or the third electrode and the diamond substrate has a layer thickness of the group III nitride semiconductor between the first electrode and the diamond substrate. The field effect transistor according to claim 3, wherein the field effect transistor is thinner than a layer thickness. 5. The device according to claim 1, wherein the first electrode is a gate electrode, the second electrode is a source electrode, and the third electrode is a drain electrode. 6. Field effect transistor.   The field effect transistor according to claim 1, wherein the group III nitride semiconductor layer is made of a polycrystalline body having hexagonal crystal grains.   The field effect transistor according to claim 6, wherein the group III nitride semiconductor layer is made of any one compound selected from the group consisting of AlN, BN, GaN, and InN.   The field effect transistor according to claim 1, wherein the diamond substrate is a single crystal substrate, and one surface thereof is parallel to a (111) crystal surface.   9. The field effect transistor according to claim 8, wherein one surface of the diamond substrate is oxygen-modified. A step of heat-treating the diamond substrate in a hydrogen / ammonia atmosphere under reduced pressure and at a high temperature of 800 ° C. or higher;
Forming a group III nitride semiconductor layer on one surface of the diamond substrate under reduced pressure and at a high temperature of 1200 ° C. or higher by a MOVPE method;
Partially removing the group III nitride semiconductor layer;
Forming a second electrode and a third electrode on one surface of the diamond substrate, and forming a first electrode on one surface of the group III nitride semiconductor layer. Manufacturing method.   The film formation condition of the MOVPE method is that the diamond substrate is 1200 ° C. to 760 ° C. while reducing the pressure to 1 to 760 Torr in a state where trimethylaluminum gas, ammonia gas and hydrogen gas are circulated in a container in which the diamond substrate is disposed. The method of manufacturing a field effect transistor according to claim 10, wherein the field effect transistor is heated to a temperature of 2000 ° C.   12. The method of manufacturing a field effect transistor according to claim 10, wherein the first electrode, the second electrode, and the third electrode are formed by vapor deposition and / or sputtering. . 13. The method of manufacturing a field effect transistor according to claim 10, wherein one surface of the diamond substrate is subjected to an acid solution treatment or a heat treatment before forming the group III nitride semiconductor layer. The method for manufacturing a field effect transistor according to claim 10, wherein the group III nitride semiconductor layer is partially removed by a lithography method. 15. The field effect transistor according to claim 14, wherein the group III nitride semiconductor layer is partially removed to form two step portions in which the layer thickness of the group III nitride semiconductor layer is thinner. Manufacturing method. 15. The method of manufacturing a field effect transistor according to claim 14, wherein the group III nitride semiconductor layer is partially removed to form two removal portions from which the group III nitride semiconductor layer is removed.