JP2012074575A - Semiconductor package substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package substrate capable of coping with densification and in which a solder bump having a volume and a height required for connection can be formed at a predetermined position in a longitudinal direction of a connection terminal by providing a convex shape at a part of the longitudinal-shaped connection terminal for connecting with a semiconductor element.SOLUTION: A semiconductor package substrate has a plurality of longitudinal-shaped connection terminals for connecting with a semiconductor element. These connection terminals are aligned in a lateral direction. A convex shape is formed in a part in the longitudinal direction of the connection terminals. The convex shape may be formed at a predetermined position in the longitudinal direction of the connection terminals aligned in the lateral direction. A length of the convex shape in the longitudinal direction of the connection terminals is one-fifth to one-third of a length of the connection terminal.

Description

  The present invention relates to a semiconductor package substrate, and in particular, it is possible to improve connection reliability by stably forming solder bumps provided on connection terminals for mounting semiconductor elements at predetermined positions. The present invention relates to a semiconductor package substrate.

  Conventionally, in order to connect semiconductor elements using a semiconductor package substrate, solder bumps are formed on the connection terminal side of the semiconductor package substrate, gold bumps or the like are formed on the semiconductor element side, and both are pressure-bonded. Is added to melt the solder bumps. At that time, it is necessary to match the position of the top of the solder bump formed on the connection terminal with the position of the gold bump or the like on the semiconductor element side. Further, this solder bump needs a certain volume and height in order to be stably connected to a gold bump or the like on the semiconductor element side.

  The solder bumps may be formed on the connection terminals whose surfaces remain copper, but usually, Ni / Au plating is performed on the surfaces of the connection terminals formed on the semiconductor package substrate. Often performed on plated connection terminals. Specifically, a solder paste containing flux is printed on the surface of the connection terminal, heated and melted through a reflow furnace, and then the unnecessary flux is removed by washing with a chemical solution on the surface of the connection terminal. Form solder bumps.

  When the solder paste melts on the surface of the connection terminal, the solder tends to be rounded by the surface tension of the solder itself. At that time, on each of the plurality of connection terminals arranged in the short direction, there is no problem if the solder is agglomerated and rounded at a predetermined position with respect to the longitudinal direction of the connection terminal, and solidifies to form a solder bump. Has a problem that it is difficult to control the position at which the solder bumps are formed, since it aggregates at various positions. If solder bumps are not formed at predetermined locations, when mounting a semiconductor element, the bump position on the semiconductor element side may not match the position of the solder bump on the semiconductor package substrate side, which may cause a bonding failure.

  As a method for solving this problem, a method is disclosed in which part of the connection terminal is thickened to the plane side (Patent Document 1). In this method, the width of a part of the connection terminal in the longitudinal direction is thickened on both sides in the width direction so that the amount of solder paste transferred to the part by printing or the like is increased. According to this, the melted solder at a location that has been transferred a lot during reflow attracts the other portion of the solder due to surface tension, so that a large solder bump can be formed at a predetermined location.

  Similarly, a method of increasing the width of a part of the connection terminal in the longitudinal direction to one side in the width direction is also disclosed (Patent Document 2). Similarly to Patent Document 1, since the transfer amount of the solder paste to the thickened portion increases, the melted solder in the portion that has been transferred a lot during reflow attracts the other portion of the solder due to the surface tension. Large solder bumps can be formed at predetermined locations.

JP 2002-329744 A Japanese Patent Laid-Open No. 2005-11902

  However, in the method of Patent Document 1, since a portion where the connection terminal is thickened is provided in a part of the connection terminal in the longitudinal direction, the gap between adjacent connection terminals is partially narrowed in the portion where the connection terminal is thickened. . For this reason, as the arrangement of the connection terminals becomes narrower, etching residue is generated during circuit processing, or electroless Ni / Au plating is deposited in the gaps of the connection terminals during surface treatment such as electroless Ni / Au plating. Since the arrangement pitch of the connection terminals cannot be made too narrow, there is a problem that hinders high density. In the method of Patent Document 2, since the width of a part of the connection terminal in the longitudinal direction is thickened only to one side in the width direction, the restriction on the gap of the connection terminal is relaxed compared to Patent Document 1, but the connection terminal As the arrangement becomes narrower, there is still a problem similar to that of Patent Document 1. As described above, in the prior art, in order to form a solder bump having a volume and a height necessary for connection at a predetermined location on the connection terminal, the arrangement pitch of the connection terminal is restricted and the density is increased. It was difficult to respond to

  The present invention has been made in view of the above-described problems, can cope with high density, and can form solder bumps having a volume and height necessary for connection at predetermined positions in the longitudinal direction of the connection terminals. An object of the present invention is to provide a simple semiconductor package substrate.

In order to solve the above problems, the present invention has the following configuration.
(1) It has a plurality of long connection terminals for connecting semiconductor elements, these connection terminals are formed side by side in the short direction, and a convex shape is formed on a part of the plurality of connection terminals. A semiconductor package substrate characterized by the above.
(2) The semiconductor package substrate according to (1), wherein the convex shape is formed at a predetermined position in the longitudinal direction of a plurality of connection terminals formed side by side in the lateral direction.
(3) In the above (1) or (2), the length of the convex shape in the longitudinal direction of the connection terminal is 1/5 to 1/3 of the length of the connection terminal. Semiconductor package substrate.
(4) In any one of the above (1) to (3), the length of the connection terminal is defined by the opening width of the solder resist formed so as to cover both sides or one side of the connection terminal in the longitudinal direction. A featured semiconductor package substrate.
(5) In any one of the above (1) to (4), by supplying solder on the connection terminal having a convex shape, a solder bump is formed at a predetermined position in the longitudinal direction on the connection terminal. A semiconductor package substrate.

  According to the present invention, it is possible to provide a semiconductor package substrate capable of forming a solder bump having a volume and a height necessary for connection at a predetermined position in a longitudinal direction of a connection terminal, which can cope with high density. Can do.

It is a top view of the semiconductor package board | substrate of the Example of this invention. It is A-A 'sectional drawing in FIG. 1 of the semiconductor package board | substrate of the Example of this invention. It is a top view when forming a solder bump using the semiconductor package substrate of the example of the present invention. FIG. 4 is a cross-sectional view taken along the line A-A ′ in FIG. 3 of the semiconductor package substrate of the embodiment of the present invention. It is a top view of the conventional semiconductor package substrate (comparative example). FIG. 6 is a cross-sectional view taken along the line A-A ′ of FIG. 5 of a conventional (comparative example) semiconductor package substrate. It is a top view when forming a solder bump using a conventional semiconductor package substrate (comparative example).

  The structure of the semiconductor package substrate of the present invention will be described using the examples shown in FIGS.

  As shown in FIGS. 1 to 4, the semiconductor package substrate 6 of the present invention has a plurality of longitudinal connection terminals 7 for connecting semiconductor elements, and the plurality of connection terminals 7 are arranged in the short direction. The convex shape 2 is formed on a part of the plurality of connection terminals 7 in the longitudinal direction.

  The semiconductor package substrate 6 of the present invention refers to a wiring substrate having connection terminals 7 for directly mounting a semiconductor element (not shown) as a semiconductor element. The connection terminal 7 of the present invention refers to a portion of the wiring pattern 1 provided on the semiconductor package substrate 6 for electrical connection with a semiconductor element.

  The semiconductor package substrate 6 of the present invention can be formed by a material / manufacturing method used for a general semiconductor package substrate 6. For example, first, an epoxy resin-based or polyimide resin-based substrate 4 is prepared, a circuit process is performed on the copper foil or copper plating formed on the surface by a subtracting method, and the wiring pattern 1 including the connection terminals 7 is formed. Form. As the base material 4, a multilayer substrate (not shown) having an inner layer pattern of the required number of layers may be used.

  Next, the convex shape 2 having a height higher than at least the other part of the connection terminal 7 is formed on a part of the connection terminal 7. This convex shape 2 is produced by forming a part of the connection terminal 7 after the wiring pattern 1 is formed, or by forming a plating pattern 2 on the connection terminal 7 after forming the wiring pattern 1. After protecting only the portion to be formed with an etching resist or the like, the entire connecting terminal 7 except for the portion to be the convex shape 2 may be formed by etching to be thin.

  Next, a solder resist 3 is formed. The solder resist 3 is formed so as to cover both sides or one side of the connection terminal 7 in the longitudinal direction. That is, the length of the connection terminal 7 is defined by the opening width 8 of the solder resist 3. As the solder resist 3, either a liquid type or a film type can be used. Although either a photosensitive type or a printing type can be used, a photosensitive type solder resist is desirable in that the dimensional accuracy of the opening width 8 of the solder resist 3 is excellent.

  FIG. 1 is a plan view of a semiconductor package substrate according to the present invention, and FIG. 2 is a cross-sectional structure of a portion indicated by A-A ′ in FIG. 1. The convex shape 2 is formed at a predetermined position in the longitudinal direction of the plurality of connection terminals 7 formed side by side in the lateral direction. Here, the predetermined position in the longitudinal direction means that the plurality of connection terminals 7 arranged in the short direction of the connection terminal 7 have the same position in the length direction of the connection terminal 7. Due to the influence of the convex shape 2, the solder paste becomes thick in the vicinity of the convex shape 2 and the amount of the solder paste is large. Therefore, a large solder bump 5 can be formed at the position of the convex shape 2 as shown in FIG. That is, the convex shape 2 is a trigger for attracting other portions of the solder 11, and the solder 11 aggregates around the convex shape 2. Therefore, by providing the convex shape 2 at a predetermined position in the longitudinal direction of the connection terminal 7. The solder bumps 5 can be formed at predetermined positions in the longitudinal direction of the connection terminals 7.

  The convex shape 2 has a structure higher than at least the connection terminal 7 in the other part, and the height is preferably about 1 to 10 μm from the surface of the connection terminal 7 to the top of the convex shape 2. 3-5 micrometers is especially preferable. If the height of the convex shape 2 is less than 1 μm, the amount of solder paste in the vicinity of the convex shape 2 is not much different from that of other portions, so that the effect of triggering the solder 11 in other portions is weak. On the other hand, if the height of the convex shape 2 exceeds 10 μm, the height of the solder bump 5 may greatly exceed the height of the solder resist 3, which may cause contact damage.

  The length of the convex shape 2 in the longitudinal direction of the connection terminal 7 is desirably 1/5 to 1/3 of the length of the connection terminal 7. If the length of the convex shape 2 is larger than 1/3 of the length in the longitudinal direction of the connection terminal 7, the movement of the molten solder on the convex shape 2 becomes large, and as a result, the position of the solder bump 5 is stable. No longer. On the other hand, if it is smaller than 1/5, the amount of the solder 11 that aggregates on the convex shape 2 is small, the action that attracts the solder 11 in other parts is weak, and the volume and height of the solder bump 5 cannot be secured.

  FIG. 3 shows a state in which solder bumps 5 for connection to semiconductor elements are formed on the semiconductor package substrate 6 of FIGS. 1 and 2 of the present invention. FIG. 4 is a cross-sectional view of a portion indicated by A-A ′ in FIG. 3. By supplying a solder paste onto the connection terminal 7 on which the convex shape 2 is formed, the solder bump 5 is formed at a predetermined position in the longitudinal direction on the connection terminal 7. That is, the solder bumps 5 are formed by aggregating the connection terminals 7 and the convex shape 2 in FIG. Since the solder bump 5 is provided with the convex shape 2 on the connection terminal 7 so that the solder 11 easily gathers in this portion, the height and volume can be stably secured, and the solder bump 5 can be stably provided at a predetermined position. Can be formed. As a result, it becomes possible to form the solder bumps 5 for flip chip connection having a stable height and volume at a stable position by the convex shape 2.

  The solder bumps 5 are formed by applying a solder paste containing flux on the connection terminals 7 and then passing the semiconductor package substrate 6 through a reflow furnace and melting the applied solder paste. After reflow, since flux is deposited around the solder bumps 5, chemical treatment is performed by a flux cleaning machine to remove the flux.

  EXAMPLES Hereinafter, although an Example demonstrates this invention, this invention is not limited to this.

(Example)
An embodiment of the present invention will be described with reference to FIGS. First, MCL-E-679FG (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a double-sided copper-clad laminate using an epoxy-based insulating resin, is prepared as the base material 4, and the surface copper foil (thickness: 18 μm) ) Was processed by the subtract method to form the wiring pattern 1 including the connection terminals 7. At this time, the thickness of the wiring pattern 1 including the formed connection terminal 7 was 18 μm and the width was 20 μm.

  Next, as shown in FIG. 1 and FIG. 2, only the portion of the connection terminal 7 that becomes the convex shape 2 is covered with an etching resist, and then the surrounding connection is made except for the portion that becomes the convex shape 2 by etching. The wiring pattern including the entire terminal 7 was made thin. At this time, the height of the convex shape 2 with respect to the surface of the surrounding connection terminal 7 is 3 μm to 5 μm, and the length is 20 μm to 33 μm (1/3 to 1/5 of the length of the connection terminal 7). Equivalent).

  Next, as shown in FIGS. 1 and 2, the solder resist 3 was formed so as to cover both sides of the connection terminal 7 in the longitudinal direction. That is, the length of the connection terminal 7 is defined by the opening width 8 (100 μm) of the solder resist 3 and the length is 100 μm.

  Thereafter, as shown in FIGS. 1 and 2, electroless Ni / Au plating was performed on the connection terminals 7 exposed from the solder resist 3 including the convex shape 2. The thickness of the solder resist 3 was 15 μm on the connection terminal 7, the thickness of the electroless Ni plating was 3 μm, and the thickness of the Au plating was 0.05 μm.

  As shown in FIGS. 3 and 4, a solder paste was applied to the connection terminals 7 including the convex shape 2 of the semiconductor package substrate 6 subjected to the electroless Ni / Au plating by a printing method. Subsequently, the solder paste was melted using reflow, and the flux was removed with a flux washer. The formed solder bump 5 could be formed at the position of the convex shape 2 of the connection terminal 7 exposed from the opening 9 of the solder resist 3. Moreover, the height of the solder bump 5 was able to ensure a height of about 10 μm with respect to the height of the solder 11 other than the convex shape 2.

(Comparative example)
A comparative example will be described with reference to FIGS. FIG. 5 is a plan view, and FIG. 6 is a cross-sectional view taken along line AA ′ of FIG. In the comparative example, the convex shape 2 was not provided on the connection terminal 7. Other than that is the same as the embodiment.

  Similarly to the example, a solder paste was applied on the connection terminals 7 to the semiconductor package substrate 6 of FIGS. Subsequently, reflow was performed, the solder paste was melted, flux cleaning was performed, the flux was removed, and solder bumps 5 were formed as shown in FIG. As a result of observation, the solder bumps 5 were formed at various positions on the connection terminals 7 and were not formed at stable positions.

DESCRIPTION OF SYMBOLS 1 ... Wiring pattern 2 ... Convex shape 3 ... Solder resist 4 ... Base material 5 ... Solder bump 6 ... Semiconductor package substrate 7 ... Connection terminal 8 ... Opening width (of solder resist) 9 ... Opening (of solder resist) 10 ... Ni / Au plating 11 ... solder

Claims (5)

  There are a plurality of longitudinal connection terminals for connecting semiconductor elements, the plurality of connection terminals are arranged side by side in the lateral direction, and a convex shape is formed in a part of the plurality of connection terminals in the longitudinal direction. A semiconductor package substrate characterized by the above.   2. The semiconductor package substrate according to claim 1, wherein the convex shape is formed at a predetermined position in the longitudinal direction of the plurality of connection terminals formed side by side in the lateral direction.   3. The semiconductor package substrate according to claim 1, wherein the length of the convex shape in the longitudinal direction of the connection terminal is 1/5 to 1/3 of the length of the connection terminal.   4. The semiconductor package substrate according to claim 1, wherein a length of the connection terminal is defined by an opening width of a solder resist formed so as to cover both sides or one side in the longitudinal direction of the connection terminal. .   5. The solder bump according to claim 1, wherein a solder bump is formed at a predetermined position in a longitudinal direction on the connection terminal by supplying solder onto the connection terminal having a convex shape. Semiconductor package substrate.

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