JP4326410B2 - Circuit board manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a circuit board, and more particularly, to a method for manufacturing a circuit board having a flip-chip connection pad on a wiring.

  In a semiconductor package in which an electronic component such as a semiconductor chip is mounted on a circuit board, mounting by flip chip connection is an effective means for realizing high speed and high density. The flip chip connection is performed by forming a part of the wiring as a connection pad and bonding a solder bump disposed on the pad to, for example, an electrode terminal of a semiconductor chip.

  Conventionally, for example, as disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2000-77471), the connection pad portion is formed wider than the other portion of the wiring (general wiring portion). This is because solder bumps are intensively formed on the pads.

  The solder bump is formed by spraying solder powder on the wiring including the pad portion, heating and melting, and then cooling and solidifying. The melted solder swells on the base due to its own surface tension, but a larger swell than the general wiring part is formed on the wide pad part because of the large amount of solder powder adhering when sprayed. And the molten solder greatly raised on the pad attracts the molten solder forming a small bulge of the general wiring portion by the action of surface tension. As a result, the molten solder concentrates on the wide pad, and when this is cooled and solidified, a thick solder bump is formed on the pad, and only a thin solder film remains on the general wiring portion.

  In recent years, in order to further increase the speed and density, there is a demand for fine pitches that increase the wiring density on the circuit board. As the wiring pitch becomes finer, the flip chip connection pads formed on the wiring also need to be miniaturized. However, since the pad portion must be formed wider than the general wiring portion, various proposals have been made in order to cope with the fine pitch.

  Patent Document 1 (Japanese Patent Application Laid-Open No. 2000-77471) proposes securing the pad area by increasing the pad length instead of making the pad width narrower than before.

  Other than the flip chip connection pads, various countermeasures for fine pitch have been proposed. For example, Patent Document 2 (JP-A-5-191019) discloses a method in which solder particles are selectively attached to an adhesive resin pattern formed on a wiring, applied with flux, and heated and melted. In Patent Document 3 (Japanese Patent Laid-Open No. 2003-251494), by utilizing the difference in ionization tendency of metals, when Sn powder that is easily ionized and an organic acid Pb salt are coexisting and heated, a part of Sn is converted to Pb. A method of forming a replacement Sn-Pb solder is shown.

  However, the conventional method can cope with fine pitches up to about 100 μm, but cannot cope with fine pitches of 100 μm or less, and further 50 μm or less.

  When the method of Patent Document 1 is applied to try to form solder bumps intensively only on the pads using the surface tension of the molten solder, the width difference between the wiring pads and other parts needs to be 10 μm or more. is there.

  FIG. 1A is a partial plan view of a circuit board to which the pad form of Patent Document 1 is applied. The wiring 12 formed on the substrate 10 includes a wide pad 12P and a general wiring 12L. Both ends of the wiring are protected by a solder resist 14. 1B is a cross-sectional view taken along line XX in FIG. 1A, and the entire wiring 12 including the pad 12P and the general wiring 12L has a constant thickness T. FIG. When the solder powder is dispersed and heated and melted on the wiring 12 as described above, the solder bumps B are formed on the pads 12P as shown in FIG. 1 (3). The solder layer S1 is also coated on other general wiring portions, but the thickness is small as shown in the figure and can be ignored as compared with the solder layer S2 constituting the bump B.

  If the circuit board of FIG. 1 is designed with a wiring pitch of 40 μm (wiring thickness T is 17 μm, for example), the pad 12P has a width A = 20 μm, the pad B has a spacing B = 20 μm, and the general wiring 12L has a width C = 10 μm (= Pad width A-10 μm). However, the wiring width that can be stably formed on a normal circuit board is up to 20 μm, and it is extremely difficult to stably realize the wiring width of 10 μm.

  Japanese Patent Laid-Open No. 2001-284481 discloses a method of forming a flip chip connecting pad portion thicker than a general wiring portion. However, a subtractive method is used, and a copper-clad substrate is used. First, a pad is formed on the copper film, and then a wiring is formed by etching in a state where it is masked by the copper film of a wiring formation scheduled portion including the pad. At this time, if the mask position deviates from the pad, a part of the pad is exposed and etched, and a pad having a predetermined shape and size cannot be obtained. For this reason, there is a limit to the fine pitch from the standpoint of the alignment accuracy between the pad and the mask, and it cannot be applied to the fine pitch of 100 μm or less, and further 50 μm or less.

  In the method of Patent Document 4, since the pad thickness is added to the thickness of the copper film, the pad portion becomes thick, and the pad side surface area increases with respect to the pad area reduced for fine pitch. It is also unsuitable for fine pitching that solder wraps around easily.

JP 2000-77471 A (Claims) JP-A-5-191019 (Claims) JP 2003-251494 A (Claims) Japanese Patent Laid-Open No. 2001-284481 (Claims)

  An object of this invention is to provide the manufacturing method of the circuit board provided with the pad for flip chip connection which enables the fine pitch of 50 micrometers or less.

In order to achieve the above object, the present invention provides a method for manufacturing a circuit board having a flip-chip connection pad as a part of wiring,
A step of covering the formation position of the flip chip connection pad on the wiring with an etching mask;
Half-etching an exposed portion of the wiring not covered with the etching mask to reduce the thickness, and removing the etching mask to expose a pad thicker than the half-etched portion A method for manufacturing a circuit board is provided.

  In particular, it is most advantageous for fine pitch formation when the reduced thickness portion of the wiring and the thicker pad portion have the same width.

  In the present invention, since the pad formation planned portion of the wiring is masked and the general wiring formation scheduled portion is half-etched, the pad is formed relatively thick with respect to the general wiring. Since the pad is already higher than the general wiring before the solder powder is sprayed, it is not necessary to form the solder bump on the pad so as to be raised. An amount of solder necessary for bonding electrode terminals (gold bumps, etc.) of an electronic component such as a semiconductor chip to be flip-chip connected may be disposed on the pad to form a solder bump.

  Therefore, it is not necessary to concentrate the solder on the pad as in the conventional case, and therefore, it is not necessary to make the pad wider than the general wiring. Therefore, a fine pitch of 100 μm or less, further 50 μm or less, which has been impossible in the past, has been achieved. It becomes possible.

  In addition, since the semi-additive method is employed in which after the wiring is formed, the pad formation scheduled portion is masked and the other general wiring formation scheduled portions are half-etched, the mask alignment tolerance is large. For this reason, the present invention does not cause the problem of misalignment that occurs when the wiring formation scheduled portion including the pad previously formed by the conventional method using the subtractive method is masked later.

  Furthermore, in the conventional method based on the subtractive method, since the pad is formed on the copper film of the copper-clad substrate, the area of the pad side surface is relatively larger than the pad area, and the molten solder wraps around the pad side surface. It became a problem. On the other hand, in the present invention, the general wiring portion other than the pad portion is half-etched to reduce the thickness, thereby making the pad portion relatively thick, and the pad thickness is increased with respect to the pad width. The problem of wraparound of molten solder as in the above conventional method does not occur.

  FIG. 2A is a partial plan view of a circuit board to which the pad form of the present invention is applied. The wiring 102 formed on the substrate 100 includes a pad 102P having the same width A and a general wiring 102L. Both ends of the wiring are protected by a solder resist 104. 2B is a cross-sectional view taken along line XX in FIG. 2A, and the thickness T of the pad 102P is larger than the thickness t of the general wiring 102L. For example, the pad 102P has a thickness T = 17 μm, and the general wiring 102L has a thickness t = 10 μm. When solder powder is dispersed and heated and melted on the wiring 102 as described above, as shown in FIG. 2C, the solder layers S1 and S2 are formed on the pad 102P and the general wiring 102L with substantially the same thickness. Is formed. As a result, the solder layer S2 originally formed on the pad 102P having the large thickness T rises higher than the solder layer S1 formed on the lower general wiring portion 102L, and forms the solder bump B.

  When the circuit board of FIG. 2 is designed with a wiring pitch of 40 μm, the same width A = 20 μm for both the pad 102P and the general wiring 102L, and the same wiring interval B = 20 μm between the pads 102P and the general wiring 102L. The wiring width A = 20 μm is a sufficiently realizable size. Thus, by applying the pad configuration of the present invention, a fine pitch with a wiring pitch of 40 μm can be achieved.

  With reference to FIGS. 3-5, an example of the process of producing a circuit board by this invention is demonstrated.

  First, a core substrate shown in FIG. In the core substrate 200, first-layer wiring layers 202 formed on both surfaces are connected to each other through through holes 204, and the entire first-layer wiring layers 202 on both surfaces are covered with a buildup resin layer 206.

  Next, as shown in FIG. 3B, via holes 208 are opened by laser processing at predetermined positions of the build-up resin layers 206 on both sides.

  Next, as shown in FIG. 3 (3), an electroless copper plating layer 210 is formed on the build-up resin layers 206 on both sides and in the via holes 208.

  Next, as shown in FIG. 3 (4), a dry film resist 212 is pasted on the electroless copper plating layers 210 on both sides.

  Next, as shown in FIG. 3 (5), the dry film resist layer 212 is patterned by exposure and development to form an opening 214 that defines the second wiring layer.

  Next, as shown in FIG. 4A, electrolytic copper plating is performed using the electroless copper plating layer 210 as a power feeding layer to form a second wiring layer 216 in the opening 214 of the dry film resist 212.

  Next, as shown in FIG. 4 (2), a dry film resist 218 is further attached to both surfaces.

  Next, as shown in FIG. 4 (3), the dry film resist layer 218 is patterned by exposure / development to expose the half etching target areas on both sides of the flip chip connection pad formation planned portion of the second wiring layer 216. The opening 220 to be formed is formed.

  Next, as shown in FIG. 4D, the second wiring layer 216 exposed in the opening 220 is half-etched. As a result, the flip chip connection pads 216P with the original thickness and the general wiring 216L with reduced thicknesses on both sides thereof are formed at predetermined portions of the second wiring layer 216.

  Next, as shown in FIG. 5A, two layers of dry film resists 212 and 218 are peeled off. As a result, the thin electroless copper plating layer 210 covering the entire surface and the second wiring layer 216 formed thereon by electrolytic copper plating are exposed. At this stage, each part of the second wiring layer 216 is electrically connected by the electroless copper plating layer 210.

  Finally, as shown in FIG. 5 (2), flash etching is performed to remove the thin electroless copper plating layer 210 connected between the portions of the second-layer wiring layer 216, and the second-layer wiring of a predetermined pattern Layer 216 is completed. A flip-chip connection pad 216P is formed on a part of the second wiring layer 216 (the leftmost portion of the upper surface in the illustrated example). The general wiring 216L on both sides of the pad 21 is reduced in thickness by half etching, but has a cross-sectional area that can sufficiently allow a predetermined current.

  According to the present invention, there is provided a method for manufacturing a circuit board provided with a flip-chip connection pad that enables a fine pitch of 50 μm or less.

FIG. 1 is a (1) plan view, (2) cross-sectional view, and (3) cross-sectional view after forming solder bumps on a pad, showing a circuit board on which a wide flip chip connection pad is formed by a conventional method. FIG. 2 is a (1) plan view, (2) cross-sectional view, and (3) cross-sectional view after forming solder bumps on the pad, showing a circuit board on which a thick flip chip connecting pad according to the present invention is formed. 3 (1) to 3 (5) are cross-sectional views showing circuit board manufacturing steps for forming flip chip connection pads according to the present invention. 4 (1) to 4 (4) are sectional views showing the circuit board manufacturing process of the present invention subsequent to the process of FIG. 3 (5). 5 (1) to 5 (2) are cross-sectional views showing the circuit board manufacturing process of the present invention following the process of FIG. 4 (4).

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Board | substrate 102 Wiring 102P Pad part of wiring 102L General wiring part of wiring 102 200 Core base material 202 1st wiring layer 204 Through hole 206 Build-up resin layer 208 Via hole 210 Electroless copper plating layer 212 Dry film resist 214 Two layers Opening that defines the wiring layer of the eye 216 Second wiring layer 216P Flip chip connection pad 216L with the original thickness 216L General wiring with reduced thickness 218 Dry film resist 220 Opening that exposes the half etching target region

Claims (2)

In a manufacturing method of a circuit board provided with a flip chip connection pad as a part of wiring,
Forming an electroless copper plating layer on the wiring forming surface of the circuit board;
Applying a first dry film resist layer to the entire surface of the electroless copper plating layer and patterning to open a portion to be a wiring layer;
Forming a wiring layer in the opening by performing electrolytic copper plating using the electroless copper plating layer as a power feeding layer;
Bonding a second dry film resist layer covering the first dry film resist layer existing outside the opening and the wiring layer in the opening;
A step of patterning the second dry film resist layer to form an etching mask covering a pad forming position;
A step of reducing the thickness of the wiring layer by half-etching the wiring layer in a portion not covered with the etching mask other than the pad forming position;
Peeling the etching mask made of the second dry film resist and the first dry film resist;
A method for manufacturing a circuit board, comprising: a step of removing an electroless copper plating layer connecting portions of a wiring layer .   2. The method of manufacturing a circuit board according to claim 1, wherein the reduced thickness portion of the wiring and the thicker pad portion have the same width.

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