JP2012069918A - チップパッケージビルドアップのシステム及び方法 - Google Patents
チップパッケージビルドアップのシステム及び方法 Download PDFInfo
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- JP2012069918A JP2012069918A JP2011158524A JP2011158524A JP2012069918A JP 2012069918 A JP2012069918 A JP 2012069918A JP 2011158524 A JP2011158524 A JP 2011158524A JP 2011158524 A JP2011158524 A JP 2011158524A JP 2012069918 A JP2012069918 A JP 2012069918A
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- die
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/171—Frame
- H01L2924/1715—Shape
- H01L2924/17151—Frame comprising an aperture, e.g. for pressure control, encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】チップパッケージは、開口部が形成されているベース再配線層16と、接着材料が塗布されていない窓部26が形成された接着剤層24と、接着剤層を介してベース再配線層に固着されたダイ12とを含み、ダイの周囲部のみが接着剤層と接触するように、ダイは窓部と位置合わせされる。シールド要素20はベース再配線層と接着剤層との間に配置され、シールド要素の周囲部のみが接着剤層に装着されるように、シールド要素は、ベース再配線層に形成された開口部及び接着剤層の窓部とほぼ位置合わせされる。シールド要素は、エアギャップによりダイから分離され且つダイの前面52を露出させるように接着剤層から選択的に除去できるように構成される。
【選択図】図7
Description
12 ダイ
14 再配線層
16 ベース(初期)再配線層
18 金属層
20 保護シールド要素
21 ベントベース
22 ベース金属配線部
24 接着剤層
26 窓部
28 ベントポート
30 接着剤層の一部分
32 ダイパッド
36 エアギャップ
38 ビア
40 金属配線部
42 追加再配線層
44 接着剤層
46 はんだマスク
48 経路
50 接着剤層の一部分
52 ダイ前面
Claims (10)
- 中央領域に開口部が形成されているベース再配線層(16)と、
前記ベース再配線層(16)の一方の面に塗布され且つ接着材料が塗布されていない窓部(26)が形成された接着剤層(24)と、
前記接着剤層(24)を介して前記ベース再配線層(16)に固着された前面(52)を有し、且つ前記前面(52)の周囲部のみが前記接着剤層(24)と接触するように前記接着剤層(24)に形成された前記窓部(26)と位置合わせが行われたダイ(12)と、
前記ベース再配線層(16)を前記ダイ(12)に電気接続するために前記ベース再配線層(16)に形成された複数のビア(38)及び複数の金属配線部(40)と、
前記ベース再配線層(16)と前記接着剤層(24)との間に配置され、周囲部のみが前記接着剤層(24)に装着されるように前記ベース再配線層(16)に形成された前記開口部及び前記接着剤層(24)の前記窓部(26)とほぼ位置合わせされ、且つエアギャップ(36)により前記ダイ(12)から分離されるシールド要素(20)と
を備えるチップパッケージ(10)であって、前記シールド要素(20)は、前記ダイ(12)の前記前面(52)を露出させるように前記接着剤層(24)から選択的に除去できるように構成される、チップパッケージ(10)。 - 前記接着剤層(24)に形成されたベントポート(28)をさらに備えていて、前記ベントポート(28)は前記エアギャップ(36)から前記ダイ(12)の前記周囲部を超えて延在する、請求項1記載のチップパッケージ(10)。
- 前記ベントポート(28)が、前記エアギャップ(36)を周囲環境と流体連通させるように構成される、請求項2記載のチップパッケージ(10)。
- 前記ベントポート(28)の形成を可能にするために前記ベントポート(28)の下方に配置された金属ベントベース(21)をさらに備える、請求項2記載のチップパッケージ(10)。
- 前記ベース再配線層(16)の前記ダイ(12)とは反対側の面に接着された少なくとも1つの追加再配線層(42)と、前記追加再配線層(42)の各々に形成された複数のビア(38)及び複数の金属配線部(40)とをさらに備える、請求項1記載のチップパッケージ(10)。
- 一番上の追加再配線層(42)の上に配置されたはんだマスク(46)をさらに備える、請求項5記載のチップパッケージ(10)。
- 前記シールド要素(20)はパターニングされた金属シールドを備える、請求項1記載のチップパッケージ(10)。
- 前記ダイ(12)が、画像感知領域を形成するように構成されたカメラダイである、請求項1記載のチップパッケージ(10)。
- 前記シールド要素(20)が前記ダイ(12)の面積より狭い面積を有する、請求項1記載のチップパッケージ(10)。
- 前記ダイ(12)が、前記ダイ(12)の周囲に沿って形成された複数のダイパッド(32)をさらに備えていて、前記複数のダイパッド(32)は、前記シールド要素(20)により被覆されている前記ダイ(12)の領域の外側に配置される、請求項9記載のチップパッケージ(10)。
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US8969176B2 (en) * | 2010-12-03 | 2015-03-03 | Raytheon Company | Laminated transferable interconnect for microelectronic package |
US8658473B2 (en) * | 2012-03-27 | 2014-02-25 | General Electric Company | Ultrathin buried die module and method of manufacturing thereof |
US9117813B2 (en) | 2012-06-15 | 2015-08-25 | General Electric Company | Integrated circuit package and method of making same |
US9324664B2 (en) * | 2013-02-22 | 2016-04-26 | Unimicron Technology Corp. | Embedded chip package structure |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5355102A (en) * | 1990-04-05 | 1994-10-11 | General Electric Company | HDI impedance matched microwave circuit assembly |
US5401687A (en) * | 1993-04-15 | 1995-03-28 | Martin Marietta Corporation | Process for high density interconnection of substrates and integrated circuit chips containing sensitive structures |
US5635762A (en) * | 1993-05-18 | 1997-06-03 | U.S. Philips Corporation | Flip chip semiconductor device with dual purpose metallized ground conductor |
US5527741A (en) * | 1994-10-11 | 1996-06-18 | Martin Marietta Corporation | Fabrication and structures of circuit modules with flexible interconnect layers |
US5561085A (en) * | 1994-12-19 | 1996-10-01 | Martin Marietta Corporation | Structure for protecting air bridges on semiconductor chips from damage |
US6255137B1 (en) * | 1999-07-01 | 2001-07-03 | Lockheed Martin Corp. | Method for making air pockets in an HDI context |
US6964881B2 (en) * | 2002-08-27 | 2005-11-15 | Micron Technology, Inc. | Multi-chip wafer level system packages and methods of forming same |
US7880297B2 (en) * | 2007-12-31 | 2011-02-01 | Mediatek Inc. | Semiconductor chip having conductive member for reducing localized voltage drop |
US8259454B2 (en) | 2008-04-14 | 2012-09-04 | General Electric Company | Interconnect structure including hybrid frame panel |
US20110156261A1 (en) * | 2009-03-24 | 2011-06-30 | Christopher James Kapusta | Integrated circuit package and method of making same |
US8319318B2 (en) * | 2010-04-06 | 2012-11-27 | Intel Corporation | Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages |
US8618652B2 (en) * | 2010-04-16 | 2013-12-31 | Intel Corporation | Forming functionalized carrier structures with coreless packages |
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