JP2012064647A - Compound semiconductor light-emitting element and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide breakdown voltage against electrostatic discharge without lowering luminous efficiency of a compound semiconductor light-emitting element.SOLUTION: A compound semiconductor light-emitting element of the present invention comprises a substrate and a semiconductor stacked structure formed on the substrate. The semiconductor stacked structure includes an n-type layer, a light-emitting layer, and a p-type layer in this order from the substrate side, and has a p-side electrode contacting the p-type layer and an n-side electrode contacting the n-type layer. The n-type layer has one or more leak path layers having a surface roughness rougher than other layers constituting the semiconductor stacked structure. The area of the leak path layer is smaller than that of the other layers constituting the semiconductor stacked structure in plan view viewed from the top surface of the compound semiconductor light-emitting element.

Description

  The present invention relates to a compound semiconductor light-emitting device, and more particularly to a compound semiconductor light-emitting device having a structure with countermeasures against electrostatic breakdown.

  Conventionally, red light emitting diodes (LEDs) and green LEDs have been manufactured, but it has been difficult to manufacture blue LEDs. For this reason, the three primary colors of red, green, and blue light cannot be realized with the light emitting diode.

  However, since the introduction of the nitride-based blue LED in the 1990s, practical use of LED lighting has started. At present, LED lighting is starting to play an active role not only for signals but also for various applications such as backlights for liquid crystal monitors.

  LED illumination generally realizes a white LED by combining a blue LED chip and a YAG (yttrium, aluminum, garnet) phosphor. This white LED has a merit of being good for the environment because of lower power consumption, space saving, and mercury-free than conventional lighting, and is expected as a next-generation lighting fixture.

  Such a blue LED has a problem that its withstand voltage against electrostatic breakdown (ESD) is not sufficient because an electric field is more likely to be applied non-uniformly than a conventional LED. In particular, nitride-based blue LEDs are said to have a problem with withstand voltage against reverse surges.

  In order to improve the withstand voltage against reverse surge, Patent Document 1 adopts a blue LED structure shown in FIG. FIG. 27 is a schematic cross-sectional view showing the nitride semiconductor light emitting device of Patent Document 1. As shown in FIG. As shown in FIG. 27, the nitride semiconductor light emitting device of Patent Document 1 includes an AlN buffer layer 10, an n-type contact layer 11, a first nESD layer 12 made of iGaN, and an nGaN on a substrate 102. A second nESD layer 13, an n-type superlattice layer 14, a light emitting layer 15, a p-type superlattice layer 16, a p-type GaN layer 17, and a transparent electrode layer 18 made of ITO (Indium Tin Oxide) The passivation layer 19 is laminated in this order. An n-side electrode 22 composed of a V layer 20 and an Al layer 21 is formed on the n contact layer 11. When using an insulating substrate like the blue LED of Patent Document 1, a p-side electrode (not shown) and an n-side electrode 22 are formed on one of the front and back surfaces of the substrate 102.

  As a growth temperature when forming a semiconductor layer on the substrate 102 by the MOVPE method, the AlN buffer layer 10 is formed at a growth temperature of 400 ° C., and the n-type contact layer 11 is formed at a growth temperature of 1080 to 1140 ° C. To do. In contrast, nESD layers such as the first nESD layer 12 and the second nESD layer 13 are formed at 850 ° C.

  Thus, by forming the first nESD layer 12 at a relatively low temperature, pits are generated on the surface of the first nESD layer 12. When the second nESD layer 13 is formed thereon, Si concentrates around the pits on the surface of the first nESD layer 12, and this part becomes a path for releasing overcurrent. Even if a surge is introduced into the LED element by the path formed in this way, the withstand voltage is not affected and the electrostatic withstand voltage characteristic can be improved.

JP 2007-180495 A JP 2007-214548 A

  However, according to the research by the inventors, it has been found that the LED of Patent Document 1 has the following problems.

  In general, when the well layer constituting the light emitting layer is thinned, the carrier concentration in the well layer increases, and non-radiative recombination called Auger recombination increases, and the light emission efficiency tends to decrease. On the contrary, when the well layer is thickened, the carrier concentration is lowered and non-radiative recombination is reduced, so that the light emission efficiency tends to be improved.

  That is, in order to efficiently convert the current injected into the light emitting element into light, it is necessary to increase the thickness of the well layer to at least about 3 nm to 3.5 nm, for example. However, as shown in Patent Document 1, it has been found that if the well layer is thickened with the nESD layer formed, the light emission efficiency is lowered rather than the light emission efficiency is improved. The cause of the decrease in luminous efficiency is considered to be due to defects in the crystal intentionally formed in the ESD layer as a current path when a surge is applied.

  This is because it is generally known that when an InGaN layer is formed, the In composition in the vicinity of crystal defects is higher than the surroundings, and InGaN with a high In composition near the dislocation in the InGaN well layer has a high p layer growth temperature. This is because it is considered that a non-light emitting region is formed by decomposition. It has also been found that increasing the thickness of the well layer increases the half-value width of the emission spectrum of the LED, and tends to promote inhomogeneity of In.

  That is, the non-light-emitting region that causes a decrease in the external quantum efficiency of the LED is less likely to be formed as the dislocation density is lower, and in order to form an LED having a thick well layer, defects in the crystal immediately below the light-emitting layer are formed. Little is very important. However, in the iGaN layer formed at a relatively low temperature as described above, there are pits on the surface and many crystal defects around the pit. Therefore, the conventional ESD layer is an LED with a thin well layer. Can not be adopted.

  The present invention has been made in view of the current situation as described above, and an object of the present invention is to provide a withstand voltage against electrostatic breakdown without reducing the light emission efficiency of the compound semiconductor light emitting element. .

  The compound-based semiconductor light-emitting device of the present invention is a compound-based semiconductor light-emitting device having a substrate and a semiconductor stacked structure formed on the substrate, and the semiconductor stacked structure includes an n-type layer and a light-emitting layer in order from the substrate side. And includes a p-type layer, and has a p-side electrode in contact with the p-type layer and an n-side electrode in contact with the n-type layer, and the n-type layer is more than other layers constituting the semiconductor stacked structure. In addition, it has at least one leak path layer having a rough surface roughness, and the area of the leak path layer is smaller than the areas of other layers constituting the semiconductor multilayer structure in plan view from the top surface of the compound semiconductor light emitting device It is characterized by.

  An n-side electrode and a p-side electrode are placed on either one of the front and back surfaces of the substrate, and the leak path layer is formed in a plan view from the upper surface of the compound semiconductor light emitting element. It is preferably located between the electrodes.

  It is preferable to arrange the leak path layer so that the region where the p-side electrode is arranged and the region where the leak path layer is arranged do not overlap in a plan view from the upper surface of the compound semiconductor light emitting device.

  An n-side electrode and a p-side electrode are placed on either one of the front and back surfaces of the substrate, and the leak path layer is directly below the p-side electrode in plan view from the top surface of the compound semiconductor light emitting device. Preferably it is located.

  It is preferable to have a structure in which current is difficult to be injected only into the light emitting layer immediately below the p-side electrode. In a region immediately below the p-side electrode of the semiconductor multilayer structure, it is preferable to have a current confinement layer having low electrical conductivity between the p-side electrode and the surface of the semiconductor multilayer structure immediately below the p-side electrode.

At the interface between the p-side electrode and the p-type layer formed immediately below the p-side electrode, the contact resistance immediately below the p-side electrode is higher than the contact resistance of the portion other than directly below the p-side electrode, and 0 It is preferably 1 Ωcm ² or more.

  The compound-based semiconductor light-emitting device of the present invention is a compound-based semiconductor light-emitting device having a substrate and a semiconductor stacked structure formed on the substrate, and the semiconductor stacked structure includes a p-type layer and a light-emitting layer in order from the substrate side. A p-side electrode in contact with the surface opposite to the side on which the semiconductor multilayer structure is formed, and an n-side electrode in contact with the n-type layer. And the n-type layer has at least one leak path layer having a surface roughness rougher than other layers constituting the semiconductor multilayer structure, and the area of the leak path layer in a plan view from the upper surface of the compound semiconductor light emitting device Is smaller than the area of the other layers constituting the semiconductor multilayer structure, and the leak path layer is formed immediately below the n-side electrode. It is preferable to have a structure in which current is difficult to be injected only into the light emitting layer directly under the n-side electrode.

  In a region immediately below the n-side electrode of the semiconductor multilayer structure, it is preferable to have a current confinement layer having low electrical conductivity between the n-side electrode and the surface of the semiconductor multilayer structure directly below the n-side electrode.

  In the method for manufacturing a compound semiconductor light emitting device of the present invention, an n-type layer and a leak path layer are grown on a substrate in this order, and the n-type layer is exposed by removing a part of the leak path layer. And a step of forming a light emitting layer and a p-type layer in this order on the leak path layer and the exposed n-type layer.

  The step of exposing the n-type layer is preferably performed by performing photolithography on the leak path layer and then dry etching a part of the leak path layer using a chlorine-based gas.

  The method for producing a compound semiconductor light emitting device of the present invention includes a step of crystal growth of an n-type layer on a substrate, a step of forming a dielectric film on the n-type layer, and patterning the dielectric film. A step of exposing a part of the n-type layer, a step of crystal-growing a leak path layer on the dielectric film and the exposed n-type layer, and etching the dielectric film and the leak path layer formed on the dielectric film And removing the n-type layer by removing the n-type layer, and forming a light emitting layer and a p-type layer in this order on the leak path layer and the exposed n-type layer in this order.

  The present invention exhibits an excellent effect that, by having the above-described configuration, a withstand voltage against electrostatic breakdown can be imparted without reducing the light emission efficiency of the compound semiconductor light emitting device.

(A) is a typical top view of the compound semiconductor light-emitting device of Embodiment 1, (b) is typical sectional drawing of Ib-Ib of the compound semiconductor light-emitting device shown by (a). It is. FIG. 5 is a schematic cross-sectional view showing the structure of a compound semiconductor light-emitting element according to Embodiment 2. FIG. 5 is a schematic cross-sectional view showing the structure of a compound semiconductor light-emitting element according to Embodiment 3. (A) is a typical top view of the compound semiconductor light-emitting device of Embodiment 4, (b) is typical sectional drawing of IIb-IIb of the compound semiconductor light-emitting device shown by (a). It is. FIG. 6 is a schematic cross-sectional view showing the structure of a compound semiconductor light-emitting element in a fifth embodiment. FIG. 10 is a schematic cross-sectional view showing the structure of a compound semiconductor light-emitting element in a sixth embodiment. It is typical sectional drawing which shows the state after forming a photoresist mask on a board | substrate. It is typical sectional drawing which shows the state after forming uneven | corrugated shape in the surface of a board | substrate. It is a typical sectional view showing the state after forming a buffer layer, a leak path whole surface layer, etc. on a substrate. It is typical sectional drawing which shows the state after removing a part of leak path whole surface layer by dry etching. It is a typical sectional view showing a state when a part of leak path whole surface layer remains on a Si dope GaN layer. It is typical sectional drawing which shows the state after removing a part of dielectric film by wet etching. FIG. 6 is a schematic cross-sectional view showing a state after a leak path entire surface layer is formed on a dielectric film. It is typical sectional drawing which shows the state after forming a semiconductor laminated structure on a leak path | pass layer. It is typical sectional drawing which shows the state after forming a transparent electrode layer on a p-type layer. It is typical sectional drawing which shows the state after removing the side surface of a semiconductor laminated structure. It is typical sectional drawing which shows the state after forming the p side pad electrode and the n side pad electrode. It is typical sectional drawing which shows the state after forming a semiconductor laminated structure on a board | substrate. It is typical sectional drawing which shows the state after forming the p side contact electrode on a p-type layer. It is typical sectional drawing which shows the state after forming a dielectric film on a p-type layer. It is typical sectional drawing which shows the state after forming the diffusion prevention layer on the upper surface of a p side contact electrode and a dielectric film. It is typical sectional drawing which shows the state after bonding Si board | substrate which has a eutectic solder layer on a diffusion prevention layer. It is typical sectional drawing which shows the state after isolate | separating a board | substrate. It is typical sectional drawing which shows the state after removing a buffer layer, an undoped GaN layer, and a part of Si dope GaN layer. It is typical sectional drawing which shows the state after removing the side surface of a semiconductor laminated structure. It is typical sectional drawing which shows the state after forming the p side pad electrode and the n side pad electrode. 6 is a schematic cross-sectional view showing a nitride semiconductor light emitting device of Patent Document 1. FIG.

  Hereinafter, the compound semiconductor light emitting device of the present invention and the manufacturing method thereof will be described with reference to the drawings. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts. In addition, dimensional relationships such as length, width, thickness, and depth are changed as appropriate for clarity and simplification of the drawings, and do not represent actual dimensional relationships.

<Embodiment 1>
FIG. 1A is a top view of the compound semiconductor light emitting device of the present embodiment, and FIG. 1B is a cross-sectional view of Ib-Ib of the compound semiconductor light emitting device shown in FIG. It is.

  As shown in FIG. 1A, the compound semiconductor light emitting device of the present embodiment is obtained by forming a semiconductor multilayer structure 190 on a substrate 100 having an uneven surface. In this semiconductor stacked structure 190, a buffer layer 110, an undoped GaN layer 120, a Si-doped GaN layer 130, a leak path layer 210, an n-side superlattice layer 140, a light emitting layer 150, and a p-type layer 160 are sequentially stacked. . Here, the Si-doped GaN layer 130 and the n-side superlattice layer 140 are n-type layers.

  The leak path layer 210 is formed so as to cover a part of the Si-doped GaN layer 130. A transparent electrode layer 300 and a p-side pad electrode 310 are formed on the surface of the p-type layer 160. Hereinafter, the transparent electrode layer 300 and the p-side pad electrode 310 may be collectively referred to as “p-side electrode 390”.

  Further, part of the side surfaces of the Si-doped GaN layer 130, the leak path layer 210, the n-side superlattice layer 140, the light emitting layer 150, and the p-type layer 160 are removed, and the exposed surface of the Si-doped GaN layer 130 is exposed. , An n-side pad electrode 320 is formed.

  The compound-based semiconductor light-emitting device of the present invention is characterized in that the area of the leak path layer 210 is smaller than the areas of the other layers constituting the semiconductor multilayer structure 190 in plan view from the top surface. By forming the leak path layer 210 in this way, even if a surge in the reverse direction is applied to the compound semiconductor light emitting device, the surge current selectively passes through the leak path layer. Also excellent.

  On the other hand, the light emission efficiency of the light emitting layer 150 immediately above the leak path layer 210 is reduced, but the area where the leak path layer 210 is not formed immediately below the light emitting layer 150 due to the small area of the leak path layer 210 as described above. In this region, the light emission efficiency of the light emitting layer can be prevented from decreasing. Thus, the compound semiconductor light emitting device of the present invention is characterized in that it can enjoy the light emission of the light emitting layer to the maximum while maintaining the withstand voltage performance against electrostatic breakdown.

  In particular, as shown in FIG. 1A, the leak path layer 210 is preferably located between the n-side electrode and the p-side electrode 390 in a plan view from the top surface of the compound semiconductor light emitting device. Thereby, the fall of the luminous efficiency of a light emitting layer can further be suppressed.

  Further, as shown in FIG. 1B, in a plan view from the upper surface of the compound semiconductor light emitting element, the region where the p-side electrode 390 is disposed and the region where the leak path layer 210 is disposed do not overlap. It is preferable to arrange | position. By arranging the p-side electrode 390 and the leak path layer 210 in this manner, the sheet resistance of the p-type layer 160 is high when a forward current is passed through the compound semiconductor light emitting device shown in FIG. In addition, since the current hardly spreads in the horizontal direction (plane direction perpendicular to the thickness direction) of the p-type layer 160, only the light-emitting layer 150 immediately below the transparent electrode layer 300 can emit light.

  By adopting the structure as described above, it becomes difficult for carriers to be injected into the light emitting layer having a relatively low light emitting efficiency above the leak path layer, so that wasteful consumption of carriers can be suppressed, thereby increasing the light emitting efficiency. be able to. Below, each part which comprises a compound type semiconductor light-emitting device is demonstrated.

(substrate)
In this embodiment mode, the substrate 100 is preferably a sapphire substrate. Further, the surface of the substrate 100 may be flat, or irregularities may be formed. From the viewpoint of improving the light extraction efficiency of the light emitting element, it is preferable that irregularities are formed.

  Here, as the unevenness formed on the surface of the substrate 100, for example, as shown in FIG. 1B, the shape of the convex portion is a truncated cone or a dome shape having no flat portion at the top. Is preferred. For example, the upper base and the bottom of the truncated cone preferably have a bottom circle diameter of 0.2 μm or more and 4 μm or less, and an upper base circle diameter of 1 μm or less. Such protrusions are preferably formed at a pitch of 0.3 μm or more and 8 μm or less.

(Semiconductor laminated structure)
In the present invention, the semiconductor multilayer structure is not limited to the multilayer structure shown in FIG. 1B, but is a general gallium nitride based semiconductor multilayer structure, and the leak path layer constitutes the semiconductor multilayer structure. As long as the area is smaller than the area of other layers, it does not depart from the scope of the present invention. In the following, the leak path layer and the position where it is formed will be described.

(Leakage path layer)
In the present invention, the leak path layer 210 serves as a current path when a surge is applied from the outside of the compound semiconductor light emitting device. By providing such a leak path layer 210, electrostatic withstand voltage characteristics can be improved.

  In order for the leak path layer 210 to exhibit the above-described performance, fine convex portions called pits need to be distributed on the surface thereof. Specifically, it is preferable that the root mean square (RMS) of the surface of the leak path layer 210 is 2 nm or more and 20 nm or less and pits are distributed. The Si doped around the pits is distributed at a relatively high concentration, and this portion serves as a current path, thereby improving the electrostatic withstand voltage characteristics. In the present invention, the above-mentioned RMS employs a value measured by an atomic force microscope (AFM: Atomic Force Microscope).

  In order to form pits in the leak path layer 210 as described above, it is preferable to form the leak path layer at a low temperature of 780 ° C. or higher and 900 ° C. or lower. This is because the island-like growth can be promoted by growing at such a low temperature. Incidentally, the RMS of the surface of the Si-doped GaN layer 130 is 1 nm or less.

  FIG. 1B shows the case where the leak path layer 210 is formed on the surface of the Si-doped GaN layer 130, but the present invention is not necessarily limited to the case where the leak path layer 210 is formed at this position. If the leak path layer 210 is formed at a position closer to the substrate side than the layer 150, the position is not particularly limited. Further, the leak path layer 210 is not limited to a single layer structure, and may have a stacked structure in which two or more layers are stacked.

  Further, the leak path layer 210 is not necessarily composed of only Si-doped GaN, and may have a two-layer structure of a non-doped GaN layer and a Si-doped GaN layer, for example. The leak path layer 210 preferably has a thickness of 0.015 μm or more and 0.04 μm or less.

(Buffer layer)
In the present embodiment, the buffer layer 110 is formed in contact with the substrate 100 in the semiconductor multilayer structure 190. By forming the buffer layer 110 at such a position, the crystalline state of the other layers constituting the semiconductor multilayer structure 190 can be kept good.

(N-type layer)
In the present invention, the n-type layer includes, for example, an In _x Ga _1-x N layer (0.05 ≦ X ≦ 0.15) having a thickness of 2 nm to 5 nm, and a Si-doped GaN layer having a thickness of 2 nm to 5 nm. Alternatively, a superlattice structure in which 10 layers are alternately stacked can be used.

(Light emitting layer)
In the present invention, the light emitting layer 150 has a laminated structure in which, for example, an undoped In _0.25 Ga _0.75 N layer with a thickness of 2.5 nm and an undoped GaN layer with a thickness of 2.5 nm are alternately repeated for each six layers. Can be used.

(P-type layer)
In the present invention, the p-type layer 160 is preferably made of Mg-doped GaN having a Mg doping concentration of about 5 × 10 ¹⁹ / cm ³ . Such a p-type layer 160 is formed at a temperature of about 1100 ° C., and has a thickness of about 80 nm, for example. After forming the p-type layer 160 in this manner, the semiconductor multilayer structure is formed by cooling the substrate to room temperature and taking out the substrate.

(Transparent electrode layer)
In the present invention, any material can be used for the transparent electrode layer 300 as long as it is made of a material having transparency and conductivity. An example of a material suitable for the transparent electrode layer 300 is ITO. Further, the thickness of the transparent electrode layer 300 can be a conventionally known thickness.

<Embodiment 2>
FIG. 2 is a cross-sectional view of the compound semiconductor light emitting device of this embodiment. As shown in FIG. 2, the compound-based semiconductor light-emitting device of this embodiment is the same as that of Embodiment 1 except that a leak path layer 210 is formed immediately below the p-side pad electrode 310. . By providing the leak path layer 210 at such a position, it is possible to make it difficult to inject current only into the light emitting layer 150 immediately below the p-side pad electrode 310. As a result, ESD countermeasures can be taken without lowering the light output, and the luminous efficiency can be further increased.

  This is because although the light emitting layer 150 immediately above the leak path layer 210 has a reduced luminous efficiency, light generated in the light emitting layer 150 immediately below the p-side pad electrode 310 is easily absorbed by the p-side pad electrode 310 in the first place. It is difficult to take out photons outside the element. Even if the leakage path layer 210 is provided at a position where the light emission efficiency of the light emitting layer is relatively low in this way, as a result, it does not contribute to the reduction of the light emission efficiency, but rather it can suppress wasteful consumption of carriers. is there.

<Embodiment 3>
FIG. 3 is a cross-sectional view of the compound semiconductor light emitting device of this embodiment. In the compound semiconductor light emitting device of the present embodiment, as shown in FIG. 3, the current confinement layer 800 having low electrical conductivity is provided at the position of the transparent electrode layer 300 immediately below the p-side pad electrode 310. Other than that, the second embodiment is the same as the second embodiment.

  By providing the current confinement layer 800 at such a position, current hardly flows in the light emitting layer 150 immediately below the current confinement layer 800. Therefore, as compared with the structure shown in FIG. 2, carriers are not wasted in the light emitting layer 150 having relatively low light emission efficiency, so that the light emission efficiency can be further increased.

(Current confinement layer)
In the present embodiment, the current confinement layer 800 may have a single layer structure or a multilayer structure in which two or more layers are stacked. In addition, the material constituting the current confinement layer 800 may be any material as long as it exhibits an insulation property that makes it difficult for carriers to be injected into the light emitting layer 150 in the region where the light emission efficiency is directly below the p-side pad electrode 310. ₂ , SiN, TiO ₂ or the like can be used.

  The thickness of the current confinement layer 800 may be any thickness as long as carriers can be hardly injected into the light emitting layer 150 immediately below the p-side pad electrode 310. For example, the thickness is preferably about 150 μm.

  Further, the position where the current confinement layer 800 is formed is not limited to the position between the p-type layer 160 and the transparent electrode layer 300 as shown in FIG. 3. For example, the transparent electrode layer 300 and the p-side pad electrode 310 are formed. Or between the transparent electrode layer 300 and the transparent electrode layer 300.

  In addition, the current confinement layer 800 is not necessarily provided. For example, the surface of the p-type layer 160 immediately below the p-side pad electrode 310 is subjected to plasma treatment or the like, thereby electrically inactivating the portion. Good.

The above plasma treatment is performed as follows. That is, after the p-type layer 160 is formed and before the transparent electrode layer 300 is formed, a portion of the surface of the p-type layer 160 other than the portion immediately above the leak path layer 210 is covered with a photoresist. Then, the exposed portion of the p-type layer 160 is increased in resistance by performing plasma discharge while flowing Ar gas in a parallel plate type RIE apparatus. The contact resistance between the p-type layer 160 and the transparent electrode layer 300 in the portion not subjected to plasma treatment is 0.02 Ω · cm ² , whereas the p-type layer 160 and the transparent electrode layer 300 in the plasma-treated portion are The contact resistance is 0.1 Ω · cm ² or more.

  Due to the difference in contact resistance, carriers are not injected into a portion with a high contact resistance even if a current confinement layer is not provided, and the light emitting layer directly above the leak path layer 210 having a relatively low light emission efficiency is substantially not present. Current can be prevented from being injected.

<Embodiment 4>
The compound-based semiconductor light-emitting device of Embodiments 1 to 3 has a structure in which a p-side electrode and an n-side electrode are formed on one surface of the front and back surfaces of the substrate, but the compound-based semiconductor light-emitting device of Embodiment 4 In the element, a p-side electrode is formed on one surface of the front and back of the substrate, and an n-side electrode is formed on the other surface. Thus, even when the n-side electrode and the p-side electrode are formed above and below the compound-based semiconductor light-emitting element, the effects of the present invention can be obtained.

  Hereinafter, the compound-based semiconductor light-emitting device of the present embodiment will be described with reference to FIG. 4A is a top view of the compound semiconductor light emitting device of the present embodiment, and FIG. 4B is a cross-sectional view of the compound semiconductor light emitting device shown in FIG. 4A taken along line IIb-IIb. is there.

  As shown in FIG. 4B, the compound-based semiconductor light-emitting device of the present embodiment is a compound-based semiconductor light-emitting device having a substrate 101 and a semiconductor multilayer structure 191 formed on the substrate 101. The semiconductor multilayer structure 191 is formed by laminating a p-type layer 161, a light emitting layer 151, and an n-type layer 141 in order from the substrate 101 side, and the semiconductor multilayer structure 191 on the front and back of the substrate 101 is formed. A p-side electrode 311 that is in contact with the surface opposite to the opposite side, and an n-side pad electrode 321 that is in contact with the n-type layer 141, and the n-type layer 141 is formed from other layers constituting the semiconductor multilayer structure 191. 1 has at least one leak path layer 211 having a rough surface roughness, and the area of the leak path layer 211 in the plan view from the upper surface of the compound semiconductor light emitting device is equal to the area of other layers constituting the semiconductor multilayer structure 191. Characterized in that is also small. That is, in this embodiment, as shown in FIG. 4, the leak path layer 211 is formed not to cover the entire surface of the n-type layer 141 but to cover a part thereof.

  Here, a eutectic solder layer 501, a diffusion prevention layer 421, a dielectric film 401, and a p-side contact electrode 411 are formed in this order between the substrate 101 and the semiconductor multilayer structure 191. In addition, a Si-doped GaN layer 131 is formed between the n-side pad electrode 321 and the n-type layer 141.

  In the compound semiconductor light emitting device of the present embodiment, a part of the leak path layer 211 is removed as in the first embodiment. Therefore, there is a region where the leak path layer 211 is not present immediately below the light emitting layer 151. Like the compound semiconductor light emitting element of the first embodiment, the light output is high and the half width of the wavelength is narrow and good. Light emission characteristics can be obtained.

<Embodiment 5>
FIG. 5 is a cross-sectional view of the compound semiconductor light emitting device of this embodiment. The compound semiconductor light emitting device of this embodiment is the same as that of Embodiment 4 except that a leak path layer 211 is formed immediately below the n-side pad electrode 321 as shown in FIG. . By disposing the leak path layer 211 at such a position, it is possible to take ESD countermeasures without lowering the light output, thereby improving the light emission efficiency.

  This is because although the light emitting layer 151 immediately below the leak path layer 211 has a relatively low luminous efficiency, light generated in the light emitting layer 151 immediately below the n-side pad electrode 321 is easily absorbed by the n-side pad electrode 321 in the first place. Therefore, it is difficult to take out photons out of the element. Thus, even if the leak path layer 211 is provided at a position where the light emission efficiency of the light emitting layer 151 is relatively low, it does not contribute to the reduction of the light emission efficiency as a result, and rather wasteful consumption of carriers can be suppressed. It is.

<Embodiment 6>
FIG. 6 is a schematic cross-sectional view of the compound semiconductor light emitting device of this embodiment. As shown in FIG. 6, the compound-based semiconductor light-emitting device of the present embodiment is implemented except that a current confinement layer 801 is provided at a position in contact with the Si-doped GaN layer 131 of the n-side pad electrode 321. It is the same as that of form 5.

  By providing the current confinement layer 801 at such a position, no current substantially flows through the light emitting layer 151 immediately below the current confinement layer 801. For this reason, as compared with the structure shown in FIG. 5, carriers are not wasted in the light emitting layer 151 having relatively low light emission efficiency, and the light emission efficiency can be further increased. Note that the current confinement layer 801 can be the same as that described in Embodiment 3.

<Method for Manufacturing Compound-Based Semiconductor Light-Emitting Element of Embodiment 1>
Below, with reference to FIGS. 7-17, the manufacturing method of the compound type semiconductor light-emitting device of Embodiment 1 is demonstrated. 7-17 is typical sectional drawing which shows 1 process of the manufacturing method of the compound type semiconductor light-emitting device of Embodiment 1. FIG. The manufacturing process shown in FIGS. 7 to 17 is schematically shown by extracting an area having a diameter of 2 inches corresponding to one element, but in actuality, the structure shown in FIG. 17 is continuously formed. By separating the adjacent chips, the compound semiconductor light emitting device shown in FIG. 1 is obtained.

  FIG. 7 is a schematic cross-sectional view showing a state after a photoresist mask is formed on the substrate. First, as shown in FIG. 7, a photoresist mask 600 is formed on the substrate 100 by using a normal photolithography method.

FIG. 8 is a schematic cross-sectional view showing a state after the uneven shape is formed on the surface of the substrate. After the photoresist mask 600 is formed as shown in FIG. 7, the substrate 100 is set in an inductively coupled plasma type dry etching apparatus. Then, the substrate 100 is dry-etched with a mixed gas of SiC ₄ and Ar to form an uneven shape on the surface of the substrate 100. Then, by removing the photoresist mask 600 on the substrate, the substrate 100 shown in FIG.

(Step of crystal growth of n-type layer and leak path layer in this order)
FIG. 9 is a schematic cross-sectional view showing a state after a buffer layer, an n-type layer, a leak path entire surface layer, and the like are formed on the substrate. The structure shown in FIG. 9 is produced by crystal growth of each layer using a metal-organic vapor phase epitaxy (MOVPE) apparatus. First, a substrate having a concavo-convex shape on the surface shown in FIG. 8 is put into a MOVPE apparatus. Then, after heating the substrate to 550 ° C., a buffer layer 110 made of undoped GaN having a thickness of 10 nm to 50 nm is formed.

Next, the temperature of the substrate 100 is raised to 1100 ° C. to form an undoped GaN layer 120 having a thickness of 2 μm and an Si-doped GaN layer 130 having a thickness of 1.5 μm. The Si doping concentration in the Si-doped GaN layer 130 is 5 × 10 ¹⁸ / cm ³ .

Then, the temperature of the substrate 100 is lowered and set to 780 ° C. or more and 900 ° C. or less, and a leak path entire surface layer 210a made of Si-doped GaN having a thickness of 30 nm is formed. The doping concentration of Si in the leak path entire surface layer 210a is 5 × 10 ¹⁸ / cm ³ . In this way, the structure shown in FIG. 9 can be formed.

(Step of exposing the n-type layer)
FIG. 10 is a schematic cross-sectional view showing a state after a part of the entire surface of the leak path is removed by dry etching. After forming the leak path entire surface layer 210a as shown in FIG. 9, a part of the leak path entire surface layer 210a is removed as shown in FIG. 10 by combining a normal photolithography method and a dry etching method. As the dry etching method, an inductively coupled plasma method using SiCl ₄ gas is preferably used.

  Here, as shown in FIG. 10, when part of the leak path entire surface layer 210a is removed by the dry etching method, even if part of the Si-doped GaN layer 130 is etched at the same time, the characteristics of the compound semiconductor light emitting device There is no problem.

  In the above description, the case where the leak path layer 210 is formed by removing a part of the leak path entire surface layer 210a has been described. However, in this case, if the top surface of the leak path entire surface layer 210a is uneven, etching is performed. As a result, a part of the portion where the leakage path entire surface layer 210a is to be removed may remain on the Si-doped GaN layer 130.

  FIG. 11 is a schematic cross-sectional view showing a state when a part of the entire surface of the leak path remains on the Si-doped GaN layer. As shown in FIG. 11, if the surface roughness of the leak path whole surface layer 210a remains on the Si-doped GaN layer 130 as it is, the crystallinity of the semiconductor multilayer structure formed on the upper surface may deteriorate.

The following method may be used as a method of forming a leak path layer for suppressing the remaining of the leak path entire surface layer. That is, first, the buffer layer 110, the undoped GaN layer 120, and the Si-doped GaN layer 130 are formed on the substrate. Thereafter, before forming the entire surface of the leak path, a dielectric film 401 made of SiO ₂ is formed using a plasma CVD apparatus.

  Then, using a normal photolithography method and a wet etching method using hydrofluoric acid, as shown in FIG. 12, the dielectric film 401 in the portion where the leak path layer is formed is removed. FIG. 12 is a schematic cross-sectional view showing a state after a part of the dielectric film is removed by wet etching. As shown in FIG. 12, after removing a part of the dielectric film, the substrate is set again in the MOVPE apparatus.

  FIG. 13 is a schematic cross-sectional view showing a state after the entire surface of the leak path is formed on the dielectric film. A leak path layer 210 made of Si-doped GaN having a thickness of 30 nm is formed on the exposed Si-doped GaN layer 130 under the same conditions as when the leak path entire surface layer is formed. At this time, as shown in FIG. 13, a film having a composition corresponding to the entire surface of the leak path is not formed on the dielectric film 401, and GaN microcrystals 700 are formed discretely.

  Then, by removing the substrate 100 from the MOVPE apparatus and removing the dielectric film together with the GaN microcrystal 700 in hydrofluoric acid, the leak path layer 210 can be formed in a desired region. By forming the leak path layer 210 in this way, the leak path layer 210 can be formed without leaving surface irregularities on the entire surface of the leak path on the Si-doped GaN layer 130.

(Step of forming light emitting layer and p-type layer)
FIG. 14 is a schematic cross-sectional view showing a state after the semiconductor multilayer structure is formed on the leak path layer. After forming the leak path layer 210 by the above method, the substrate 100 is set in the MOVPE apparatus, and as shown in FIG. 14, the n-side superlattice layer 140, the light emitting layer 150, and the p-type layer 160 are formed in this order. . Hereinafter, film forming conditions for the n-side superlattice layer 140, the light emitting layer 150, and the p-type layer 160 will be described.

The n-side superlattice layer 140 is formed by heating the substrate 100 to 815 ° C., then forming an In _x Ga _1-x N layer (0.05 ≦ x ≦ 0.15) having a thickness of 2.5 nm and a thickness of 2.5 nm. It is formed by alternately laminating 10 layers of Si-doped GaN layers each having a thickness.

The light emitting layer 150 is formed by maintaining the temperature in the MOVPE apparatus at 815 ° C. and alternately laminating six undoped In _0.25 Ga _0.75 N layers and six undoped GaN layers.

The p-type layer is formed by raising the temperature to 1100 ° C. and growing Mg-doped GaN having a Mg doping concentration of 5 × 10 ¹⁹ / cm ³ .

  FIG. 15 is a schematic cross-sectional view showing a state after the transparent electrode layer is formed on the p-type layer. After the p-type layer is formed as described above, the substrate is taken out after cooling to room temperature, and heat treatment is performed in nitrogen gas at 800 ° C. for 5 minutes.

  Next, a transparent electrode entire surface layer is formed on the surface of the p-type layer 160 using a sputtering apparatus. Then, by using a normal photolithography method and a wet etching method, the transparent electrode whole surface layer is patterned into a desired shape, and a transparent electrode layer 300 as shown in FIG. 15 is formed.

FIG. 16 is a schematic cross-sectional view showing a state after removing a part of the semiconductor multilayer structure. Next, by combining a normal photolithography method and an inductively coupled plasma type dry etching method using SiCl ₄ gas, as shown in FIG. 16, a p-type layer 160, a light emitting layer 150, an n-side superlattice. The layer 140, the leak path layer 210, and a part of the Si-doped GaN layer 130 are removed, and a part of the Si-doped GaN layer 130 is exposed.

  FIG. 17 is a schematic cross-sectional view showing a state after the p-side pad electrode and the n-side pad electrode are formed. As shown in FIG. 17, the p-side pad electrode 310 is formed on the surface of the transparent electrode layer 300, and the n-side pad electrode 320 is formed on the surface where the Si-doped GaN layer 130 is exposed. The p-side pad electrode 310 and the n-side pad electrode 320 are formed by combining a normal photolithography method, an electron beam evaporation method, and a lift-off method. The thus-formed stack shown in FIG. 17 is divided into chips to obtain the compound semiconductor light emitting device of the first embodiment shown in FIG.

<Method for Manufacturing Compound Semiconductor Light-Emitting Device of Embodiment 4>
Below, with reference to FIGS. 18-26, the manufacturing method of the compound type semiconductor light-emitting device of Embodiment 4 is demonstrated. 18 to 26 are schematic cross-sectional views illustrating one process of the method for manufacturing the compound semiconductor light-emitting device of the fourth embodiment.

  FIG. 18 is a schematic cross-sectional view showing a state after the semiconductor multilayer structure is formed on the substrate. In the manufacturing method of the compound semiconductor light emitting device of the fourth embodiment, a semiconductor multilayer structure is formed on the substrate 100 without forming irregularities on the surface of the substrate 100. First, the substrate 100 is put into a MOVPE apparatus to form a buffer layer 110, an undoped GaN layer 120, a Si-doped GaN layer 131, and a leak path entire surface layer. Thereafter, the substrate 100 is once taken out of the MOVPE apparatus, and a part of the entire surface of the leak path is removed to form the leak path layer 211.

  Next, the substrate 100 is again put into the MOVPE apparatus, and the n-type layer 141, the light emitting layer 151, and the p-type layer 161 are laminated in this order.

  FIG. 19 is a schematic cross-sectional view showing a state after the p-side contact electrode 411 is formed on the p-type layer. After the p-type layer 161 is formed as described above, the substrate 100 is taken out from the MOVPE apparatus, and heat treatment is performed at 800 ° C. for 5 minutes in a nitrogen gas atmosphere. Furthermore, a layer made of Ag is formed on the surface of the p-type layer 161 by using an electron beam vapor deposition apparatus, and this is patterned by using a normal photolithography method and a wet etching method, as shown in FIG. A p-side contact electrode 411 made of Ag is formed.

  FIG. 20 is a schematic cross-sectional view showing a state after a dielectric film is formed on the p-type layer. After the p-side contact electrode is formed as described above, as shown in FIG. 20, by combining a normal photolithography method, an electron beam evaporation method, and a lift-off method, 400 nm is formed on the surface of the p-type layer 161. A dielectric film 401 having a thickness of 5 mm is formed. The dielectric film 401 is formed so as to cover the end portion of the p-side contact electrode 411.

  FIG. 21 is a schematic cross-sectional view showing a state after the diffusion prevention layer is formed on the upper surfaces of the p-side contact electrode and the dielectric film. A diffusion prevention layer 421 made of TiW is formed on the upper surfaces of the p-side contact electrode 411 and the dielectric film 401 formed as described above by sputtering (FIG. 21).

  FIG. 22 is a schematic cross-sectional view showing a state after bonding a Si substrate having a eutectic solder layer on the diffusion preventing layer. Separately from the substrate formed above, an eutectic solder layer 501 made of AuSn was deposited on the surface of a Si substrate 101 having a thickness of 450 μm, and this was prevented from diffusion as shown in FIG. Crimping is performed so as to be in contact with the layer 421.

  Here, the eutectic bonding metal constituting the eutectic solder layer 501 is not limited to AuSn. For example, one or more metals selected from the group consisting of Au, AuSi, and AuGe or alloys of the metals are used. Can be used.

  FIG. 23 is a schematic cross-sectional view showing a state after the substrate is separated. In FIG. 23, the separated substrate is not shown, and is upside down with respect to FIG. 22 so that the Si substrate 101 is on the lower side. After bonding the Si substrate 101 as described above, UV laser irradiation is performed from the back surface of the substrate 100, that is, the side of the front and back surfaces of the substrate 100 where the semiconductor multilayer structure is not formed.

  The energy of the UV laser is substantially transmitted through the substrate 100 and absorbed by the semiconductor multilayer structure starting from the buffer layer 110. As a result, processing strain is applied to the buffer layer 110 in the vicinity of the substrate 100. When the entire surface of the substrate 100 is scanned with a UV laser, the substrate 100 is separated as shown in FIG.

FIG. 24 is a schematic cross-sectional view showing a state after removing a part of the buffer layer, the undoped GaN layer, and the Si-doped GaN layer. Next, by using an inductively coupled plasma dry etching method using SiCl ₄ gas, as shown in FIG. 24, the buffer layer 110, the undoped GaN layer 120, and a part of the Si doped GaN layer 130 are removed. To do.

FIG. 25 is a schematic cross-sectional view showing a state after removing the side surface of the semiconductor multilayer structure. In addition to the dry etching described above, a part of the diffusion prevention layer 421 can be obtained by combining a normal photolithography method and an inductively coupled plasma type dry etching method using SiCl ₄ gas, as shown in FIG. The Si-doped GaN layer 130, the leak path layer 211, the n-type layer 141, the light-emitting layer 151, and the p-type layer 161 are partially removed until is exposed.

  FIG. 26 is a schematic cross-sectional view showing a state after an n-side pad electrode is formed on the surface of the Si-doped GaN layer 130. Next, as shown in FIG. 26, by combining a normal photolithography method, an electron beam evaporation method, and a lift-off method, the n-side is formed on the surface of the Si-doped GaN layer 130 as shown in FIG. A pad electrode 321 is formed. The thus formed laminate shown in FIG. 17 is divided into chips to obtain the compound semiconductor light emitting device of the fourth embodiment shown in FIG.

  EXAMPLES Hereinafter, although an Example is given and this invention is demonstrated in detail, this invention is not limited to these.

Example 1
In this example, the compound semiconductor light emitting device shown in FIG. 1 was fabricated by the following steps.

First, as shown in FIG. 7, a photoresist mask 600 was formed on a substrate 100 made of sapphire using a normal photolithography method. Thereafter, a part of the substrate 100 was etched with a mixed gas of SiC ₄ and Ar using an inductively coupled plasma type dry etching apparatus. In this way, the surface of the substrate 100 was formed with concavities and convexities having a truncated cone at a pitch of 2 μm. The truncated cone had a lower base diameter of 0.5 μm and an upper base diameter of 0.2 μm.

  Then, the substrate 100 as shown in FIG. 8 was obtained by removing the photoresist mask 600.

Next, the substrate 100 on which the projections and depressions were formed was put into a metal organic vapor phase epitaxy apparatus (hereinafter also referred to as “MOVPE apparatus”), and the semiconductor multilayer structure shown in FIG. 9 was grown. Specifically, first, the substrate 100 was heated to 550 ° C., and then a buffer layer 220 made of undoped GaN was formed to a thickness of 20 nm. Thereafter, the temperature was raised to 1100 ° C., the undoped GaN layer 120 was formed with a thickness of 2 μm, and the Si-doped GaN layer 130 with a Si doping concentration of 5 × 10 ¹⁸ / cm ³ was formed with a thickness of 1.5 μm. .

Thereafter, the temperature in the MOVPE apparatus was lowered to 815 ° C., and a leak path layer 210 made of Si-doped GaN having a Si doping concentration of 5 × 10 ¹⁸ / cm ³ was formed to a thickness of 30 nm.

  Here, the substrate 100 was once taken out from the MOVPE apparatus, and the surface roughness of the leak path layer 210 was measured. As a result, the RMS of the surface of the leak path layer 210 was 10 nm and pits were distributed. Around this pit, doped Si is distributed at a relatively high concentration, and this part serves as a path to release overcurrent when a surge is introduced into the device, improving the electrostatic withstand voltage characteristics. Let

Next, a part of the leak path layer 210 was removed as shown in FIG. 10 by combining a normal photolithography technique and an inductively coupled plasma dry etching technique using SiCl ₄ gas.

Then, the substrate 100 is again put into the MOVPE apparatus, and as shown in FIG. 14, the substrate 100 is first heated to 815 ° C., and then an In _x Ga _1-x N layer (0. 05 ≦ x ≦ 0.15) and an Si-doped GaN layer having a thickness of 2.5 nm, and an n-side superlattice layer 140 having a superlattice structure in which 10 layers are alternately stacked.

Next, the temperature in the MOVPE apparatus is maintained at 815 ° C., and a structure in which an undoped In _0.25 Ga _0.75 N layer having a thickness of 2.5 nm and an undoped GaN layer having a thickness of 2.5 nm are alternately stacked in six layers each. The light emitting layer 150 was formed.

Thereafter, the temperature was raised to 1100 ° C., and an Mg-doped GaN layer 160 with an Mg doping concentration of 5 × 10 ¹⁹ / cm ³ was formed to a thickness of 80 nm. Then, after cooling to room temperature, the substrate was taken out and subjected to heat treatment at 800 ° C. for 5 minutes in nitrogen gas.

  Further, a transparent electrode layer 300 made of ITO was formed on the surface of the Mg-doped GaN layer 160 using a sputtering apparatus. Then, by patterning using a normal photolithography method and a wet etching method, as shown in FIG. 15, the transparent electrode layer 300 is not overlapped with the region of the leak path layer 210 in a plan view from the substrate 100 side. Formed.

Next, by performing a combination of normal photolithography and inductively coupled plasma dry etching using SiCl ₄ gas, as shown in FIG. 16, Mg doped GaN layer 160, light emitting layer 150, n A part of the side superlattice layer 140, the leak path layer 210, and the Si-doped GaN layer 130 was removed, and a part of the Si-doped GaN layer 130 was exposed.

  Thereafter, the p-side pad electrode 310 was formed on the surface of the transparent electrode layer 300 by combining a normal photolithography method, an electron beam evaporation method, and a lift-off method. Using the same method, the n-side pad electrode 320 was formed on the exposed surface of the Si-doped GaN layer 130. Thus, the compound semiconductor light emitting device shown in FIG. 1 was produced.

(Comparative Example 1)
The compound semiconductor of Comparative Example 1 is the same as that of Example 1 except that the step of removing a part of the leak path layer is not performed with respect to the method of manufacturing the compound semiconductor light emitting device of Example 1. A light emitting element was manufactured.

<Characteristic evaluation>
When a current of 60 mA was applied in the forward direction to each of the compound semiconductor light emitting devices of Example 1 and Comparative Example 1, the light emitted with a total radiant flux of 75 mW in Example 1, whereas in Comparative Example 1, , And emitted light with a total radiant flux of 58 mW. In addition, the value which measured the element mounted in TO-18 stem with the integrating sphere was employ | adopted for the total radiant flux. Moreover, when the half value width of the light emission wavelength which the compound-type semiconductor light-emitting device of Example 1 and Comparative Example 1 emits was measured, Example 1 was 18 nm, while Comparative Example 1 was 23 nm.

  From the results as described above, the structure of the leak path layer formed on a part of the semiconductor multilayer structure as in Example 1 is more than the structure of the leak path layer covering the entire surface of the semiconductor multilayer structure as in Comparative Example 1. However, it was found that good light emission characteristics with a high light output and a narrow half width of the wavelength can be obtained.

  This is considered due to the fact that the leak path layer is formed at a relatively low temperature of 815 ° C. in order to develop a desired ESD countermeasure in the leak path layer. That is, since the crystallinity is deteriorated by forming the leak path layer at a low temperature, when the n-side superlattice layer 140 and the light emitting layer 150 are formed thereon, there is in-plane fluctuation in the light emission efficiency and the light emission wavelength of the light emitting layer 150. It is considered that the light output and the half-value width of the light wavelength deteriorated.

  In contrast, the compound-based semiconductor light-emitting device manufactured in Example 1 has a portion of the leak path layer removed and a large proportion of the light-emitting layer formed immediately above the light-emitting layer. The problem of in-plane fluctuation hardly occurs.

  In addition, when the electrostatic withstand voltage of the compound semiconductor light emitting devices of both Example 1 and Comparative Example 1 was measured, the ratio of devices that did not break even when subjected to a 1500 V surge in the human body model was about 96%. It was. Therefore, even when the area of the leak path layer is made smaller than the area of the other layers constituting the semiconductor multilayer structure in a plan view from the upper surface of the compound semiconductor light emitting device, the electrostatic withstand voltage characteristics do not deteriorate. Is clear.

  Although the embodiments and examples of the present invention have been described as described above, it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments and examples.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 10 Buffer layer, 11 Contact layer, 12 1st nESD layer, 13 2nd nESD layer, 14 n-type superlattice layer, 15 Light emitting layer, 16 p-type superlattice layer, 17 p-type GaN layer, 18 Transparent electrode layer , 19 Passivation layer, 20 V layer, 21 Al layer, 22 n-side electrode, 100, 101, 102 substrate, 110 buffer layer, 120 undoped GaN layer, 130, 131 Si-doped GaN layer, 140 n-side superlattice layer, 141 n-type layer, 150, 151 light emitting layer, 160, 161 p-type layer, 190, 191 semiconductor laminated structure, 210a leak path entire surface layer, 210, 211 leak path layer, 220 buffer layer, 300 transparent electrode layer, 310 p-side pad electrode, 311 p-side electrode, 320, 321 n-side pad electrode, 401 dielectric film, 411-side contact Electrode, 421 the diffusion preventing layer, 501 eutectic solder layer, 600 a photoresist mask, 700 microcrystals, 800, 801 current confinement layer.

Claims (13)

A compound-based semiconductor light-emitting device having a substrate and a semiconductor multilayer structure formed on the substrate,
The semiconductor stacked structure includes an n-type layer, a light emitting layer, and a p-type layer in order from the substrate side.
A p-side electrode in contact with the p-type layer;
An n-side electrode in contact with the n-type layer,
The n-type layer has one or more leak path layers having a rougher surface roughness than other layers constituting the semiconductor multilayer structure,
The compound-based semiconductor light-emitting element, wherein the area of the leak path layer is smaller than the area of the other layers constituting the semiconductor multilayer structure in a plan view from the top surface of the compound-based semiconductor light-emitting element. The n-side electrode and the p-side electrode are placed on either one of the front and back surfaces of the substrate,
2. The compound semiconductor light-emitting element according to claim 1, wherein the leak path layer is located between the n-side electrode and the p-side electrode in a plan view from the top surface of the compound semiconductor light-emitting element.   The leak path layer is disposed so that a region where the p-side electrode is disposed and a region where the leak path layer is disposed do not overlap in a plan view from the upper surface of the compound semiconductor light emitting element. 2. The compound semiconductor light emitting device according to 2. The n-side electrode and the p-side electrode are placed on either one of the front and back surfaces of the substrate,
2. The compound semiconductor light-emitting element according to claim 1, wherein the leak path layer is located immediately below the p-side electrode in a plan view from the upper surface of the compound semiconductor light-emitting element.   5. The compound semiconductor light emitting element according to claim 4, having a structure in which current is hardly injected only into the light emitting layer directly below the p-side electrode.   A current confinement layer having low electrical conductivity is provided between the p-side electrode and the surface of the semiconductor multilayer structure directly below the p-side electrode in a region immediately below the p-side electrode of the semiconductor multilayer structure. Item 6. The compound semiconductor light-emitting device according to Item 5. At the interface between the p-side electrode and the p-type layer formed immediately below the p-side electrode, the contact resistance immediately below the p-side electrode is higher than the contact resistance at a portion other than directly below the p-side electrode. And the compound type semiconductor light-emitting device of Claim 5 which is 0.1 ohm-cm < ² > or more. A compound-based semiconductor light-emitting device having a substrate and a semiconductor multilayer structure formed on the substrate,
The semiconductor multilayer structure includes a p-type layer, a light emitting layer, and an n-type layer in order from the substrate side.
A p-side electrode in contact with a surface opposite to the side on which the semiconductor multilayer structure is formed on the front and back of the substrate;
An n-side electrode in contact with the n-type layer,
The n-type layer has one or more leak path layers having a rougher surface roughness than other layers constituting the semiconductor multilayer structure,
In plan view from the top surface of the compound semiconductor light emitting device, the area of the leak path layer is smaller than the area of the other layers constituting the semiconductor multilayer structure, and the leak path layer is formed immediately below the n-side electrode. A compound semiconductor light emitting device.   The compound semiconductor light-emitting element according to claim 8, having a structure in which current is hardly injected only into the light-emitting layer immediately below the n-side electrode.   A current confinement layer having low electrical conductivity is provided between the n-side electrode and the surface of the semiconductor multilayer structure directly below the n-side electrode in a region immediately below the n-side electrode of the semiconductor multilayer structure. Item 10. The compound semiconductor light emitting device according to Item 9. Crystal growing an n-type layer and a leak path layer in this order on a substrate;
Exposing the n-type layer by removing a portion of the leak path layer;
Forming a light-emitting layer and a p-type layer in this order on the leak path layer and the exposed n-type layer in this order.   The compound system according to claim 11, wherein the step of exposing the n-type layer is performed by performing dry etching on a part of the leak path layer using a chlorine-based gas after performing photolithography on the leak path layer. A method for manufacturing a semiconductor light emitting device. Crystal growing an n-type layer on the substrate;
Forming a dielectric film on the n-type layer;
Exposing a portion of the n-type layer by patterning the dielectric film;
Crystal growing a leak path layer on the dielectric film and the exposed n-type layer;
Exposing the n-type layer by removing the dielectric film and the leak path layer formed on the dielectric film by etching;
Forming a light-emitting layer and a p-type layer in this order on the leak path layer and the exposed n-type layer in this order.

Images