JP2012060100A - ウエハレベルパッケージ構造およびその製造方法 - Google Patents
ウエハレベルパッケージ構造およびその製造方法 Download PDFInfo
- Publication number
- JP2012060100A JP2012060100A JP2011056004A JP2011056004A JP2012060100A JP 2012060100 A JP2012060100 A JP 2012060100A JP 2011056004 A JP2011056004 A JP 2011056004A JP 2011056004 A JP2011056004 A JP 2011056004A JP 2012060100 A JP2012060100 A JP 2012060100A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- metal
- groove
- manufacturing
- wafer level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 70
- 229910052751 metal Inorganic materials 0.000 claims abstract description 236
- 239000002184 metal Substances 0.000 claims abstract description 236
- 229920005989 resin Polymers 0.000 claims abstract description 223
- 239000011347 resin Substances 0.000 claims abstract description 223
- 238000005520 cutting process Methods 0.000 claims abstract description 150
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 238000000034 method Methods 0.000 claims abstract description 91
- 230000008569 process Effects 0.000 claims abstract description 42
- 238000011900 installation process Methods 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims description 57
- 238000002161 passivation Methods 0.000 claims description 34
- 239000005011 phenolic resin Substances 0.000 claims description 22
- 238000005240 physical vapour deposition Methods 0.000 claims description 22
- 229920001721 polyimide Polymers 0.000 claims description 20
- 239000009719 polyimide resin Substances 0.000 claims description 19
- 238000007733 ion plating Methods 0.000 claims description 15
- 229920000877 Melamine resin Polymers 0.000 claims description 14
- 229920001807 Urea-formaldehyde Polymers 0.000 claims description 14
- 238000004544 sputter deposition Methods 0.000 claims description 13
- 239000004640 Melamine resin Substances 0.000 claims description 12
- 229920006337 unsaturated polyester resin Polymers 0.000 claims description 11
- 238000007747 plating Methods 0.000 claims description 10
- 238000005299 abrasion Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 66
- 235000012431 wafers Nutrition 0.000 description 58
- 230000015572 biosynthetic process Effects 0.000 description 33
- 239000000463 material Substances 0.000 description 33
- 239000010949 copper Substances 0.000 description 25
- 230000004888 barrier function Effects 0.000 description 22
- 229910052782 aluminium Inorganic materials 0.000 description 19
- 229910000679 solder Inorganic materials 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 15
- 238000010586 diagram Methods 0.000 description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000000605 extraction Methods 0.000 description 13
- 230000001681 protective effect Effects 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 11
- 239000007769 metal material Substances 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- 238000009434 installation Methods 0.000 description 7
- 239000002585 base Substances 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- 150000002739 metals Chemical group 0.000 description 6
- 238000000227 grinding Methods 0.000 description 5
- 238000002156 mixing Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229920001187 thermosetting polymer Polymers 0.000 description 5
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- -1 nitrile rubber-modified phenol Chemical class 0.000 description 4
- 229920003986 novolac Polymers 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 229920003023 plastic Polymers 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000003786 synthesis reaction Methods 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 description 3
- 239000001913 cellulose Substances 0.000 description 3
- 229920002678 cellulose Polymers 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 125000004122 cyclic group Chemical group 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 125000005462 imide group Chemical group 0.000 description 3
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 3
- 229920001568 phenolic resin Polymers 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 2
- YXLXNENXOJSQEI-UHFFFAOYSA-L Oxine-copper Chemical compound [Cu+2].C1=CN=C2C([O-])=CC=CC2=C1.C1=CN=C2C([O-])=CC=CC2=C1 YXLXNENXOJSQEI-UHFFFAOYSA-L 0.000 description 2
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 description 2
- XSQUKJJJFZCRTK-UHFFFAOYSA-N Urea Chemical compound NC(N)=O XSQUKJJJFZCRTK-UHFFFAOYSA-N 0.000 description 2
- MBHRHUJRKGNOKX-UHFFFAOYSA-N [(4,6-diamino-1,3,5-triazin-2-yl)amino]methanol Chemical compound NC1=NC(N)=NC(NCO)=N1 MBHRHUJRKGNOKX-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000004202 carbamide Substances 0.000 description 2
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006482 condensation reaction Methods 0.000 description 2
- 150000001923 cyclic compounds Chemical class 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- VKYKSIONXSXAKP-UHFFFAOYSA-N hexamethylenetetramine Chemical compound C1N(C2)CN3CN1CN2C3 VKYKSIONXSXAKP-UHFFFAOYSA-N 0.000 description 2
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- QQVIHTHCMHWDBS-UHFFFAOYSA-N isophthalic acid Chemical compound OC(=O)C1=CC=CC(C(O)=O)=C1 QQVIHTHCMHWDBS-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- FPYJFEHAWHCUMM-UHFFFAOYSA-N maleic anhydride Chemical compound O=C1OC(=O)C=C1 FPYJFEHAWHCUMM-UHFFFAOYSA-N 0.000 description 2
- JDSHMPZPIAZGSV-UHFFFAOYSA-N melamine Chemical compound NC1=NC(N)=NC(N)=N1 JDSHMPZPIAZGSV-UHFFFAOYSA-N 0.000 description 2
- WSFSSNUMVMOOMR-NJFSPNSNSA-N methanone Chemical compound O=[14CH2] WSFSSNUMVMOOMR-NJFSPNSNSA-N 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 239000000049 pigment Substances 0.000 description 2
- 238000012643 polycondensation polymerization Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000002990 reinforced plastic Substances 0.000 description 2
- PMJHHCWVYXUKFD-SNAWJCMRSA-N (E)-1,3-pentadiene Chemical compound C\C=C\C=C PMJHHCWVYXUKFD-SNAWJCMRSA-N 0.000 description 1
- IAYPIBMASNFSPL-UHFFFAOYSA-N Ethylene oxide Chemical group C1CO1 IAYPIBMASNFSPL-UHFFFAOYSA-N 0.000 description 1
- DHMQDGOQFOQNFH-UHFFFAOYSA-N Glycine Natural products NCC(O)=O DHMQDGOQFOQNFH-UHFFFAOYSA-N 0.000 description 1
- 239000004471 Glycine Substances 0.000 description 1
- 229920001410 Microfiber Polymers 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 239000003377 acid catalyst Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 125000000217 alkyl group Chemical group 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical group C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004312 hexamethylene tetramine Substances 0.000 description 1
- 235000010299 hexamethylene tetramine Nutrition 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000007737 ion beam deposition Methods 0.000 description 1
- 238000001659 ion-beam spectroscopy Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000003658 microfiber Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 150000002989 phenols Chemical class 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 230000000379 polymerizing effect Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 229920003987 resole Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 150000005846 sugar alcohols Polymers 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229920006305 unsaturated polyester Polymers 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05164—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05171—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05181—Tantalum [Ta] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】ウエハレベルパッケージ製造方法は、例えば、基板450の表面に、配線が形成される溝462を含む絶縁性の第1の樹脂460を形成する樹脂形成工程400と、第1の樹脂460の表面に、配線の一部となる第1の金属470を、物理気相成長によって成膜する第1の成膜工程410と、第1の金属470の表面に、配線の一部となる、第1の金属470より硬度が低い第2の金属480を、更に成膜する第2の成膜工程420と、溝462の側面において第1の金属470が成膜されていない場所または薄くなっている場所に該当する高さH0、H1に切削刃490を設置する設置工程430と、切削刃490を走査することにより、少なくとも第1の樹脂460を切削する切削工程440とを含む。
【選択図】図19
Description
図17は本発明によるウエハレベルパッケージ製造方法の第2〜第7の実施形態に共通のプロセスフローを示すフローチャートである。尚、前述の第1の実施形態も、図17のプロセスフローに準じている。図18は図17のフローチャートに沿って製造されるウエハレベルパッケージの変化の一例を示す概略図である。
図19は本発明によるウエハレベルパッケージ製造方法の第2の実施形態を示す図である。図20は、図19においてウエハレベルパッケージ製造方法が完了した結果得られる、ウエハレベルパッケージの中間体を示す図である。
本実施形態の特徴は、上記のような成膜が行われた後に、設置工程430において、例えば第1の金属470が成膜されていない、厚みがゼロの場所に該当する高さH0の切削ラインに沿って切削刃490を設置し、図17に示す切削工程440にて基板450の表面に沿って切削刃490を走査することによって切削を行うことである。したがって切削刃490が切削するのは、最も軟らかい第1の樹脂460と、第1の金属470よりも相対的に硬度の低い第2の金属480の2種類だけである。尚、第2の金属480の成膜の厚さは任意であり、切削刃490の設置高さHとは直接的な関連はない。例えば、第2の金属480の成膜の厚さが薄い場合、高さH0の切削ラインで切削刃490が切削するのは、第1の樹脂460だけの場合もある。例えば、第2の金属480の成膜の厚さが薄い場合、高さH1の切削ラインは、溝462に形成された第2の金属480の表面である場合もある。尚、「最も軟らかい」とは、切削される対象の複数の材料のうちで最も軟らかい材質であるという意味である。尚、切削刃490を固定して基板450を走査する、または両者をそれぞれ独立して走査する、ことも本願の技術範囲に含まれる。
ただし、設置工程430および切削工程440では、溝462の側面に成膜された最も硬度の高い第1の金属470の厚さが小さければ、その高さを狙って切削してもよい。例えば図19の領域A拡大図に示すように、高さH1では、第1の金属470の成膜厚さT1は、第1の樹脂460の上面に成膜された同じ第1の金属470の厚みT2(図19の領域B拡大図参照)よりも薄くなっている。この高さH1の切削ラインで切削してもよい。
さらに本実施形態では、第1の樹脂460が長方形の断面を有するため、第1の樹脂460の側面は垂直な面となる。したがって、第1の樹脂460の側面を下方にゆくに従って、第1の金属470の成膜厚さが次第に小さくなりやがてゼロになり、本実施形態による切削工程440を適用可能な構造が実現できる。
特許文献1を比較例として本発明の実施形態と比較する。特許文献1の技術では、同文献の図10及び段落のように、SiO2層間絶縁膜22のエッジ面上であって、バリヤメタル24との界面よりやや下がった位置に切削刃6を当接させ、X方向に切削することを開示するものの、バリヤメタル24の硬度と切削刃の劣化(摩耗)についての課題は一切開示されておらず、切削刃の劣化抑止を視点とした切削刃の高さについての検討は一切されておらず、開示も示唆もない。更に後述する層間絶縁膜22の材質と切削刃の関係の検討についても、一切開示示唆されていない。
既に述べたように、相対的に硬度の高い第1の金属470をより多く切削するほど、言い換えれば、切削ラインの線分長に占める第1の金属470の線分長の比率が大きいほど、切削刃490の磨耗が激しいため、第1の金属470の厚みが薄い所あるいはゼロになる所を狙って切削し、第1の金属470の切削量を可能な限り抑制するのが本発明の各実施形態の一つの特徴である。以下、物理定数と切削刃490の磨耗に関して考察する。
既に述べたように、第1の樹脂460は、フェノール樹脂のほか、不飽和ポリエステル樹脂、メラミン樹脂またはユレア樹脂を主成分としてもよい。切削刃による切削は切削時の局部発熱で塑性変形を起こさない、熱硬化樹脂が望ましいからである。また、切削刃の切れ味を良くするためには、第1の樹脂460は、適度な弾性率を持ち、限界応力に対する歪みが小さく強度が比較的低い樹脂が良好と考えられるからである。
図19に示すように、基板450は、少なくともその表面の一部にパッシベーション膜444を有し、パッシベーション膜444が第1の樹脂460と接している。パッシベーション膜444と第1の樹脂460とが接することによって第1の樹脂460の密着性(接着力)が向上し、切削性能がより向上する。
図25は本発明によるウエハレベルパッケージ製造方法の第3の実施形態を示す図であり、図18(c)に示した第1の樹脂452Aに対して、第1の成膜工程410、第2の成膜工程420、設置工程430および切削工程440を施したものである。図26は、図25においてウエハレベルパッケージ製造方法が完了した結果得られる、ウエハレベルパッケージの中間体を示す図である。
図27は本発明によるウエハレベルパッケージ製造方法の第4の実施形態を示す図である。図28は、図27においてウエハレベルパッケージ製造方法が完了した結果得られる、ウエハレベルパッケージの中間体を示す図である。
図29は本発明によるウエハレベルパッケージ製造方法の第5の実施形態を示す図である。本実施形態では、図17の樹脂形成工程410において、第2の実施形態と同様に、長方形の断面を有する第1の樹脂460を残存させるように溝462を形成した。その後、溝462に対応した位置に開口部512を有するメタルマスク510を介して第1の成膜工程410を行った。その結果、図29に示すように、第1の樹脂460の上に位置するメタルマスク510および溝462に、第1の金属470が成膜される。メタルマスク510を用いているため溝462の側面に成膜される第1の金属470は少ない。ただし側面に全く成膜されないわけではなく、溝462の底面付近では、側面にも第1の金属470が成膜される。
図32は本発明によるウエハレベルパッケージ製造方法の第6の実施形態を示す図である。本実施形態でも、図17の第1の成膜工程410において、第2の実施形態と同様に、長方形の断面を有する第1の樹脂460を残存させるように溝462を形成した。その後、溝462に対応した位置に開口部512を有するメタルマスク510を介して第1の成膜工程410および第2の成膜工程420を行った。メタルマスク510のセットとリフトオフは、一回である。その結果、図32に示すように、第1の樹脂460の上に位置するメタルマスク510および溝462に、第1および第2の金属470、480が成膜される。
これまでの各実施形態における基板450は、回路及び回路へ信号を入出力する内部端子電極を含む半導体基板(例えばシリコンウエハ)を想定していた。すなわち各チップにダイシングする前のウエハである。
図33は本発明によるウエハレベルパッケージ製造方法の第7の実施形態を示す図であり、本実施形態で用いる基板の平面図である。図34は図33の断面図である。図34(a)は図33のX−X断面図であり、図34(b)は図34(a)の領域C拡大図である。本実施形態では、第1〜第6の実施形態と異なり、単なる半導体基板450(シリコンウエハ)でなく、ファンアウト用WLP基板520に対して、図17に示したウエハレベルパッケージ製造方法を適用している。
以下、付記として、本発明による半導体装置を付記として開示する。
半導体装置は、半導体基板450と、前記半導体基板450の表面に形成され、配線が形成される溝462を含む絶縁性の第1の樹脂層460と、前記配線として前記溝462に形成された金属層と、を備え、前記第1の樹脂層460は、フェノール樹脂、不飽和ポリエステル樹脂、メラミン樹脂、またはユレア樹脂を主成分とする。
付記1に記載の半導体装置において、前記半導体基板450は、少なくともその表面の一部にパッシベーション膜444を有し、パッシベーション膜444が前記第1の樹脂層460と接する。
付記2に記載の半導体装置において、前記パッシベーション膜444は、ポリイミド樹脂を主成分とする。
付記3に記載の半導体装置において、前記第1の樹脂層460は、前記ポリイミド樹脂に対して接着する樹脂である。
付記4に記載の半導体装置において、前記第1の樹脂層460は、感光性樹脂である。
付記1乃至5のいずれか一項に記載の半導体装置において、前記金属層は、バリアメタルである第1の金属470と、CuまたはAlである第2の金属480とを含む。
付記5に記載の半導体装置において、前記第1の金属470は、Ti、Cr、TaまたはPdである。
付記1乃至7のいずれか一項に記載の半導体装置において、前記第1の樹脂層460の断面は、前記半導体基板450の表面を基準として長方形、正テーパ、または逆テーパである。
付記1から3のいずれか1項に記載の半導体装置において、前記半導体基板1は更に、回路及びその回路へ信号を入出力する内部端子電極2と、前記半導体基板1のチップに相当する領域内にファンインとして設けられた外部端子電極9とを含み、前記配線は、前記内部端子電極2と、前記外部端子電極9とを接続する。
付記1から3のいずれか1項に記載の半導体装置において、前記半導体基板520は、回路及びその回路へ信号を入出力する内部端子電極522、523を含む半導体チップ524と、その半導体チップ524の少なくとも側面を覆う絶縁性の第2の樹脂層526と、前記半導体チップ524の領域外の第2の樹脂層526にファンアウトとして設けられた外部端子電極(半田ボール)540、550とを含み、前記第1の樹脂層460は、前記半導体チップ524及びそのチップ524の領域外の前記第2の樹脂層526の表面に形成され、前記配線(第1の金属(例えばTi)470と、第2の金属(例えばCu)480)は、前記内部端子電極522、523と、前記外部端子電極540、550を接続する。
2 チップ取り出し電極(内部端子電極)
3 パッシベーション膜
4 バリア金属配線
4b 溝内部のバリア金属材料
4u 樹脂上面のバリア金属材料
5 アルミニュウム配線
5b 溝内部のアルミニュウム配線
5u 樹脂上面のアルミニュウム配線
6 配線層を形成する溝を作るための樹脂
6a 感光された樹脂
7 バリア金属配線
8 銅配線
9 半田ボール
10 シリコンウエハ
11 保護絶縁膜
21 配線層(第1の配線層)
22 配線層(第2の配線層)
22s 配線層の側面
200 マスク
201 溝
202 感光用の光
203 マスク開口部
300 マスク
301 マスク開口部
400 …樹脂形成工程
410 …第1の成膜工程
420 …第2の成膜工程
430 …設置工程
440 …切削工程
442、522、523 …内部端子電極
444、528 …パッシベーション膜
446 …ナノスタンパ
450 …基板
452、452A、460、465、500 …第1の樹脂
461 …ポリイミド樹脂
454、456、462、502 …溝
470 …第1の金属
480 …第2の金属
490 …切削刃(バイト)
492 …有機物バルク部
494 …クレーズ
496 …フィブリル
498 …ヴォイド
510 …メタルマスク
512 …開口部
520 …ファンアウト用WLP基板
524 …半導体チップ
526 …第2の樹脂
530 …半導体ウエハ
532 …チップ固定テープ
540、550 …外部端子電極
560 …ソルダレジスト
Claims (20)
- 基板の表面に、配線が形成される溝を含む絶縁性の第1の樹脂を形成する樹脂形成工程と、
前記第1の樹脂の表面に、前記配線の一部となる第1の金属を、物理気相成長によって成膜する第1の成膜工程と、
前記第1の金属の表面に、前記配線の一部となる、前記第1の金属より硬度が低い第2の金属を成膜する第2の成膜工程と、
前記溝の側面に前記第1の金属が成膜されていない高さ、または、前記溝の側面に成膜された前記第1の金属の厚みが、前記第1の樹脂の上面に成膜された前記第1の金属の厚みよりも薄い場所に該当する高さ、若しくは前記溝の底面に成膜された前記第1の金属の厚みよりも薄い場所に該当する高さに、切削刃を設置する設置工程と、
前記切削刃を走査することにより、少なくとも前記第1の樹脂を切削する切削工程と、を含む、ことを特徴とするウエハレベルパッケージの製造方法。 - 前記第1の樹脂は、フェノール樹脂、不飽和ポリエステル樹脂、メラミン樹脂、またはユレア樹脂を主成分とする、ことを特徴とする請求項1に記載のウエハレベルパッケージの製造方法。
- 前記基板は、少なくともその表面の一部にパッシベーション膜を有し、該パッシベーション膜が前記第1の樹脂と接する、ことを特徴とする請求項2に記載のウエハレベルパッケージの製造方法。
- 前記パッシベーション膜は、ポリイミド樹脂を主成分とする、ことを特徴とする請求項3に記載のウエハレベルパッケージの製造方法。
- 前記第1の成膜工程は、前記溝に対応した位置に開口部を有するメタルマスクを用いたイオンプレーティング法によって行う、ことを特徴とする請求項1乃至4のいずれか一項に記載のウエハレベルパッケージの製造方法。
- 前記第2の成膜工程は、物理気相成長によって行う、ことを特徴とする請求項1乃至5のいずれか一項に記載のウエハレベルパッケージの製造方法。
- 前記第2の成膜工程は、前記溝に対応した位置に開口部を有するメタルマスクを用いたイオンプレーティング法によって行う、ことを特徴とする請求項6に記載のウエハレベルパッケージの製造方法。
- 前記第2の成膜工程は、スパッタリング法によって行う、ことを特徴とする請求項6に記載のウエハレベルパッケージの製造方法。
- 前記第2の成膜工程は、メッキ法によって行う、ことを特徴とする請求項1乃至5のいずれか一項に記載のウエハレベルパッケージの製造方法。
- 前記樹脂形成工程では、前記溝に隣接する前記第1の樹脂の断面を、前記基板の表面を基準として長方形または正テーパに形成する、ことを特徴とする請求項5に記載のウエハレベルパッケージの製造方法。
- 前記開口部の幅は、前記溝の幅よりも狭い、ことを特徴とする請求項5または10に記載のウエハレベルパッケージの製造方法。
- 前記樹脂形成工程では、前記溝に隣接する前記第1の樹脂の断面を、前記基板の表面を基準として逆テーパに形成する、ことを特徴とする請求項1乃至4のいずれか一項に記載のウエハレベルパッケージの製造方法。
- 前記第1の成膜工程は、スパッタリング法またはイオンプレーティング法によって行う、ことを特徴とする請求項12に記載のウエハレベルパッケージの製造方法。
- 前記第2の成膜工程は、物理気相成長によって行う、ことを特徴とする請求項12または13に記載のウエハレベルパッケージの製造方法。
- 前記第2の成膜工程は、メッキ法によって行う、ことを特徴とする請求項12または13に記載のウエハレベルパッケージの製造方法。
- 前記第2の成膜工程は、スパッタリング法またはイオンプレーティング法によって行う、ことを特徴とする請求項14に記載のウエハレベルパッケージの製造方法。
- 前記切削刃を走査することにより、前記第2の金属を切削する、ことを特徴とする請求項1乃至16のいずれか一項に記載のウエハレベルパッケージの製造方法。
- 前記切削刃を走査することにより、前記第1の樹脂の上面または前記溝の底面に成膜された前記第1の金属の厚みよりも薄い前記第1の金属を切削する、ことを特徴とする請求項1乃至17のいずれか一項に記載のウエハレベルパッケージの製造方法。
- 前記基板は、回路及び該回路へ信号を入出力する内部端子電極を含む半導体基板であり、
前記溝に成膜された前記第1の金属および前記第2の金属は、前記内部端子電極と、前記半導体基板のチップに相当する領域内にファンインとして設けられた外部端子電極と、を接続する配線層を形成する、ことを特徴とする請求項1乃至18のいずれか一項に記載のウエハレベルパッケージの製造方法。 - 前記基板は、回路及び該回路へ信号を入出力する内部端子電極を含む半導体チップと、該半導体チップの少なくとも側面を覆う絶縁性の第2の樹脂と、を含み、
前記溝に成膜された前記第1の金属および前記第2の金属は、前記内部端子電極と、前記半導体チップの領域外の第2の樹脂にファンアウトとして設けられた外部端子電極と、を接続する配線層を形成する、ことを特徴とする請求項1乃至18のいずれか一項に記載のウエハレベルパッケージの製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011056004A JP5189665B2 (ja) | 2010-08-09 | 2011-03-14 | ウエハレベルパッケージ構造およびその製造方法 |
US13/418,134 US20130034934A1 (en) | 2010-08-09 | 2012-03-12 | Wafer level package structure and method for manufacturing the same |
CN2012100661895A CN102683226A (zh) | 2011-03-14 | 2012-03-14 | 晶圆级封装结构及其制造方法 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010179072 | 2010-08-09 | ||
JP2010179072 | 2010-08-09 | ||
JP2011056004A JP5189665B2 (ja) | 2010-08-09 | 2011-03-14 | ウエハレベルパッケージ構造およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012060100A true JP2012060100A (ja) | 2012-03-22 |
JP5189665B2 JP5189665B2 (ja) | 2013-04-24 |
Family
ID=46056777
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011056004A Active JP5189665B2 (ja) | 2010-08-09 | 2011-03-14 | ウエハレベルパッケージ構造およびその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20130034934A1 (ja) |
JP (1) | JP5189665B2 (ja) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012190854A (ja) * | 2011-03-08 | 2012-10-04 | Toshiba Corp | 半導体装置及びその配線の形成方法 |
JP2014187339A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187333A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187334A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187338A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187337A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187336A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187335A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2015119061A (ja) * | 2013-12-19 | 2015-06-25 | 豊田合成株式会社 | 半導体装置の製造方法 |
KR20170130279A (ko) | 2016-05-18 | 2017-11-28 | 도오꾜오까고오교 가부시끼가이샤 | 봉지체의 제조 방법, 및 적층체 |
WO2018079046A1 (ja) * | 2016-10-28 | 2018-05-03 | 株式会社村田製作所 | 電子部品装置 |
JPWO2017038110A1 (ja) * | 2015-08-28 | 2018-06-07 | 日立化成株式会社 | 半導体装置及びその製造方法 |
JP2020150095A (ja) * | 2019-03-13 | 2020-09-17 | イビデン株式会社 | ガラス回路基板の製造方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9269681B2 (en) * | 2012-11-16 | 2016-02-23 | Qualcomm Incorporated | Surface finish on trace for a thermal compression flip chip (TCFC) |
TWI562255B (en) * | 2015-05-04 | 2016-12-11 | Chipmos Technologies Inc | Chip package structure and manufacturing method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000277608A (ja) * | 1999-03-24 | 2000-10-06 | Rohm Co Ltd | 半導体装置の製造方法 |
JP2006216768A (ja) * | 2005-02-03 | 2006-08-17 | Sony Corp | 半導体装置およびその製造方法 |
EP2075825A1 (en) * | 2007-12-28 | 2009-07-01 | Interuniversitaire Microelectronica Centrum vzw ( IMEC) | semiconductor device comprising conductive structures and a planarized surface |
JP2009246218A (ja) * | 2008-03-31 | 2009-10-22 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
-
2011
- 2011-03-14 JP JP2011056004A patent/JP5189665B2/ja active Active
-
2012
- 2012-03-12 US US13/418,134 patent/US20130034934A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000277608A (ja) * | 1999-03-24 | 2000-10-06 | Rohm Co Ltd | 半導体装置の製造方法 |
JP2006216768A (ja) * | 2005-02-03 | 2006-08-17 | Sony Corp | 半導体装置およびその製造方法 |
EP2075825A1 (en) * | 2007-12-28 | 2009-07-01 | Interuniversitaire Microelectronica Centrum vzw ( IMEC) | semiconductor device comprising conductive structures and a planarized surface |
JP2009246218A (ja) * | 2008-03-31 | 2009-10-22 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012190854A (ja) * | 2011-03-08 | 2012-10-04 | Toshiba Corp | 半導体装置及びその配線の形成方法 |
JP2014187339A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187333A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187334A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187338A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187337A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187336A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2014187335A (ja) * | 2013-03-25 | 2014-10-02 | Disco Abrasive Syst Ltd | ウエハレベルパッケージ構造およびその製造方法 |
JP2015119061A (ja) * | 2013-12-19 | 2015-06-25 | 豊田合成株式会社 | 半導体装置の製造方法 |
JPWO2017038110A1 (ja) * | 2015-08-28 | 2018-06-07 | 日立化成株式会社 | 半導体装置及びその製造方法 |
US10388608B2 (en) | 2015-08-28 | 2019-08-20 | Hitachi Chemical Company, Ltd. | Semiconductor device and method for manufacturing same |
JP2020161848A (ja) * | 2015-08-28 | 2020-10-01 | 日立化成株式会社 | 半導体装置及びその製造方法 |
KR20170130279A (ko) | 2016-05-18 | 2017-11-28 | 도오꾜오까고오교 가부시끼가이샤 | 봉지체의 제조 방법, 및 적층체 |
WO2018079046A1 (ja) * | 2016-10-28 | 2018-05-03 | 株式会社村田製作所 | 電子部品装置 |
CN109844935A (zh) * | 2016-10-28 | 2019-06-04 | 株式会社村田制作所 | 电子部件装置 |
US10804196B2 (en) | 2016-10-28 | 2020-10-13 | Murata Manufacturing Co., Ltd. | Electronic component device |
CN109844935B (zh) * | 2016-10-28 | 2023-01-06 | 株式会社村田制作所 | 电子部件装置 |
JP2020150095A (ja) * | 2019-03-13 | 2020-09-17 | イビデン株式会社 | ガラス回路基板の製造方法 |
JP7227798B2 (ja) | 2019-03-13 | 2023-02-22 | イビデン株式会社 | ガラス回路基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5189665B2 (ja) | 2013-04-24 |
US20130034934A1 (en) | 2013-02-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5189665B2 (ja) | ウエハレベルパッケージ構造およびその製造方法 | |
US7348210B2 (en) | Post bump passivation for soft error protection | |
US7208337B2 (en) | Method of forming light emitting devices including forming mesas and singulating | |
US7071024B2 (en) | Method for packaging a microelectronic device using on-die bond pad expansion | |
US7893525B2 (en) | Semiconductor device having an adhesive portion with a stacked structure and method for manufacturing the same | |
KR102377281B1 (ko) | 반도체 장치의 제조 방법 | |
Lu et al. | Asymmetric wafer-level polyimide and Cu/Sn hybrid bonding for 3-D heterogeneous integration | |
JP6425062B2 (ja) | 絶縁樹脂シート、並びにそれを用いた回路基板および半導体パッケージ | |
CN103123917A (zh) | 导电结构及其形成方法 | |
TW201523719A (zh) | 半導體封裝件之製造方法 | |
JP2014187339A (ja) | ウエハレベルパッケージ構造およびその製造方法 | |
TW201307184A (zh) | 在晶圓層級封裝中用於高密度電感與重分配的薄膜結構 | |
WO2013157080A1 (ja) | 半導体装置およびその製造方法 | |
US20100112786A1 (en) | Method of manufacturing semiconductor device | |
JP3870876B2 (ja) | 半導体装置の製造方法 | |
JP2014187336A (ja) | ウエハレベルパッケージ構造およびその製造方法 | |
JP3855900B2 (ja) | 半導体装置の製造方法 | |
JP2014187337A (ja) | ウエハレベルパッケージ構造およびその製造方法 | |
TWI742749B (zh) | 封裝結構及其形成方法 | |
JP2014187333A (ja) | ウエハレベルパッケージ構造およびその製造方法 | |
US11227775B2 (en) | Method of fabricating carrier for wafer level package by using lead frame | |
JP2014187334A (ja) | ウエハレベルパッケージ構造およびその製造方法 | |
JP2014187335A (ja) | ウエハレベルパッケージ構造およびその製造方法 | |
US10418316B1 (en) | Semiconductor substrate, semiconductor package structure and method of manufacturing a semiconductor device | |
JP2014187338A (ja) | ウエハレベルパッケージ構造およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120110 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120312 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20120413 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20120413 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120626 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120920 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20121001 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130108 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130124 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160201 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5189665 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160201 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |