JP2012059877A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device including a new manufacturing technique of a mask.SOLUTION: A manufacturing method of a semiconductor device comprises the steps of: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; applying plasma treatment to a side portion of the patterned first mask film to change the side portion to an altered layer; forming a second mask film covering an upper portion and the side portion of the first mask film after the plasma treatment; removing the second mask film formed above the first mask film while leaving the second mask film formed on the side portion by etching the second mask film; removing the altered layer after the etching of the second mask film; and etching the first film using the remaining first mask film and second mask film as a mask after the removal of the altered layer.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In order to form a circuit pattern of a semiconductor device, etching using a mask is performed. With the miniaturization of circuit patterns, masks have also been miniaturized.

JP 2009-218574 A

  An object of the present invention is to provide a method of manufacturing a semiconductor device including a novel mask manufacturing technique.

  According to an aspect of the present invention, a step of forming a first film above a semiconductor substrate, a step of forming a first mask film above the first film, and patterning the first mask film. A step of performing plasma treatment on a side portion of the patterned first mask film to convert the side portion into a deteriorated layer; and after the plasma treatment, an upper portion of the first mask film and the side portion. Forming a second mask film that covers the first mask film, and etching the second mask film to leave the second mask film formed on the side portion, while forming the second mask film on the first mask film. A step of removing the second mask film; a step of removing the altered layer after etching of the second mask film; and a portion of the first mask film remaining after removing the altered layer, and the first Using the two mask films as a mask, the first film The method of manufacturing a semiconductor device having a step of etching is provided.

  A mask pattern in which the first mask film and the second mask film are arranged across the altered layer formation region can be formed. For example, it can be applied to fine mask pattern formation. Further, for example, by adjusting the thickness of the deteriorated layer, the gap width between the first mask film and the second mask film can be adjusted, and the mask pattern shape can be easily controlled.

1AP, FIG. 1AX, and FIG. 1AY1 to FIG. 1AY3 are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the first embodiment. 1BP, FIG. 1BX, and FIG. 1BY1 to FIG. 1BY3 are a schematic plan view and a cross-sectional view showing the main steps of the semiconductor device manufacturing method according to the first embodiment. 1CP, FIG. 1CX, and FIG. 1CY1 to FIG. 1CY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the first embodiment. FIG. 1DP and FIG. 1DX are a schematic plan view and a cross-sectional view showing the main steps of the semiconductor device manufacturing method according to the first embodiment. 1EP and FIG. 1EX are a schematic plan view and a cross-sectional view showing the main steps of the semiconductor device manufacturing method according to the first embodiment. 1FP, FIG. 1FX, and FIG. 1FY1 to FIG.1FY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the first embodiment. 1GP, FIG. 1GX, and FIG. 1GY1 to FIG. 1GY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the first embodiment. 1HP, FIG. 1HX, and FIG. 1HY1 to FIG. 1HY3 are a schematic plan view and a cross-sectional view showing the main steps of the semiconductor device manufacturing method according to the first embodiment. 1IP, FIG. 1IX, and FIG. 1IY1 to FIG. 1IY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the first embodiment. 1JP, FIG. 1JX, and FIG. 1JY1 to FIG. 1JY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the first embodiment. 1KP, FIG. 1KX, and FIG. 1KY1 to FIG. 1KY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the first embodiment. 1LP, FIG. 1LX, and FIG. 1LY1 to FIG. 1LY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the first embodiment. 1MP, FIG. 1MX, and FIG. 1MY1 to FIG. 1MY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the first embodiment. 1NP, FIG. 1NX, and FIG. 1NY1 to FIG. 1NY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the first embodiment. 1OP, FIG. 1OX, and FIG. 1OY1 to FIG. 1OY3 are a schematic plan view and a cross-sectional view showing the main steps of the semiconductor device manufacturing method according to the first embodiment. FIG. 1PP, FIG. 1PX, FIG. 1PY1 to FIG. 1PY3 are a schematic plan view and a cross-sectional view showing the main steps of the semiconductor device manufacturing method of the first embodiment. 1QP, FIG. 1QX, and FIG. 1QY1 to FIG. 1QY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the first embodiment. 2AP, FIG. 2AX, and FIG. 2AY1 to FIG. 2AY3 are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method of the second embodiment. 2BP, FIG. 2BX, and FIG. 2BY1 to FIG. 2BY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the second embodiment. 2CP, FIG. 2CX, and FIG. 2CY1 to FIG. 2CY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the second embodiment. 2DP, FIG. 2DX, and FIG. 2DY1 to FIG. 2DY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the second embodiment. 2EP, FIG. 2EX, and FIG. 2EY1 to FIG. 2EY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the second embodiment. 2FP, FIG. 2FX, and FIG. 2FY1 to FIG. 2FY3 are a schematic plan view and a cross-sectional view showing main steps of the semiconductor device manufacturing method according to the second embodiment.

  First, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described. In the first embodiment, a static random access memory (SRAM) is manufactured, and the patterning for forming the gate electrode of the MOS transistor will be described in detail among the manufacturing steps of the SRAM circuit.

  1A to 1Q are a schematic plan view and a schematic cross-sectional view showing the main steps of the semiconductor device manufacturing method according to the first embodiment. For example, “P” is added to the plan view as shown in “FIG. 1AP”, and “X” is added to the cross-sectional view in the horizontal direction along the alternate long and short dash line X in the plan view as shown in FIG. 1AX. Then, cross-sectional views in the vertical direction of the drawing along the alternate long and short dash lines Y1, Y2, and Y3 in the plan view, for example, “Y1”, “Y2”, and “Y3” as shown in FIG. 1AY1, FIG. 1AY2, and FIG. ".

  In order to avoid complicated explanation, a plan view with “P” and cross-sectional views with “X”, “Y1”, “Y2”, “Y3” are collectively called as a group of figures. For example, FIG. 1AP, FIG. 1AX, and FIGS. 1AY1 to 1AY3 are referred to as FIG. 1A. This method of explanation is the same in the second embodiment described later. 1D and 1E show only a plan view and a cross-sectional view in the X direction.

  Reference is made to FIG. 1A. An active region is defined by forming an element isolation insulating film on the semiconductor substrate 1 (for example, a p-type silicon substrate) by, for example, shallow trench isolation (STI).

  A photoresist film is formed on the semiconductor substrate 1 by, for example, spin coating. An opening for exposing an active region for forming the p-type MOS transistor is formed in the photoresist film by photolithography. Using this photoresist film as a mask, an n-type well nw is formed by introducing an n-type impurity into the active region where the p-type MOS transistor is to be formed, for example, by ion implantation. The photoresist film used for forming the n-type well nw is removed by ashing.

  A photoresist film is formed on the semiconductor substrate 1 by, for example, spin coating. An opening for exposing an active region for forming the n-type MOS transistor is formed in the photoresist film by photolithography. Using this photoresist film as a mask, p-type impurities are introduced into the active region for forming the n-type MOS transistor, for example, by ion implantation to form a p-type well pw. The photoresist film used for forming the p-type well pw is removed by ashing.

  A p-type MOS transistor formation region (n-type well nw) elongated in the X direction and an n-type MOS transistor formation region (p-type well pw) are arranged side by side in the Y direction.

  Refer to FIG. 1B. On the semiconductor substrate 1, for example, a silicon oxide film having a thickness of 1.5 nm is formed by thermal oxidation to form the gate insulating film 2.

  Reference is made to FIG. 1C. A conductive material is deposited on the gate insulating film 2, and a polysilicon film having a thickness of 100 nm is deposited by, for example, chemical vapor deposition (CVD) to form the gate electrode film 3.

  A mask film 4 is formed on the gate electrode film 3. The mask film 4 is, for example, a SiCOH film, and is formed, for example, by coating nanoclustering silica (NCS), which is a porous silica-based low dielectric constant material, by coating. The film thickness of the mask film 4 is, for example, 100 nm.

  Reference is made to FIG. 1D. An organic material antireflection film BARK1 is formed on the mask film 4 by coating. A photoresist film is formed on the antireflection film BARK1 by coating. A pattern is transferred to the photoresist film by photolithography to form a resist pattern RP1. The thickness of the antireflection film BARK1 is about 70 nm, for example, and the thickness of the resist pattern RP1 is about 150 nm, for example.

  The resist pattern RP1 is for forming a mask for patterning in the width direction (X direction) of the gate electrode. As shown in FIG. 1DP, the resist pattern RP1 defines an elongated opening OP1 in the length direction (Y direction) of the gate electrode. The width of the opening OP1 is equal to the width of the gate electrode, for example, 50 nm. The width of each part of the resist pattern RP1 is equal to the width of the gap from one gate electrode to the next adjacent gate electrode, for example, 190 nm.

  Reference is made to FIG. 1E. The antireflection film BARK1 is etched using the resist pattern RP1 as a mask, and the mask film 4 is etched using the resist pattern RP1 and the antireflection film BARK1 as a mask until the gate electrode film 3 is exposed.

Etching of the mask film 4 is performed in a vacuum chamber using, for example, a parallel plate type dry etching apparatus. The substrate temperature during etching is, for example, about 25 ° C. For example, CF ₄ , CHF ₃ , and Ar can be used as the etching gas.

Specifically, the gas ratios are combined in the order of CF ₄ , CHF ₃ , and Ar in the order of 50 to 300, 10 to 100, and 0 to 1000, and the total flow rate of the mixed gas is set to a range of 200 sccm to 1000 sccm. The pressure in the chamber is, for example, 10 mTorr to 300 mTorr. The frequency of the high frequency power to be applied is, for example, 13.56 MHz, and the magnitude is, for example, about 100 W to 1000 W. It is also possible to switch the etching gas to another combination of mixed gases during the etching process.

Reference is made to FIG. 1F. The resist pattern RP1 and the antireflection film BARK1 are removed by ashing, that is, plasma treatment with a gas containing oxygen. The processing gas used for the plasma processing may include at least one gas selected from O ₂ , CO, and CO ₂ . Further, at least one of H ₂ and N ₂ may be mixed in the processing gas. Specifically, for example, O ₂ gas is introduced at a flow rate of 500 sccm into a vacuum chamber of a parallel plate type reactive ion etching apparatus, and high frequency power of 13.56 MHz and 500 W is applied to a flat plate under a pressure of 250 mTorr. The electrode is applied to the electrode, and a treatment for 60 seconds is performed at a substrate temperature of 25 ° C.

By this plasma treatment, the resist pattern RP1 and the antireflection film BARK1 are removed, and an altered layer 4a is formed on the side surface and upper surface of the mask film 4 (the side and upper portions of the mask film 4 are converted into the altered layer 4a). ). The altered layer 4a is formed by the oxygen in the plasma processing gas soaked from the surface of the mask film 4 and the SiCOH is transformed into SiO ₂ . From the viewpoint of easy oxygen penetration, the mask film 4 is preferably a porous film.

  For a while from the start of the plasma treatment, the resist pattern RP1 and the antireflection film BARK1 cover the upper part of the mask film 4, and the deterioration proceeds on the exposed side surfaces of each part of the patterned mask film 4. When the antireflection film BARK1 disappears, alteration on the upper surface of the mask film 4 also starts.

  The thickness of the altered layer 4a of the mask film 4 can be adjusted by the plasma processing time. As will be described later with reference to FIG. 1N, for example, the non-altered portion 4b is left as a mask for patterning the gate electrode film 3. In this embodiment, the plasma processing time is selected so that the thickness of the altered layer 4a on the side of the mask film 4 is, for example, 70 nm.

  The width of each portion of the patterned mask film 4 is, for example, 190 nm, the total thickness of the altered layers 4a on both side portions is, for example, 140 nm, and the width of the non-altered portion 4b is, for example, 50 nm (see FIG. 1FX). . That is, the thickness of the deteriorated layer 4a formed on the side surface of the mask film 4 is selected so that the width of the non-modified portion 4b is the gate electrode width, for example, 50 nm.

  For example, when the gate electrode film 3 having a thickness of 100 nm is etched, it is desirable that the height of the unmodified portion 4b serving as a mask is 70 nm or more. Accordingly, the thickness of the mask film 4 is selected so that the height of the non-altered portion 4b after the plasma treatment is, for example, 100 nm to 70 nm, and the thickness of the altered layer 4a on the upper surface of the mask film 4 is, for example, 0 nm to 30 nm.

  Reference is made to FIG. 1G. A mask film 5 is formed on the gate electrode film 3 so as to cover the patterned mask film 4 (covering the upper and side portions of each portion of the mask film 4). For example, the mask film 5 is formed of the same material as the mask film 4. The mask film 5 is a SiCOH film formed by applying NCS by spin coating, for example, and has a thickness of 200 nm, for example.

Refer to FIG. 1H. On the mask film 5, an SiO ₂ film 6 having a thickness of 30 nm is deposited by CVD, for example.

  Reference is made to FIG. An organic material antireflection film BARK2 is formed on the mask film 5 by coating. A photoresist film is formed on the antireflection film BARK2 by coating. A pattern is transferred to the photoresist film by photolithography to form a resist pattern RP2.

  The resist pattern RP2 is for forming a mask for patterning in the length direction (Y direction) of the gate electrode. As shown in FIG. 1IP, the resist pattern RP2 has an opening OP2 that is elongated in the width direction (X direction) of the gate electrode. Each gate electrode is divided in the Y direction across the opening OP2 so that a desired SRAM circuit is formed.

Reference is made to FIG. 1J. Using the resist pattern RP2 as a mask, etching is performed to a depth at which the upper surface of the altered layer 4a is exposed. First, the antireflection film BARK2 is etched using the resist pattern RP2 as a mask, and the SiO ₂ film 6 is etched using the resist pattern RP2 and the antireflection film BARK2 as a mask. Further, the mask film 5 is etched to a depth at which the upper surface of the altered layer 4a is exposed.

Etching of the SiO ₂ film 6 and the mask film 5 is performed in a vacuum chamber using, for example, a parallel plate type dry etching apparatus. The substrate temperature during etching is, for example, about 25 ° C. Etching of the SiO ₂ film 6 is performed, for example, under the following SiO ₂ etching conditions. Etching of the mask film 5 is performed, for example, under the following SiCOH etching conditions.

In this embodiment, the material of the mask film 4 and the mask film 5 is SiCOH, and the material of the altered layer 4a of the mask film 4, the altered layer 5a of the mask film 5 described later, and the SiO ₂ film 6 is SiO ₂ . For example, the selective etching of SiCOH and SiO ₂ can be performed under the following conditions.

For etching SiO ₂ , for example, C ₄ F ₆ , O ₂ , and Ar can be used as an etching gas. Specifically, the gas ratios are combined in the order of C ₄ F ₆ , O ₂ , Ar in the order of 5-30, 5-100, 0-1000, and the total flow rate of the mixed gas is in the range of 200 sccm to 1000 sccm. The pressure in the chamber is, for example, 10 mTorr to 300 mTorr. The frequency of the high frequency power to be applied is, for example, 13.56 MHz, and the magnitude is, for example, about 100 W to 1500 W. It is also possible to switch the etching gas to another combination of mixed gases during the etching process.

For the etching of SiOCH, for example, CF ₄ , CHF ₃ , and Ar can be used as the etching gas as in the etching conditions of the mask film 4 described with reference to FIG. 1E. Specifically, the gas ratios are combined in the order of CF ₄ , CHF ₃ , and Ar in the order of 50 to 300, 10 to 100, and 0 to 1000, and the total flow rate of the mixed gas is set to a range of 200 sccm to 1000 sccm. The pressure in the chamber is, for example, 10 mTorr to 300 mTorr. The frequency of the high frequency power to be applied is, for example, 13.56 MHz, and the magnitude is, for example, about 100 W to 1000 W. It is also possible to switch the etching gas to another combination of mixed gases during the etching process.

Reference is made to FIG. 1K. The resist pattern RP2 and the antireflection film BARK2 are removed by ashing. Along with this ashing, the surface of the mask film 5 exposed in the recess RC formed by the etching described with reference to FIG. 1J is transformed into SiO ₂ , and the altered layer 5a is formed.

Reference is made to FIG. 1L. Etch SiO _{2 on} the entire surface. This SiO ₂ etching is performed, for example, under the above-described SiO ₂ etching conditions. Outside the recess RC, the SiO ₂ film 6 is removed, and the mask film 5 under the SiO ₂ film 6 is exposed (see FIGS. 1LX and 1LY1). At the bottom of the recess RC, the altered layer 4a on the upper surface of the mask film 4 is removed to expose the non-altered portion 4b (see FIG. 1LY2), and the altered layer 5a of the mask film 5 is removed to remove the unaltered portion of the mask film 5. Is exposed (see FIG. 1LY3). Note that the altered layer 5a of the mask film 5 remains on the side surface of the recess RC due to the anisotropy of dry etching.

  Reference is made to FIG. 1M. Etch SiCOH on the entire surface. This SiCOH etching is performed, for example, under the above-described SiCOH etching conditions. The mask film 5 formed on the mask film 4 is removed while leaving the mask film 5 formed on the side of the mask film 4 remaining.

  Outside the recess RC, the mask film 5 on the mask film 4 is removed, and the altered layer 4a on the upper surface of the mask film 4 is exposed (see FIGS. 1MX and 1MY1). The mask film 5 is so deep that the height of the mask film 5b remaining in the gaps between the portions of the patterned mask film 4 (on the sides of the mask film 4) is aligned with the height of the non-altered portion 4b of the mask film 4. Etched (see FIG. 1 MX).

  Inside the recess RC, the non-altered portion 4b of the mask film 4 exposed at the bottom is removed (see FIG. 1MY2), the mask film 5 is removed (see FIG. 1MY3), and the gate electrode film 3 is exposed. .

Reference is made to FIG. Etch SiO _{2 on} the entire surface. This SiO ₂ etching is performed by, for example, wet etching with hydrofluoric acid or dry etching under the above-described etching conditions. Note that even wet etching with hydrofluoric acid enables selective etching with a SiO ₂ selectivity ratio of about 5 when SiO _{2 having} a concentration of 0.5% is used.

  By this etching, the altered layer 4a on the upper and side portions of the mask film 4 and the altered layer 5a of the mask film 5 are all removed. Then, on the gate electrode film 3, the mask pattern formed by the non-modified portion 4 b of the mask film 4 and the mask pattern formed by the mask film 5 b formed in the gap between the portions of the patterned mask film 4 are left.

  As shown in FIG. 1NX, a pattern in which masks 4b and 5b are alternately arranged in the gate electrode width direction is formed.

  As described with reference to FIG. 1F, the mask of the non-altered layer is formed on the inner side of the side altered layer 4a by altering the side surface of each part of the mask film 4 patterned based on the resist pattern RP1. 4b can be formed.

  Then, as described with reference to FIG. 1G, by forming the mask film 5 so as to cover the patterned mask film 4, the mask 5 b can be formed in the gaps between the portions of the mask film 4.

  The width of the gap between the adjacent masks 4b and 5b is equal to the thickness of the altered layer 4a on the side of the mask film 4. That is, the altered layer 4a on the side of the mask film 4 functions as a spacer that determines the gap width between the adjacent mask 4b and the mask 5b.

  In this manner, masks 4b and 5b for patterning in the width direction of the gate electrode can be formed.

  According to the present embodiment, for example, patterning in the width direction of the gate electrode can be performed on the basis of one-time patterning by the resist pattern RP1, or the pitch of the pattern by the masks 4b and 5b finally formed can be doubled. The photolithographic process can be facilitated such that the thickness can be made thicker (a fine mask pattern in which the pitch formed in the lithography process is reduced to ½) can be obtained. Further, for example, by adjusting the thickness of the altered layer on the side of the mask film 4, the gap width between the mask 4b and the mask 5b can be easily adjusted, or the narrowness of the width of the mask 4b can be easily adjusted. It is easy to control the mask pattern shape.

  Note that one of the masks 4b and 5b does not become a mask of a laminated structure of different materials, and the masks 4b and 5b can be formed in the same structure with the same material, so that it is easy to improve the uniformity of patterning processing. It is.

  As shown in FIGS. 1NY2 and 1NY3, the mask 4b and the mask 5b are divided at desired positions in the gate electrode length direction.

  As described with reference to FIG. 1M, based on the resist pattern RP2, the unmodified portions of the mask film 4 and the mask film 5 can be removed at desired division positions in the gate electrode length direction. In this manner, the pattern shape in the length direction of the gate electrode can be given to the masks 4b and 5b.

When the resist pattern RP2 and the antireflection film BARK2 can be completely removed by etching the SiO ₂ film 6 and the mask film 5 described with reference to FIG. 1J, the ashing described with reference to FIG. 1K is not performed. May be. In that case, the deteriorated layer 5a of the mask film 5 is not formed on the inner surface of the recess RC, but the processes of FIGS. 1L to 1N can be performed in the same manner.

  Refer to FIG. The gate electrode film 3 is etched using the pattern of the mask 4b and the mask 5b as a mask.

  Reference is made to FIG. 1P. Similar to the process described with reference to FIG. 1F, the mask 4b and the mask 5b are altered by plasma treatment using a gas containing oxygen to form the altered mask 4a and the altered mask 5a. The plasma processing time is set so that all parts of the mask 4b and the mask 5b are altered.

Reference is made to FIG. 1Q. The entire surface of SiO ₂ is removed by wet etching with hydrofluoric acid, for example. Thereby, the alteration mask 4a and alteration mask 5a and the gate insulating film 2 exposed outside the gate electrode 3 are removed. In this way, the gate electrode 3 is formed. The mask 4b and the mask 5b can be removed by wet etching simultaneously with the extra gate insulating film 2 by being altered.

  Thereafter, using a known technique, a p-type impurity is introduced into the n-type well nw to form a p-type MOS transistor, an n-type impurity is introduced into the p-type well pw to form an n-type MOS transistor, and An upper wiring structure can be formed. In this way, the semiconductor device of the first embodiment is formed.

  Next, a method for manufacturing the semiconductor device of the second embodiment will be described. In the first embodiment, as described with reference to FIG. 1F, ashing for removing the resist pattern RP1 and the antireflection film BARK1 is used to convert the side of the mask film 4 into the altered layer 4a. . In the second embodiment, as will be described below, the removal process of the resist pattern RP1 and the antireflection film BARK1 and the process of converting the side portion of the mask film 4 into the altered layer 4a are performed independently.

  First, up to the mask film 4 on the gate electrode film 3 is formed in the same manner as the process described with reference to FIG. 1C of the first embodiment. In the second embodiment, the reference numerals in the first embodiment are used for members and structures that have a clear correspondence with the first embodiment.

Refer to FIG. 2A. An SiO ₂ film 14 having a thickness of 10 nm to 30 nm is deposited on the mask film 4 by, for example, CVD. On the SiO ₂ film 14, an antireflection film BARK1 made of an organic material is formed by coating. A photoresist film is formed on the antireflection film BARK1 by coating. A pattern is transferred to the photoresist film by photolithography to form a resist pattern RP1. Unlike the first embodiment, the SiO ₂ film 14 is sandwiched between the mask film 4 and the antireflection film BARK1.

Refer to FIG. 2B. The antireflection film BARK1 is etched using the resist pattern RP1 as a mask, and further, the SiO ₂ film 14 is etched to an intermediate thickness using the resist pattern RP1 and the antireflection film BARK1 as a mask. This etching is performed, for example, under the above-described SiO ₂ etching conditions.

Refer to FIG. 2C. The resist pattern RP1 and the antireflection film BARK1 are removed by ashing. Since the mask film 4 is still covered with the SiO ₂ film 14, no alteration layer is generated in the mask film 4 by this ashing.

Reference is made to FIG. 2D. Etching of SiO _{2 on} the entire surface is performed to the thickness of the SiO ₂ film 14 described with reference to FIG. 2B until the entire thickness is reached, and at the bottom of the recess corresponding to the opening of the resist pattern RP1. Then, the mask film 4 is exposed. This etching is performed, for example, under the above-described SiO ₂ etching conditions.

Refer to FIG. 2E. Using the SiO ₂ film 14 as a mask, the mask film 4 is etched until the gate electrode film 3 is exposed. This etching is performed, for example, under the above-described SiCOH etching conditions.

Refer to FIG. 2F. In a state where the SiO ₂ film 14 is formed on the mask film 4, plasma processing using a gas containing oxygen is performed to alter the mask film 4. Thereby, the upper surface side of the mask film 4 is not altered, the side surface side of the mask film 4 is altered, and the side portion of the mask film 4 is converted into the altered layer 4a. The plasma processing conditions are the same as those described with reference to FIG. 1F of the first embodiment, for example. The plasma processing time is set so that the altered layer 4a has a desired thickness, that is, the non-altered portion 4b has a desired width.

In the second embodiment, the upper portion of the mask film 4 is covered with the SiO ₂ film 14 and is not altered. Therefore, the height of the mask 4b can be determined by the thickness of the mask film 4 at the time of film formation. It is not necessary to control the thickness of the altered layer on the mask film 4.

SiO ₂ film 14, since the material similar to the altered layer of the mask film 4 is a SiO _2, functions similar to the altered layer 4a formed in the mask film 4 top in the first embodiment.

Subsequent steps of the second embodiment are performed in the same manner as the steps after FIG. 1G of the first embodiment by replacing the altered layer 4a formed on the upper surface of the mask film 4 with the SiO ₂ film 14 in the first embodiment. Can do. In this way, the semiconductor device of the second embodiment is formed.

  In the entire SiCOH etching process corresponding to the process described with reference to FIG. 1M in the first embodiment, the height of the mask film 5b left between the portions of the patterned mask film 4 is It is aligned with the height of the mask film 4 at the time of film formation.

In the entire SiO ₂ etching process corresponding to the process described with reference to FIG. 1N in the first embodiment, the cover film formed on the mask film 4 together with the altered layer 4a on the side of the mask film 4 is used. 14 is also removed.

  As described above, as described in the first and second embodiments, the side portion of the patterned mask film 4 is converted into the deteriorated layer 4a by the reactive plasma treatment, and the unmodified portion 4b is left inside the deteriorated layer 4a. The mask film 5b is formed outside the altered layer 4a, and the altered layer 4a is removed, thereby forming a mask pattern in which the non-altered portion 4b of the mask film 4 and the mask film 5b are arranged with the altered layer forming region in between. can do.

  In the first and second embodiments, the altered layer 4a is formed by converting the side portion of the mask film 4 formed of a material containing silicon into silicon oxide by plasma treatment using a gas containing oxygen. As an example of the material of the mask film 4, SiCOH that can be formed by application has been described, but the material of the mask film 4 is not limited to SiCOH that can be formed by application.

  For example, various types of porous SiCOH, SiOC, and SiC that can be formed by CVD have been developed as low dielectric constant materials, and some of them form an altered layer by, for example, oxygen plasma treatment. It can be used as a material. Plasma processing conditions for controlling the thickness of the altered layer can be found experimentally. In addition, it seems that there is a possibility that polycrystalline Si can be used as the material of the mask film 4.

  Note that it is not essential from the viewpoint of forming the mask 5b that the mask 5b is made of the same material as the mask 4b and that the mask 5b has the same height as the mask 4b. However, it is preferable that the mask 4b and the mask 5b are made of the same material and have the same height from the viewpoint of improving the uniformity of the patterning process using a group of mask patterns by the masks 4b and 5b.

In addition, it is not essential that the mask film 5 is converted into an altered layer. In the first embodiment, when the resist pattern RP2 and the antireflection film BARK2 can be completely removed by etching the SiO ₂ film 6 and the mask film 5 described with reference to FIG. 1J, refer to FIG. 1K. Although an example in which the ashing described above is not necessary has been described, in this case, the altered layer 5a of the mask film 5 is not formed.

  In addition, in the etching using the resist pattern RP1 as a mask and the etching using the resist pattern RP2 as a mask, the examples using the antireflection films BARK1 and BARK2, respectively, have been described, but the antireflection film is essential for etching. is not.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

The following additional notes are further disclosed regarding the embodiment including the first and second examples described above.
(Appendix 1)
Forming a first film over the semiconductor substrate;
Forming a first mask film above the first film;
Patterning the first mask film;
Performing a plasma treatment on a side portion of the patterned first mask film to convert the side portion into a deteriorated layer;
After the plasma treatment, forming a second mask film covering the upper part and the side part of the first mask film;
Etching the second mask film to remove the second mask film formed on the first mask film while leaving the second mask film formed on the side portion;
Removing the altered layer after etching the second mask film;
And a step of etching the first film using the remaining portions of the first mask film and the second mask film as a mask after removing the deteriorated layer.
(Appendix 2)
The first mask film is formed of a material containing silicon, and in the plasma treatment step, the material containing silicon is converted into silicon oxide by performing a plasma treatment using a gas containing oxygen. A method for manufacturing a semiconductor device.
(Appendix 3)
The method for manufacturing a semiconductor device according to attachment 2, wherein the first mask film is a porous film.
(Appendix 4)
The semiconductor device manufacturing method according to appendix 2 or 3, wherein the first mask film is formed of SiCOH, SiOC, or SiC.
(Appendix 5)
The step of patterning the first mask film includes a step of forming a resist pattern above the first mask film and etching the first mask film using the resist pattern as a mask,
5. The method of manufacturing a semiconductor device according to any one of appendices 2 to 4, wherein the plasma treatment removes the resist pattern and forms the deteriorated layer.
(Appendix 6)
By the plasma treatment, the side portion of the first mask film is converted into an altered layer, and the upper portion of the first mask film is also transformed into an altered layer,
6. The method of manufacturing a semiconductor device according to appendix 5, wherein the step of removing the deteriorated layer includes removing the deteriorated layer on the side portion and removing the deteriorated layer on the upper portion.
(Appendix 7)
The step of patterning the first mask film includes a step of forming a cover film on the first mask film, patterning the cover film, and etching the first mask film using the cover film as a mask,
The method of manufacturing a semiconductor device according to any one of appendices 1 to 4, wherein the plasma treatment is performed in a state where the upper portion of the first mask film is covered with the cover film.
(Appendix 8)
The cover film is formed of the same material as the altered layer,
The method of manufacturing a semiconductor device according to appendix 7, wherein the step of removing the deteriorated layer removes the deteriorated layer and also removes the cover film.
(Appendix 9)
Forming a cover film on the first mask film, patterning the cover film, and etching the first mask film using the cover film as a mask;
Forming a resist pattern above the cover film, and etching the cover film to an intermediate thickness using the resist pattern as a mask;
A step of removing the resist pattern by a plasma treatment with a gas containing oxygen in a state where the cover film is etched to an intermediate thickness;
After the removal of the resist pattern, the cover film is further etched to expose the first mask film at the bottom of the recess formed based on the resist pattern, and the first mask film as a mask. A method of manufacturing a semiconductor device according to appendix 7 subordinate to any one of appendixes 2 to 4, or appendix 8 subordinate to appendix 7 including the step of etching the mask film.
(Appendix 10)
The method for manufacturing a semiconductor device according to any one of appendices 1 to 9, wherein the first mask film and the second mask film are made of the same material.
(Appendix 11)
In the step of removing the second mask film, the height of the second mask film in the remaining portion is aligned with the height of the first mask film in the portion left in the step of removing the altered layer. The method for manufacturing a semiconductor device according to attachment 10, wherein the second mask film is removed.
(Appendix 12)
The first film is a conductive film, and the step of etching the first film is performed by patterning the conductive film to form a gate electrode of a MOS transistor. A method for manufacturing a semiconductor device.
(Appendix 13)
The first mask film and the second mask film are made of the same material,
further,
Forming a gate insulating film on the semiconductor substrate with silicon oxide;
The step of forming the first film includes forming the first film with a conductive material above the gate insulating film,
The step of etching the first film includes patterning the first film to form a gate electrode,
further,
After etching the first film, the entire portions of the first mask film and the second mask film are transformed into silicon oxide, and the altered first mask film and second mask film are removed. The method for manufacturing a semiconductor device according to any one of appendices 2 to 4, further comprising a step of removing the gate insulating film outside the gate electrode.
(Appendix 14)
The steps of removing the altered first mask film and the second mask film and also removing the gate insulating film outside the gate electrode include the first mask film, the second mask film, 14. The method for manufacturing a semiconductor device according to attachment 13, wherein the gate insulating film is removed.
(Appendix 15)
Forming a first film over the semiconductor substrate;
Forming a first mask film above the first film;
Patterning the first mask film into a plurality of portions arranged with a gap between them;
Performing a plasma treatment on the side surface of each portion of the patterned first mask film to form a deteriorated layer on the side surface of each portion;
Forming a second mask film covering the first mask film after forming the altered layer;
Etching the second mask film to remove the second mask film above the first mask film and leaving the second mask film in the gap;
Removing the altered layer after etching the second mask film;
Etching the first film using the first mask film of the portion remaining after removal of the deteriorated layer in each portion and the second mask film of the portion remaining in the gap as a mask, and A method for manufacturing a semiconductor device.
(Appendix 16)
The gap has a first width, and in the step of etching the first film, a portion of the second mask film left in the gap has the first width,
16. The method of manufacturing a semiconductor device according to appendix 15, wherein, in the step of etching the first film, a portion of the first mask film remaining after removal of the deteriorated layer in each portion has the first width.
(Appendix 17)
The first mask film is formed of a material containing silicon, and the step of forming the altered layer includes performing a plasma treatment with a gas containing oxygen as the plasma treatment to form a silicon oxide film as the altered layer,
In the step of forming the deteriorated layer, the processing time of the plasma processing using the oxygen-containing gas is performed so that the first mask film of the portion remaining after the removal of the deteriorated layer in each portion has the first width. Item 18. The method for manufacturing a semiconductor device according to appendix 16, wherein:

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate nw n-type well pw p-type well 2 Gate insulating film 3 Gate electrode film 4, 5 Mask film 4a, 5a Altered layer 4b, 5b Mask (non-altered layer)
6, 14 SiO ₂ film RP1, RP2 Resist pattern BARK1, BARK2 Antireflection film

Claims (10)

Forming a first film over the semiconductor substrate;
Forming a first mask film above the first film;
Patterning the first mask film;
Performing a plasma treatment on a side portion of the patterned first mask film to convert the side portion into a deteriorated layer;
After the plasma treatment, forming a second mask film covering the upper part and the side part of the first mask film;
Etching the second mask film to remove the second mask film formed on the first mask film while leaving the second mask film formed on the side portion;
Removing the altered layer after etching the second mask film;
And a step of etching the first film using the remaining portions of the first mask film and the second mask film as a mask after removing the deteriorated layer.   2. The first mask film is formed of a material containing silicon, and in the plasma treatment step, the material containing silicon is converted into silicon oxide by performing a plasma treatment using a gas containing oxygen. Semiconductor device manufacturing method.   The method of manufacturing a semiconductor device according to claim 2, wherein the first mask film is a porous film.   4. The method of manufacturing a semiconductor device according to claim 2, wherein the first mask film is formed of SiCOH, SiOC, or SiC. The step of patterning the first mask film includes a step of forming a resist pattern above the first mask film and etching the first mask film using the resist pattern as a mask,
The method for manufacturing a semiconductor device according to claim 2, wherein the plasma treatment removes the resist pattern and forms the altered layer. By the plasma treatment, the side portion of the first mask film is converted into an altered layer, and the upper portion of the first mask film is also transformed into an altered layer,
6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of removing the deteriorated layer includes removing the deteriorated layer on the side portion and removing the deteriorated layer on the upper portion. The step of patterning the first mask film includes a step of forming a cover film on the first mask film, patterning the cover film, and etching the first mask film using the cover film as a mask,
5. The method of manufacturing a semiconductor device according to claim 1, wherein the plasma treatment is performed in a state where an upper portion of the first mask film is covered with the cover film. The cover film is formed of the same material as the altered layer,
8. The method of manufacturing a semiconductor device according to claim 7, wherein the step of removing the deteriorated layer removes the deteriorated layer and also removes the cover film. Forming a cover film on the first mask film, patterning the cover film, and etching the first mask film using the cover film as a mask;
Forming a resist pattern above the cover film, and etching the cover film to an intermediate thickness using the resist pattern as a mask;
A step of removing the resist pattern by a plasma treatment with a gas containing oxygen in a state where the cover film is etched to an intermediate thickness;
After the removal of the resist pattern, the cover film is further etched to expose the first mask film at the bottom of the recess formed based on the resist pattern, and the first mask film as a mask. The method of manufacturing a semiconductor device according to claim 7, which depends on any one of claims 2 to 4, or claim 8 which is dependent on such claim 7, comprising a step of etching a mask film.   The method for manufacturing a semiconductor device according to claim 1, wherein the first mask film and the second mask film are made of the same material.

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