JP2003179064A - Method of forming wiring pattern - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and surely form, with the existing photolithography technology, a wiring pattern in the line width which is thinner than that of a resist pattern formed by the photolithography. <P>SOLUTION: A mask layer 6 consisting of SiOC is provided on a gate electrode layer 3 and a photoresist layer 4 is also provided on this mask layer 6. A resist mask 4a is formed to this photoresist layer 4 with the ordinary photolithography technology and the mask layer 6 is dry-etched using this resist mask 4a. Thereafter, the resist mask 4a is removed and the surface of the remaining mask layer 6 is denatured to the SiOX layer 6a through the ashing in the oxygen plasma. The formed SiOX layer 6a is removed with hydrofluoric acid to form the SiOC mask 6b, the gate electrode layer 3 is etched using this SiOC mask 6b, and thereby a wiring pattern 3a of the gate electrode can be obtained. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring pattern in a semiconductor device or the like, and more particularly to a method for forming a wiring pattern effective for miniaturizing the wiring pattern.

[0002]

2. Description of the Related Art In the field of semiconductor devices, for example, V
High integration and high performance such as LSI are progressing
In line with this, it is necessary to further miniaturize the wiring pattern.
It is Here, according to conventional photolithography,
2A to FIG.
The explanation will be given below with reference to (g). Figure 2
In (a), reference numeral 1 is a substrate made of Si or the like,
SiO on it ₂Oxide film 2 made of etc., WSi
/ PolySi etc. gate electrode layer 3 (in the figure, one layer
However, it is actually a two-layer structure), photoresist
Layer 4 is provided. In this explanation, the photo
The resist layer 4 is a so-called positive type. And
Grooves 5 corresponding to the wiring pattern are formed on the photoresist layer 4 side.
Place a photomask 5 with a
To expose the photoresist layer 4 through the mask 5.
As a result, the wiring pattern corresponding to the groove 5a is printed.
It Next, the photoresist layer 4 after being exposed with a predetermined chemical solution is formed.
By processing, it is exposed as shown in FIG.
The photoresist layer 4 in the exposed portion is removed (hereinafter,
The photoresist layer 4 remaining on the gate electrode layer 3
Mask 4a). Then, as shown in FIG.
Etching in plasma gas (dry etching)
The resist mass of the gate electrode layer 3 is
The part not covered with the mask 4a is removed. afterwards,
As shown in FIG. 2D, for example, a plasma gas containing oxygen is used.
Resist mask 4 by ashing in the mask
a is removed and the wiring pattern 3a of the gate electrode is formed.
Be done.

By the way, in the above-mentioned wiring pattern forming method, the line width of the formed wiring is determined by the wavelength of light used for exposure. For example, it is very difficult to form a line width of less than 0.15 μm with the KrF excimer laser which is widely used at present. Therefore, various methods for forming a wiring pattern using a light source with a shorter wavelength have been studied for the purpose of further miniaturizing the wiring. However, since the wiring pattern is extremely fine, it is difficult to secure the resolution and alignment accuracy of photolithography.

Therefore, in order to solve such a problem, there has been proposed a technique for miniaturizing a wiring pattern while utilizing a conventional photolithography technique.
As such a technique, for example, after forming the resist mask 4a shown in FIG. 2B, as shown in FIG. 2E, processing is performed in a plasma gas containing oxygen so that the resist mask 4a is removed. The line width is narrowed, and thereafter, the wiring pattern 3a of the gate electrode is formed by etching in a plasma gas atmosphere (see FIG. 2F) and ashing in oxygen gas plasma (see FIG. 2G). There is something. This is one in which the resist mask 4a is isotropically etched by the reaction between oxygen plasma and the resist so that the line width of the resist mask 4a is made finer than the resolution of lithography.

[0005]

However, since the resist material has a high reactivity with oxygen plasma, the rate of decrease of the resist mask 4a is fast, and it is difficult to control the resist mask 4a to a desired line width. There was a technical problem of being lost. As a method for solving this, for example, it is conceivable to set the reaction time in the oxygen plasma based on the detailed experimental results. Even in such a case, the plasma density generated by the oxygen plasma generator is generated. However, there is a phenomenon that the line width of the resist mask 4a changes depending on the position within the wafer, and the above-mentioned technical problem cannot be solved.

The present invention has been made to solve the above technical problems, and an object thereof is to easily and surely form by photolithography while using a conventional photolithography technique. Another object of the present invention is to provide a wiring pattern forming method capable of forming a wiring pattern having a line width narrower than that of a resist pattern.

[0007]

With the above object, the inventors of the present invention have made earnest studies. First, in order to control the line width of the mask to a desired line width, a reaction from a resist is performed as a mask. We have found that it is effective to use a material with low reactivity and controllable reactivity. Moreover, although it is necessary to form a predetermined pattern on this mask, it was found that it is effective to use a conventional photolithography technique for this. Therefore, the method for forming a wiring pattern of the present invention includes a mask layer forming step of forming a mask layer on a wiring layer, a resist pattern forming step of forming a resist pattern on this mask layer, and a resist of the mask layer. A mask layer etching step for selectively removing the portion not covered by the pattern, an ashing step for removing the resist pattern and for altering the remaining mask layer surface to form an altered layer, and an altered layer are removed. A mask pattern forming step of forming a mask pattern on the wiring layer and a wiring layer etching step of selectively removing a portion of the wiring layer not covered by the mask pattern.

In the present invention, the same pattern as the resist pattern is formed on the mask layer, and an altered layer is formed and removed on the surface of the formed pattern to form a mask pattern finer than the resist pattern, and the formed mask is formed. Since the wiring layer is etched by using the pattern to form the wiring pattern, it is necessary to form a wiring pattern finer than the resist pattern, that is, the resist pattern formed by the conventional photolithography technique is used. It is possible to form a wiring pattern finer than the pattern.

In the present invention, the wiring layer may be appropriately selected as long as it is a material used for electrical conduction. Further, in the mask layer etching step of the present invention, the altered layer may be formed on the surface of the mask layer exposed by the progress of etching. According to such a forming method, it is possible to form the deteriorated layer to some extent before the ashing step, so that the time required for the ashing step can be shortened.

The mask layer of the present invention may be appropriately selected from various ones, but silicon oxide containing carbon,
In particular, it is preferably composed of SiOC. When such a mask layer is used, a known semiconductor process can be used to form the mask layer, and also a known semiconductor process can be used in an ashing step and a mask pattern forming step described later.

Further, in the embodiment in which silicon oxide containing carbon is used as the mask layer, it is preferable to adopt a plasma treatment step using oxygen gas as the ashing step. According to this formation method, while the resist is ashed by the oxygen plasma, the carbon is desorbed from the silicon oxide containing carbon to form an altered layer made of SiO _x (0 <X ≦ 2). The process can be carried out easily. Here, SiO _x is silicon dioxide (S
iO ₂ ) or SiO ₂ from which oxygen is removed.

Furthermore, in the above aspect, it is preferable to adopt a wet etching process using hydrofluoric acid (HF) as the mask pattern forming process. According to this forming method, the altered layer (SiO _x layer) can be easily removed. Further, the mask layers (made of silicon oxide containing carbon) other than the altered layer are hardly removed.

The wiring pattern forming method of the present invention comprises a first step of forming a coating layer made of silicon oxide containing carbon on a conductive layer, and selectively modifying the coating layer by oxygen radicals. a second step of forming a SiO _x layer, a third step of forming a wiring pattern on the conductive layer by removing the SiO _x layer formed, not covered by the wiring pattern of the conductive layer And a fourth step of selectively removing the site. In the present invention, a wiring pattern is formed on a conductive layer by selectively forming a SiO _x layer on a coating layer made of silicon oxide containing carbon by using oxygen radicals and then removing the formed SiO _x layer. can do.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below in detail based on the embodiments shown in the accompanying drawings. 1 (a)-
(F) is a schematic diagram for explaining a method for forming a wiring pattern in the present embodiment. In addition, in FIG.
The same components as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. In FIG. 1A, reference numeral 6 is a mask layer provided on the gate electrode layer 3 and below the photoresist layer 4. The mask layer 6 is a SiOC film formed on the gate electrode layer 3 by CVD, sputtering, coating or the like, and its thickness is set to 100 nm or more. The thickness of the gate electrode layer 3 is 200 to
It is set to about 500 nm. The photoresist layer 4 is applied on the mask layer 6 by spin coating.

Next, a specific method of forming the wiring pattern will be described. First, a resist pattern is formed by a normal photolithography technique. That is, by arranging a photomask 5 having a groove 5a on the side of the photoresist layer 4 and exposing the photoresist layer 4 through the photomask 5, a pattern corresponding to the groove 5a is printed. . In this embodiment,
A KrF excimer laser (wavelength 248n is used as an exposure light source.
m) is used, the resolution of photolithography is 0.15 μm. The pattern formed here has a line width set slightly thicker than the actual wiring pattern to be finally formed, and is not the wiring pattern itself.

Next, the exposed photoresist layer 4 is treated with a predetermined chemical solution to remove the exposed photoresist layer 4 as shown in FIG. 1B (hereinafter referred to as a mask). The photoresist layer 4 remaining on the layer 6 is called resist mask 4a). Then, as shown in FIG. 1C, the mask layer 6 is dry-etched using the formed resist mask 4a. The etching conditions are as follows. <Etching conditions> Apparatus: magnetron type RIE (reactive ion etching) apparatus gas: C ₄ F ₈ / N ₂ / O ₂ / Ar = 10/15/5/50
0 sccm RF power: 1700 W Pressure: 7.3 Pa Lower electrode temperature: 20 ° C. Magnetic flux density: 0.012T By this dry etching, the part of the mask layer 6 which is not covered with the resist mask 4a is removed, and The same pattern as the resist mask 4a is formed. Further, due to the effect of oxygen used as an etching gas, the depth from the exposed surface of the mask layer 6 (both side surfaces exposed by etching) is about 5 nm (0.005 μm).
In the region up to m), SiOC is removed from C and a SiO _X layer 6a (altered layer) partially replaced with O is formed (FIG. 1).
(See the enlarged view of (c)).

Next, ashing is performed to remove the resist mask 4a. The ashing conditions are as follows. <Ashing conditions> Device: Microwave ashing device Gas: O ₂ = 400 sccm Source power: 0 W Bias power: 500 W Pressure: 8.0 Pa (60 mTorr) Temperature: 25 ° C. Then, the state shown in FIG. . As described above, the resist mask 4a is removed by ashing, while the SiO _x layer 6a is further 20 nm (0.
It is formed to a deep portion of about 02 μm). Therefore, the remaining mask layer 6 has a thickness of 25 nm (0.
The SiO _x layer 6a having a thickness of 025 μm) is formed. In the present embodiment, the ashing is continued even after the resist mask 4a is completely removed, so that the SiO _X layer 6a is formed also on the upper side of the mask layer 6 that is in close contact with the resist mask 4a. (See the enlarged view of FIG. 1D).

After the ashing is completed, wet etching (cleaning) is performed with a chemical solution containing hydrofluoric acid. At this time,
As shown in (e), of the remaining mask layer 6, SiO _x
The layer 6a is removed because it dissolves in hydrofluoric acid, but since SiOC itself inside Si is so slow that the etching rate by hydrofluoric acid is negligible, the SiOC itself remains almost unetched (hereinafter, The mask layer 6 remaining on the gate electrode layer 3 is referred to as a SiOC mask 6b). The line width of the SiOC mask 6b is reduced from the original line width (0.15 μm) by 0.025 μm on each side to be 0.10 μm.

Then, as shown in FIG. 1F, the gate electrode layer 3 is dry-etched using the formed SiOC mask 6b in an atmosphere containing Cl (chlorine) gas, for example. By this dry etching, the portion of the gate electrode layer 3 not covered by the SiOC mask 6b is removed, and the SiOC mask 6b is formed on the gate electrode layer 3.
And the same pattern is formed. As mentioned above, SiO
Since the line width of the C mask 6b is 0.10 μm, the line width of the wiring pattern 3a of the gate electrode formed on the gate electrode layer 3 is also 0.10 μm.

Therefore, in this embodiment, a resist pattern formed by ordinary photolithography can be used to form a wiring pattern having a line width smaller than that of the resist pattern. The formation of the SiO _x layer 6a is
The line width of the wiring pattern 3a of the gate electrode can be easily controlled because it can be controlled on the nm order by the etching condition of the mask layer 6 made of SiOC or the ashing condition of the photoresist layer 4. Furthermore, since the reaction between SiOC and oxygen occurs more slowly than the reaction between the photoresist and oxygen, the variation in the line width of the wiring pattern 3a of the gate electrode due to various changes in condition can be suppressed to a very small level. .

In this embodiment, the WSi / PolySi film is used as the gate electrode layer 3, but it is not particularly limited, and wiring materials such as Al, AlSi, Cu and W are used. Good. Further, its use is not limited to the gate electrode layer 3 and may be appropriately selected. Further, in the present embodiment, the SiOC mask 6b is left on the wiring pattern 3a of the gate electrode, but this may be removed. As a method of removing such a SiOC mask 6b, for example, wet etching or CMP (Chemical Mechanical Poli) is used.
shing) and the like. Other than this, the configurations described in the above embodiments can be selected or changed to other configurations without departing from the gist of the present invention.

[0022]

As described above, according to the present invention,
By using the conventional photolithography technique, it is possible to easily and reliably form a wiring pattern having a line width smaller than that of the resist pattern formed by the photolithography.

[Brief description of drawings]

1A to 1F are cross-sectional views showing a method of forming a wiring pattern according to an embodiment in the order of steps.

2A to 2G are cross-sectional views showing a conventional method for forming a wiring pattern in the order of steps.

[Explanation of symbols]

1 ... Substrate, 2 ... Gate oxide film, 3 ... Gate electrode layer, 3a
... Wiring pattern, 4 ... Photoresist layer, 4a ... Resist mask, 5 ... Photomask, 5a ... Groove, 6 ... Mask layer, 6a ... SiO _X layer, 6b ... SiOC mask

Continued front page    F-term (reference) 4M104 AA01 BB01 BB02 BB03 BB04                       BB18 CC05 DD64 DD65 DD71                       EE03 EE05 EE14 EE16 FF14                       GG09 HH14                 5F004 AA09 DA23 DA25 DA26 DB00                       DB02 DB17 DB26 EA04 EB02                 5F033 HH04 HH08 HH09 HH11 HH19                       HH28 MM07 QQ08 QQ09 QQ10                       QQ11 QQ19 QQ28 QQ48 QQ89                       RR01 RR04 XX03

Claims (6)

[Claims] 1. A mask layer forming step of forming a mask layer on a wiring layer, a resist pattern forming step of forming a resist pattern on the mask layer, and a resist pattern of the mask layer not covered with the resist pattern. A mask layer etching step of selectively removing a portion, an ashing step of removing the resist pattern and changing the remaining mask layer surface to form an altered layer, and removing the altered layer to form the wiring layer. Forming a wiring pattern, comprising: a mask pattern forming step for forming a mask pattern on the wiring layer; and a wiring layer etching step for selectively removing a portion of the wiring layer that is not covered by the mask pattern. Method. 2. The method of forming a wiring pattern according to claim 1, wherein in the mask layer etching step, the altered layer is formed on an exposed surface of the mask layer. 3. The method for forming a wiring pattern according to claim 1, wherein the mask layer is made of silicon oxide containing carbon. 4. The method for forming a wiring pattern according to claim 3, wherein the ashing step is a plasma processing step using oxygen gas. 5. The method of forming a wiring pattern according to claim 4, wherein the mask pattern forming step is a wet etching step using hydrofluoric acid. 6. A first step of forming a coating layer made of silicon oxide containing carbon on a conductive layer, and a second step of forming a SiO _x layer by selectively modifying the coating layer with oxygen radicals. A step of forming a wiring pattern on the conductive layer by removing the formed SiO _x layer, and selectively removing a portion of the conductive layer not covered by the wiring pattern And a fourth step of performing a wiring pattern forming method.