JP2012050099A - Phase-locked loop method and apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication system that uses a phase-locked loop employing two-point modulation.SOLUTION: The phase-locked loop includes: a master oscillator 100 having an output operably connected to a first input of a phase detector 106; a slave oscillator 102 having an output operably connected to a second input of the phase detector 106; and a forward-gain-adaptation module operably connected to a raw-error terminal of the phase detector 106. The forward-gain-adaptation module comprises: a variable gain amplifier 200 of the forward-gain-adaptation module operably connected to the raw-error terminal of the phase detector 106; and an integrator 202 of the forward-gain-adaptation module operably connected to the variable gain amplifier 200 of the forward-gain-adaptation module and the slave oscillator 102.

Description

  This application relates generally to phase-locked loops.

  A phase-locked loop is an electronic circuit that provides a relatively stable output waveform of variable frequency through the use of a master oscillator circuit having a relatively fixed frequency.

FIG. 1 shows a block diagram representing a phase locked loop 150. The master oscillator 100 has a voltage input labeled U _M. The master oscillator 100 generates a highly stable oscillation for an arbitrarily defined center frequency of the oscillator. The oscillation frequency can be changed slightly by changing the value of the voltage input U _M. The master oscillator 100 has a sensitivity rate for each voltage (sensitivity rating) K _M hertz (Hz / Volt). This indicates a proportionality between the input voltage and the oscillation frequency of the output voltage of the main oscillator 100.

The slave _VCO 102 generates an oscillation output signal whose frequency is based on the value of the voltage input V _VCO of the slave _VCO 102. The slave VCO 102 generally has a sensitivity rate K _V hertz (Hz / Volt) for each voltage. This indicates a proportional relationship between the input voltage and the oscillation frequency of the output voltage of the sub VCO 102.

  The main oscillator 100 generally oscillates in a highly stable manner, but the frequencies that can be oscillated are relatively limited. Conversely, the slave VCO 102 generally oscillates in a very unstable manner, although it is very flexible in terms of frequencies that can oscillate. The phase-locked loop 150 is a circuit that tries to make the best use of the characteristics while avoiding the limitations of both the master oscillator 100 and the slave VCO 102.

The output of the phase-locked loop 150 is also the output of the secondary VCO 102 but is provided to the “divide by N” (1 / N) frequency divider 104. The “divide by N” frequency divider 104 accepts the voltage waveform at frequency f ₁ as input and transmits as output the “divided by N” frequency version of the f ₁ frequency waveform. The output of the 1 / N frequency divider 104 is provided to one input of the differential frequency / phase voltage controller 106. The output of master oscillator 100 is provided to another input of differential frequency / phase voltage controller 106.

  Differential frequency / phase voltage controller 106 is shown as a summing junction in the negative feedback configuration. This configuration allows the difference frequency / phase voltage controller 106 to produce a nearly constant output (eg, zero) if the two inputs are the same, but if the two inputs are different, some change will occur. Indicates that it will occur. For example, when the differential frequency / phase voltage controller 106 detects that the voltage waveform output from the 1 / N frequency divider 104 is “lagging” to the voltage waveform output from the main oscillator 100. In the meantime, the differential frequency / phase voltage controller 106 slightly increases its output voltage, resulting in a corresponding increase in the output frequency of the waveform generated by the slave VCO 102. Conversely, when the differential frequency / phase voltage controller 106 detects that the voltage waveform from the 1 / N frequency divider 104 “leads” the voltage waveform from the main oscillator 100. In one configuration, the differential frequency / phase voltage controller 106 slightly reduces the output voltage to produce a corresponding decrease in the output frequency of the waveform generated by the slave VCO 102.

  Even if the differential frequency / phase voltage controller 106 actually detects the frequency difference, the indicated frequency difference is “relative to” the 100 kHz reference frequency generated by the main oscillator 100. From the standpoint of the differential frequency / phase voltage controller 106, the output voltage of the 1/10 frequency divider 104 is “out of phase” by the reference frequency waveform of 100 kHz. It should be noted that “is” (eg, time is “delayed” or “preceding”). As a result, those skilled in the art often refer to the differential frequency / phase detector portion (see, for example, FIG. 3) of the differential frequency / phase voltage control device 106 exclusively as a “phase detector”.

One block not yet discussed is the loop filter 108 block. As will be appreciated, the differential frequency / phase voltage controller 106 determines the frequency / phase difference between the inputs and outputs a voltage signal corresponding to this difference in near-more-real time. To do. As will be further appreciated, this output signal of the differential frequency / phase voltage controller 106 is ultimately used to drive the slave VCO 102. If the slave VCO 102 can respond to all the real-time voltage variations of the differential frequency / phase voltage controller 106, the slave VCO 102 often “overreacts” to produce a relatively unstable output voltage waveform. Better stability is achieved by making the sub-VCO 102 “less sensitive” to more rapid changes in the voltage output of the differential frequency / phase voltage controller 106. This is accomplished by placing the loop filter 108 between the differential frequency / phase voltage controller 106 and the voltage input V _VCO of the slave _VCO 102. Here, the loop filter 108 screens and “removes” any rapid change in the output voltage of the differential frequency / phase voltage controller 106. This tends to make the output of the slave VCO 102 (and thus also the output of the phase locked loop 150) irregular.

  The inventors of the present invention have recognized the need for related art phase locked loop stability and devised methods and systems that meet those needs. The inventor's perception of such needs constitutes part of the subject matter herein, and such perceived needs are discussed in the detailed description below.

  In one embodiment, the communication system has a master oscillator having an output operably connected to the first input of the phase detector and an output operably connected to the second input of the phase detector. Characterized by a forward gain adaptation module having a slave oscillator and a first input operably connected to the raw error terminal of the phase detector.

  In another embodiment, a method for controlling a communication system adjusts a feed forward gain of a phase locked loop in response to a raw error signal of the phase locked loop, and a slave oscillator of the phase locked loop in response to the feed forward gain. Including adjusting.

  In another embodiment, a communication system includes a master oscillator having an output connected to a first input of a phase detector, a slave oscillator having an output connected to a second input of the phase detector, and phase detection. And a forward gain adaptation module having a first input connected to the filtered error terminal of the generator.

  In another embodiment, a method of controlling a communication system adjusts a phase-locked loop feedforward gain in response to a phase-locked loop filtered error signal to create a jammed filtered error signal. Adjusting the phase-locked loop slave oscillator in response to the feedforward gain and the jammed filtered error signal.

  Since the above is a summary, simplification, generalization, and omission of details are included as necessary. Consequently, those skilled in the art will recognize that this summary is merely illustrative and is not intended to be limiting in any way. Other aspects, inventive features, and advantages described herein, as defined solely by the claims, will become apparent in the detailed description, without limitation herein.

FIG. 1 shows a block diagram illustrating a phase locked loop. FIG. 2 shows a high level block diagram of a phase locked loop in which two point modulation is utilized. FIG. 3 shows a block diagram of a phase locked loop shown in Laplace transform format. FIG. 4 shows a schematic diagram of one configuration of the loop filter. FIG. 5A shows an alternative system version of the system shown in FIGS. 2-4, which is substantially the system of FIG. 3 augmented by two additional signals, the first signal ξ indicates any uncontrollable or unpredictable external influence (eg noise) on the system, and the internal cancellation signal D is intended to cancel the residual influence of ξ that has not been canceled by the loop filter. Yes. FIG. 5B shows the system of FIG. 5A shown to be recognized by those skilled in the art as being somewhat similar to the Laplace transform secondary system “standard” or “canonical” format. FIG. 6A shows the system of FIG. 5B with an additional forward gain adaptation module. FIG. 6B illustrates the system shown in FIG. 6A, shown with further additional components in the forward gain adaptation module. FIG. 7A illustrates a system that is somewhat similar to the system shown in FIG. 6A, but with different connections and addition of jamming cancellation modules. FIG. 7B illustrates a system that is somewhat similar to the system shown in FIG. 7A, but with additional components. FIG. 8A shows a system where a primarily digital configuration is preferred. FIG. 8B shows a system in which an analog configuration is preferred. FIG. 9A shows a system with a phase locked loop that is somewhat similar to the phase locked loop shown and discussed with respect to FIG. 3, but with the addition of a linear model of the ΣΔ modulator. FIG. 9B is mathematically equivalent to the graphic display 13, 19, 21, 23 of FIG. 9A, but is operated so that the phase-locked loop appearing in FIG. 9B has a substantially similar topology to the phase-locked loop of FIG. 5A. 1 shows a system having a phase locked loop. FIG. 10A shows a system having the ΣΔ decimal-N phase locked loop of FIG. 9B, but with an additional forward gain adaptation module that implements the above-described raw error adapted system rules described with respect to FIG. 6B. FIG. 10B shows the system of FIG. 10A with further additional components in the forward gain adaptation module. FIG. 11A shows a system with the ΣΔ decimal-N phase locked loop of FIG. 9B, but with additional modules to help implement the above-described filtered error-adapted system rule described with respect to FIG. 7A. FIG. 11B illustrates a representative view of a system that is somewhat similar to the system shown in FIG. 11A.

  This application is a benefit of US Provisional Application No. 60 / 406,435 "Phase Locked Loop Method and Apparatus" based on US Patent Act 119 (e) filed on August 28, 2002 by inventor Gary Ballantyne. The entire contents of the application are included in this application.

  The use of the same symbol in different drawings generally indicates similar or identical items.

I. Non-Adaptive System FIG. 2 shows a high level block diagram of a phase-locked loop 250 that employs two-point modulation. The voltage input Um of the main oscillator 100 is supplied to the variable gain amplifier 200. Here, the variable gain amplifier 200 has a feed forward gain Ku. The output of variable gain amplifier 200 is supplied to summing junction 202. This is shown interposed between the loop filter 108 and the secondary VCO 102. The remaining components of the phase locked loop 250 function in a manner similar to that described with respect to FIG.

When the feedforward gain _Ku is set to a correct value, the variable gain amplifier 200 determines the maximum operating bandwidth of the phase locked loop 250 (ie, the band of the viable frequency that the phase locked loop 250 can execute) as follows. Enhancing beyond the bandwidth associated with the phase locked loop 150 of FIG. There are several different techniques for determining a substantially optimal value for the feedforward gain _Ku . For example, (an oscilloscope or such a spectral density meter) measuring device may be used to monitor the signal, the feedforward gain K _u to be adjusted manually, substantially the maximum operating bandwidth of the phase locked loop 250 Can be used to maximize. However, engineers typically implement these technologies in an ad hoc manner rather than matching any predefined design rules.

  The inventor of the subject matter disclosed herein has devised a process and associated device that substantially maximizes the maximum operating bandwidth of the phase-locked loop according to predefined rules. These devices and processes are now described.

  FIG. 3 shows a block diagram of a phase locked loop 350 expressed in a Laplace transformed format. In circuit analysis, the Laplace transform is used to transform a set of differential integrals from the time domain into a set of algebraic expressions in the frequency domain. Thus, solutions for unknown quantities are reduced to algebraic processing. Once the frequency domain equation for this unknown quantity is obtained, it can be transformed back to the time domain using known techniques. The Laplace transform block diagram circuits and devices described herein represent their time domain representation and vice versa.

  With reference to FIG. 3, in one configuration, master oscillator 300 forms master oscillator 100 with 1 / M frequency divider 302. In general, the 1 / M frequency divider 302 adds stability to the master oscillator 100. The master oscillator 300 supplies the input of the “divide by M” (1 / M) frequency divider 302. The output of 1 / M frequency divider 302 is connected to the input of differential frequency / phase voltage controller 106.

  In one configuration, the differential frequency / phase voltage controller 106 comprises a differential phase / frequency detector 304 that supplies a charge pump 306. The output of the charge pump 306 is connected to the input of the loop filter 108 (as represented by the Laplace transformed s-domain). The output of the loop filter 108 is connected to the input of the summing junction 202.

The output of the variable gain amplifier 200 is connected to the input of the summing junction 202, while the input of the variable gain amplifier 200 is connected to the input U _M of the main oscillator 300. The output of summing junction 202 is connected to the input of sub VCO 102. The output of the slave VCO 102 is connected to the input of the “divide by N” (1 / N) frequency divider 104. The output of the “divide by N” (1 / N) frequency divider 104 is connected to the input of the differential phase / frequency detector 304.

FIG. 4 shows a schematic diagram of one configuration of the loop filter 108. Those skilled in the art will appreciate that for the electrical circuit components shown, resistor R ₂ and capacitance C ₂ control loop dynamics. As a result, the following discussion here mainly considers only the effects of resistance R ₂ and capacitance C ₂ . However, the remaining components shown in FIG. 4 may be taken into account, particularly when numerical and numerical simulations of the processes and devices shown and described herein are performed.

  FIG. 5A shows an alternative system 550. Alternative system 550 is substantially similar to the system of FIG. 3, but is augmented by two extra signals. The first signal ξ indicates any uncontrollable and unpredictable external influence (eg noise) on the system, and the internal cancellation signal D cancels the residual influence of ξ that has not been canceled by the loop filter 108. Is intended to be. The internal erase signal D is described in more detail below in connection with FIGS. 7A and 7B.

  FIG. 5B shows the system of FIG. 5A shown to be recognized by those skilled in the art as being somewhat similar to the Laplace transform secondary system “standard” or “canonical” format. The representation of the standard formula of FIG. 5B, ie, canonical, is equivalent to that of FIG. 5A, but is easier to process and compare than a system not written in canonical form. This is because many system processing techniques use terminology similar to that of FIG. 5B. The representation of FIG. 5B is the result of numerical substitution and algebra processing, the details of which are not discussed here. Further, as will be shown below, a state equation is described by inspection by representing the system as shown in FIG. 5B. This proves advantageous in one configuration. Even though the following quantities are listed in canonical form, they are substantially equivalent to non-canonical form, and such non-canonical equivalents can be determined via standard conversion methods. The canonical form is used here as a consideration for ease of understanding and processing.

The representation of FIG. 5B is equivalent to that of FIG. 5A due to the following relationship:

One skilled in the art will recognize that when D = ξ, the system of FIG. 5B can be analyzed to derive the following transformation function:

From this conversion function, when the canonical feedforward gain K ^ _U = 1, the conversion function of the system is reduced to ((K _M N / M) Hz / volt) * 1 / s, which is ((K _M N It is noted that this is a Laplace transformed representation of a voltage controlled oscillator with a sensitivity of / M) Hz / volt). The inventor has determined that it would be advantageous to reduce the conversion function of the system of FIG. 5B to that of a near ideal oscillator. As a result, the inventor has shown that an advantageous form of adaptation is maintained at K ^ _U substantially at or near a single value, i.e. It was assumed that the movement of the system of FIGS. 5A-B would try to approximate that of a near-ideal oscillator.

II. As will be appreciated adapted systems, if maintained in the canonical feed-forward gain K ^ _U approximately 1, the motion of the system of Figure 5A-B is near the ideal voltage having a sensitivity of K _M N / MHz / Volt Approaching that of a controlled oscillator. The inventor has devised two main adaptation schemes that make the system of FIGS. 5A-B operate like a near-ideal system. A raw error-based adaptation scheme and a filtered error adaptation scheme.

A. Raw Error Adaptation System As will be appreciated, the inventor has shown that the canonical feedforward gain K ^ _U is such that the conversion function of the system shown in FIG. 5B is preferably reduced to that of a near-ideal oscillator. Judged to be desirable. The inventor has devised a rule that can be used to keep the canonical feedforward gain K ^ close to that of the ideal oscillator. The rules are as follows:

  The adaptive equation is derived based on the condition that the rate of change of energy (raw or filtered) is always negative. That is, the error tends to become zero with the passage of time.

FIG. 6A shows the system of FIG. 5B with an additional forward gain adaptation module 600 that implements the rules described above. In other words, the raw error rule, in one configuration, the canonical feed-forward gain K ^ _U which tend to operate the system as a near ideal oscillator, canonical input U ^ _M and raw error signal the product of y ₁ gamma ₁ times It states what can be obtained by integrating. In the raw error rule, γ ₁ is a positive constant and helps determine the speed of adaptation. The raw error rule is based on the stability argument and is intended to make the overall phase locked loop / adaptive system as stable as possible for all values of γ ₁ . With respect to FIG. 6A, the components that substantially implement the raw error adaptation rule are the preceding multiplier 606, the variable gain amplifier 602 of the forward gain adaptation module with a gain of γ ₁ , and the integrator 604 of the forward gain adaptation module. .

With continued reference to FIG. 6A, the canonical input U ^ _M is connected to the input of the preceding multiplier 606. The terminal with raw error y ₁ (carrying the raw error signal y ₁ ) is connected to the input of the preceding multiplier 606. The output of the preceding multiplier 606 is connected to the input of the variable gain amplifier 602 of the forward gain adaptation module having a gain of γ ₁ . The output of the variable gain amplifier 602 of the forward gain adaptation module is connected to the input of the integrator 604 of the forward gain adaptation module. Connected to the input of the subsequent multiplier 616 are both the output of the integrator 604 of the forward gain adaptation module and the canonical version of the input signal U ^ _M. The output of the subsequent multiplier 616 is operatively connected to the input of the summing junction 202. For the remaining system components, the system functions as has been displayed and described herein.

  Although not explicitly shown in the drawing, in other configurations, there is a filter that is generally similar to the loop filter 108 interposed between the preceding multiplier 606 and the variable gain amplifier 602 of the forward gain adaptation module. As a result, wherever the preceding multiplier 606 and the variable gain amplifier 602 of the forward gain adaptation module appear or are described herein, in an alternative configuration, the variable gain of the preceding multiplier 606 and the forward gain adaptation module It should be understood that there is a filter that is generally similar to the loop filter 108 interposed between the amplifier 602.

  Although a proportionally distributed variable gain amplifier is described herein (eg, a proportionally distributed variable gain amplifier 610 described below and a proportionally distributed variable gain amplifier 710 described below), such as described and described herein. Those skilled in the art will recognize that a proportionally distributed variable gain amplifier represents a controller such as a proportional-integral (PI) controller or a proportional-integral-derivative (PID) controller.

  Although voltage controlled oscillators are actually non-linear, there is a recognized range of operation of voltage controlled oscillators that may be treated as substantially linear for design purposes. As a result, the discussion here treats the voltage controlled oscillator as substantially linear, as is often done in design applications. Although the use of a “divide by N” circuit is described herein, in other configurations, the voltage controlled oscillator is downconverted with a mixer rather than a “divide by N” circuit.

The inventor believes that in practice the secondary VCO 102 may have a response that is not perfectly modeled by an ideal oscillator (as shown in FIG. 6A), or that additional components in the loop filter of FIG. There may be other unmodeled dynamics such as these, and these differences between the actual and modeled systems are beyond that of the phase-locked loop of FIG. 6A. Also noticed that limiting the maximum magnitude of γ ₁ that remains feasible. In such a real world situation, the inventor has found it advantageous to augment the raw error rule with a proportional distribution (γ ₁ ) and a “leak” factor (δ ₁ ). While the inventor can assume that proportional control is available to accelerate adaptation, of the several methods available to make the adaptation system robust against disturbances and unmodeled variations One heuristically points out that a leak factor can be assumed. An alternative system that implements the basic proportional distribution of raw error rules described above and the addition of leak factors is shown below in FIG. 6B.

FIG. 6B illustrates the system shown in FIG. 6A and shown with additional additional components within the forward gain adaptation module 600. As can be seen from FIG. 6B, in this configuration, forward gain adaptation module 600 is driven, at least in part, by what may be characterized as a “raw error” signal y ₁ . Signal y ₁ is referred to herein as a “raw error” signal to distinguish it from what is referred to herein as a “filtered error” signal y ₂ .

Still referring to FIG. 6B, the canonical input U ^ _M is connected to the input of the preceding multiplier 606. The raw error y ₁ is connected to the input of the preceding multiplier 606. The output of the preceding multiplier 606 is connected to the input of the variable gain amplifier 602 of the forward gain adaptation module having a gain of γ ₁ . The output of variable gain amplifier 602 of the forward gain adaptation module is connected to the input of summing junction 608. The output of summing junction 608 is connected to the input of integrator 604 of the forward gain adaptation module. The output of integrator 604 of the forward gain adaptation module is connected to the input of summing junction 608 in a negative feedback manner. Here, the negative feedback is provided by a leak factor variable gain amplifier 612 having a gain of σ ₁ .

The output of integrator 604 of the forward gain adaptation module is connected to the input of summing junction 614. The input of the summing junction 614 is further connected to the output of a proportional distribution variable gain amplifier 610 having a gain of γ ₂ . The input of the proportional distribution variable gain amplifier 610 is connected to the output of the preceding multiplier 606.

The output of summing junction 614 is connected to the input of subsequent multiplier 616. The succeeding multiplier 616 is connected to a canonical version of the input signal U ^ _M. The output of the subsequent multiplier 616 is operatively connected to the input of the summing junction 202. For the remaining system components, the system functions as displayed and described herein.

B. Filtered Error Adaptation System Intuitively, it would be preferable for adaptation using the filtered error signal y ₂ to use the raw error signal y ₁ to adapt the system. However, when the inventor attempted to use the filtered error signal y ₂ to perform the adaptation, the inventor unexpectedly discovered that the adaptation became very sensitive to the first signal ξ. did. This signal is used here to indicate some uncontrollable and unpredictable external effects (eg noise) to the system. Therefore, the inventor has devised an internal erase signal D. This is intended to eliminate the residual effects of ξ that are not canceled by the loop filter 108.

In respect of the above, the inventor has devised two rules that can be used to create a system whose transfer function approaches that of an ideal oscillator. These two rules are as follows:

  The adaptive equation is derived based on the condition that the rate of change of energy (raw or filtered) is always negative. That is, the error tends to become zero with the passage of time.

FIG. 7A shows modules 600 and 700 that implement the rules described above. If other words, the filtered error rule, in one configuration, the canonical feed-forward gain K ^ _U is the product of the canonical input U ^ _M feedforward error y ₂ is found by integrating _once gamma, In addition, mentioning that the system of FIG. 7A can be made closer to the operation of an ideal oscillator when a disturbance cancellation factor D found by integrating feedforward error y ₂ γ ₃ times is inserted into the system. Yes. In the filtered error rule, γ ₁ and γ ₃ are positive constants that help determine the rate of adaptation. Components, prior multiplier 606 forward gain adaptation module 600 components of the variable gain amplifier 602 and forward-gain adaptation module, the forward gain adaptation module having a gain of gamma ₁ which substantially implement the filtered error adaptation rule Integrator 604, a component of disturbance cancellation module 700 of disturbance cancellation module variable gain amplifier 702 having a gain of γ ₃ , integrator 704 of disturbance cancellation module.

The system shown in FIG. 7A is similar to the system shown in FIG. 6A, but with a different connection and the addition of a disturbance cancellation module 700. As can be seen from Figure 6A, the forward gain adaptation module 600, at least in part, one skilled in the art is driven by an admission and may be an error signal y ₂ which is the filter. That is, in FIG. 6A, one input to the preceding multiplier 606 was the raw error signal y ₁ , but in FIG. 7A, that same input is shown as a filtered error signal y ₂ . Otherwise, the connections are as shown and described with respect to FIG. 6A, and as a result, the discussion regarding these components in common with FIG. 6A will not be repeated here.

Continuing to refer to FIG. 7A, the interference erase module 700, the filtered error signal y ₂ is coupled to an input of the variable gain amplifier 702 of the interference erase module having a gain of gamma _3. The output of the variable gain amplifier 702 of the disturbance cancellation module having a gain of γ ₃ is connected to the input of the integrator 704 of the disturbance cancellation module. The output of the jammer cancellation module integrator 704 is connected to the input of summing junction 720.

Input of the summing junction 720 is connected to the error signal y ₂ which is the filter. The output of summing junction 720 is connected to the input of summing junction 202. For the remaining system components, the system functions as displayed and described herein.

Just like the raw error rule, the inventor may actually have a response that the plant (secondary VCO) 102 is not completely modeled by a pure integrator (as shown in FIG. 7A), or There may be other unmodeled variations, such as additional components in the loop filter 108, and these differences between the actual system and the modeled system indicate that the system shown in FIG. We have found that we limit the maximum size of γ ₃ beyond which this is feasible. In such a real world situation, the inventor has realized that there are advantages to augmenting the error rules filtered with proportional distribution factors γ ₁ and γ ₄ and leak factors δ _{1 and} δ ₂ . An alternative system that implements the proportional distribution of the basic filtered error rules described above and the addition of leak factors is shown below in FIG. 7B.

FIG. 7B illustrates a system that is somewhat similar to the system shown in FIG. 7A but with additional components in modules 600 and 700. As can be seen from FIG. 7B, in this configuration, the forward gain adaptation module 700 is similar to the forward gain adaptation module 600 of FIG. 6B, but at least partially by the skilled person with the filtered error signal y ₂ . Driven by what you admit. That is, in FIG. 6B, one input to the preceding multiplier 606 was the raw error signal y ₁ , but in FIG. 7B, that same input is shown as the filtered error signal y ₂ . Otherwise, the connections are displayed and described with respect to FIG. 6B and are displayed and described, and eventually the discussion regarding these components in common with FIG. 6B is not repeated here.

Continuing to refer to FIG. 7B, the interference erase module 700, the filtered error signal y ₂ is coupled to an input of the variable gain amplifier 702 of the interference erase module having a gain of gamma _3. The output of the variable gain amplifier 702 of the interference cancellation module having a gain of γ ₃ is connected to the input of the summing junction 708. The output of summing junction 708 is connected to the input of integrator 704 of the interference cancellation module. The output of the jammer cancellation module integrator 704 is connected to the input of summing junction 708 in a negative feedback manner. Here, the negative feedback is provided by the variable gain amplifier 712 of the interference cancellation module's leak factor with a gain of σ ₂ .

The output of the disturbance cancellation module integrator 704 is connected to the input of summing junction 714. Connected to the input of the summing junction 714 is the output of the distribution proportional variable gain amplifier 710 of the proportional distribution module of the interference cancellation module having a gain of γ ₄ . The input of the proportional cancellation variable gain amplifier 710 of the jamming cancellation module is connected to “filtered error” y ₂ .

The output of summing junction 714 is connected to the input of summing junction 720. Input of the summing junction 720 is connected to the error signal y ₂ which is the filter. The output of summing junction 720 is connected to the input of summing junction 202. For the remaining system components, the system functions as displayed and described herein.

  Those skilled in the art recognize that the state of the art has progressed to the point where little distinction remains between the hardware and software configurations in the system aspect. Therefore, the use of hardware or software is generally a design choice that represents a cost-effective tradeoff (but not always. In some contexts, the choice between hardware and software is critical. May be). Those skilled in the art will recognize that there are a variety of vehicles by which the processing and / or system aspects described herein (eg, hardware, software and / or firmware) can be performed, You will recognize that the system changes with the background to which it is installed. For example, if the implementer determines that speed and accuracy are the best, the implementer can choose a unique software configuration, or alternatively, the implementer can be hardware, software, and / or firmware. Any combination of may be selected. Thus, there are several possible media, which can provide aspects of the processing described herein. Neither of these is that any media to be utilized is a choice that depends on the background in which the media is installed and on the implementer's particulars (such as speed, flexibility, or predictability). None of these are better in nature than others, and any of these can vary.

  The above detailed description describes various embodiments of devices and / or processes via block diagrams, flowcharts, etc. As long as such block diagrams, flowcharts, etc. include one or more functions and / or operations, each function and / or operation in such block diagrams, flowcharts, etc. may be individually and / or collectively. It will be appreciated by those skilled in the art that it can be realized by a wide range of hardware, software, firmware, or virtually any combination thereof. In one embodiment, the present invention can be implemented via an application specific integrated circuit (ASIC). However, embodiments disclosed herein may be implemented as one or more computer programs running on one or more computers (eg, as one or more programs running on one or more computer systems), one or more As one or more programs that run on a controller (eg, a microcontroller), as one or more programs that run on one or more processors (eg, a microprocessor or a digital signal processor), as firmware, or as a virtual Disclosure of the invention is that, in general, any combination of these, in whole or in part, can be equally implemented in a standard integrated circuit, and design the circuit and / or write software or firmware code. Will be within the scope of those skilled in the art. Rudaro intends. Further, those skilled in the art will recognize that the mechanism of the present invention can be distributed in various forms as a program product, and that the exemplary embodiment of the present invention is the specific type used to actually perform this distribution. It will be appreciated that it applies equally regardless of the signal carrier medium. Examples of signal carrying media include, but are not limited to: Writable media such as floppy disks, hard disk drives, CD ROMs, digital tapes, and computer memory, and digital-to-analog communication links or IP-based communication links (eg, packet links) using TDM Such a transmission type medium.

  In a general sense, the various embodiments described herein may be configured individually and / or collectively by a wide range of hardware, software, firmware, or any combination thereof, although various types of Those skilled in the art will recognize that they may be considered as consisting of “electronic circuits”. As a result, as used herein, “electronic circuit” includes, but is not limited to, an electronic circuit having at least one discrete electrical circuit and an electronic having at least one integrated circuit. A general purpose computing device comprised of a circuit, an electronic circuit having at least one application specific integrated circuit, and a computer program (eg, constituted by a computer program that at least partially executes the processes and / or devices described herein) Forming a memory device (eg, a random access memory) and an electronic circuit forming a general purpose computer, or a microprocessor configured by a computer program that at least partially executes the processes and / or devices described herein Formation) Electronic circuit and communication Vice (e.g., a modem, communications switch, or optical electronic devices) include an electronic circuit for forming a can.

  Those skilled in the art will recognize that it is common in the art to describe devices and / or processes in the manner described herein, and use standard design practices to describe such described devices and / or processes. Would typically be incorporated into a partially analog and partially digital system. That is, the devices and / or processes described herein may be incorporated into a partially analog and partially digital system through a reasonable amount of experimentation that is well within the skill of the art. 8A and 8B show examples of systems that can incorporate at least a portion of the devices and / or processes described herein with a reasonable amount of experimentation.

  FIG. 8A shows a system that is particularly suitable for digital configurations. Digital and analog section dividers are marked in FIG. 8A. The system may optionally include a mixer for downconverting the output. The main oscillator, loop filter and adaptive circuit are digital. The output of the VCO enters a ΣΔ downconverter to form an error with a digital oscillator. The outputs of the loop filter and adaptive circuit are converted to analog signals and applied to the VCO input.

  FIG. 8B shows a system particularly suited for analog configurations. The dividers for digital and analog parts are marked in FIG. 8B. The system of FIG. 8B is an alternative to that of FIG. 8A in that the partition of FIG. 8B is suitable for analog circuits. This method is suitable for adaptive algorithms as described herein.

ΣΔ fractional N phase locked loop embodiment described above, instead of modulating the oscillator directly as the phase-locked loop may be modulated by varying the loop divider ratio N dynamically. In particular, N may be controlled by a ΣΔ modulator to allow decimals rather than integer values. Just like the phase-locked loop discussed above, two-point modulation can be applied to such a ΣΔ decimal-N loop as shown below.

FIG. 9A shows a system having a phase-locked loop 900 that is somewhat similar to the phase-locked loop 350 (FIG. 3) but with the addition of a linear model of the ΣΔ modulator (the ΣΔ modulator is typically a loop division ratio). 9A shows a linear version of the ΣΔ modulator, where (constant) N represents the nominal divide ratio, where a small change in divide ratio is the inserted phase modulation θ _MOD Represented by).

  For clarity and ease of illustration, a linearized version of the ΣΔ modulator is shown and described here, but the actual ΣΔ modulator (as opposed to the linear model used for analysis) A high resolution signal is typically generated using only the level. In particular, ΣΔ modulators generally accomplish the above by dithering the output between levels such that the output has a desired value when filtered. In the background considered here, the ΣΔ modulator is typically implemented with a digital circuit. The divide ratio N is then dithered between several individual values, thereby producing the required value when filtered by the low pass filtering operation of the phase locked loop. Accordingly, when a linearized ΣΔ modulator is shown, described, and / or referenced herein in part or in whole, such a partial or total linearized ΣΔ modulator is a partial ΣΔ modulator. Or it is meant to represent the physical configuration of substantially all of the ΣΔ modulator partial or total components, not just the overall linearization analysis version.

Phase locked loop 900 has two inputs. Upper input _RCH and lower input _RMD . The upper receive R _CH is a constant and sets the frequency of the channel (ie, the frequency at which the modulation spectrum is centered). Lower input R _MD varies with time, resulting in frequency modulation of VCO902. This frequency modulation is converted into phase modulation θ _MOD and inserted into the phase locked loop 900.

A scaled version of the upper input R _CH and the lower input R _MD is inserted at the summing junction 202 of the slave VCO 102 to allow two point modulation. Here, such scaling is performed by the variable gain amplifier 908.

And the variable gain amplifier 904

Are controlled by each. A comparison of phase locked loop 900 and phase locked loop 350 of FIG. 9A shows that such phase locked loops are considered substantially different. Thus, it is not readily apparent how the processes and devices described herein can be applied to the phase locked loop 900.

  To overcome the above problems, the inventors have discovered that the ΣΔ decimal-N phase locked loop 900 can be transformed such that the processes and devices described above can be applied to the phase locked loop 900. This conversion can be understood as follows.

With continued reference to FIG. 9A, the following is obtained.

  In terms of the above, using numerical processing (similar to the numerical processing described with respect to FIGS. 5A and 5B above), the system of FIG. 9A becomes a system that is approximately mathematically equivalent to the system shown in FIG. Can be converted.

FIG. 9B shows a phase locked loop 950 system. This is approximately mathematically equivalent to phase-locked loop 900, but phase-locked loop 950 is shown having a reference input that can be equivalent to the phase-locked loop 950 appearing in FIG. Except that the phase-locked loop 550 of FIG. 5A is processed in a manner similar to the topology (the main oscillator 300 is represented by its Laplace transform version Km / s). Note that).

  As can be seen by comparing the phase-locked loop 950 with the phase-locked loop 550, apart from the phase-locked loop 950 input and the phase difference of the phase-locked loop 550, the phase-locked loop 950 and the phase-locked loop 550 Are almost identical.

  With the aid of the fact that the phase-locked loop 950 of FIG. 9B is substantially similar to the phase-locked loop 550 resulting from the mathematical transformation described above, the inventor creates a ΣΔ decimal-N phase-locked loop. did. This incorporates the processes and devices described above. These ΣΔ decimal-N phase locked loops are now described.

FIG. 10A has the ΣΔ decimal-N phase locked loop 950 of FIG. 9B, but with an additional forward gain adaptation module 600 that implements the above-described raw error adapted system rules as described with respect to FIG. 6B. Indicates the system. As recognized above, this rule is as follows:

As will be appreciated, FIG. 10A is substantially similar to FIG. 6A with the following exceptions regarding FIG. 10A.

  Apart from the above differences, the phase locked loop 950 of FIG. 10A functions substantially similar to the phase locked loop 550 of FIG. 6A. Accordingly, descriptions of such functions are not explicitly described here for the sake of brevity.

FIG. 10B shows the system of FIG. 10A with additional components in the forward gain adaptation module 600. As can be seen by comparison, FIG. 10B is substantially similar to FIG. 6B with the following exceptions regarding FIG. 10B.

  Apart from the above differences, the phase-locked loop 950 of FIG. 10B functions substantially similar to the phase-locked loop 550 of FIG. 6B. Accordingly, descriptions of such functions are not explicitly described here for the sake of brevity.

FIG. 11A shows a system having the ΣΔ decimal-N phase locked loop 950 of FIG. 9B, but further implements the above-described filtered error adapted system rule implementation as described in connection with FIG. 7A. Additional modules 600 and 700 to assist are also provided. These two rules are as follows:

FIG. 11A is substantially similar to FIG. 7A with the following exceptions regarding FIG. 11A.

  Apart from the above differences, the phase locked loop 950 of FIG. 11A functions substantially the same as the phase locked loop 550 of FIG. 7A. Accordingly, descriptions of such functions are not explicitly described here for the sake of brevity.

FIG. 11B illustrates the system. As can be seen by comparison, FIG. 11B is substantially similar to FIG. 7B with the following exceptions regarding FIG. 11B.

  Apart from the above differences, the phase-locked loop 950 of FIG. 11B functions in much the same way as the phase-locked loop 550 of FIG. 7B. Accordingly, the description of such functions is not explicitly described here for the sake of brevity.

  As already described in connection with FIGS. 8A and 8B, the various actual configurations of the loops and / or systems shown here are divided between the digital and analog domains in many different ways.

  The previously described embodiments show different components that are included in or connected to different different components. It should be understood that such a shown architecture is exemplary only and that many other architectures that actually accomplish the same function may be implemented. In a conceptual sense, any arrangement of components to achieve the same function is effectively “associated”. Thereby, a desired function is achieved. Thus, any two components combined here to achieve a particular function can be understood to be “associated” with each other. This achieves the desired function regardless of the architecture or intermediate components. Similarly, any two components so associated may be considered “operably connected” or “operably coupled” to each other to achieve a desired function.

  While particular embodiments of the present invention have been shown and described, changes and modifications may be made based on the teachings herein without departing from the invention and its broader aspects, and therefore, the claims It should be apparent to those skilled in the art that the scope should encompass the scope of the invention, and all such changes and modifications are within the true spirit and scope of the invention. Furthermore, it is to be understood that the invention is defined only by the claims. In general, terms used herein, particularly those used in the claims (eg, the body of the claims), are generally intended as “open” terms (eg, the term “ "Including" should be construed as "including but not limited to", the term "having" should be construed as "having at least", and the term "including" should be "including but not limited to" It should be understood by those skilled in the art. In addition, if there is an intention to introduce a specific number in a claim statement, such intention is clearly stated in the claim, and if there is no such statement, such intention is presented. It should be understood by those skilled in the art that this is not done. For example, as an aid to understanding, the following claims may include the use of the introduced expression “at least one” or “one or more” in the description of the introduced claim. However, the use of such expressions may include the expressions “one or more” or “at least one” and the indefinite article such as “a” or “an” in which the same claim is introduced ( For example, “a” and / or “an” are generally taken to mean “at least one” or “one or more”), the introduction of a claim by the indefinite article “a” or “an” Should not be construed as implying that any particular claim, including the description of such introduced claims, should be limited to an invention containing only one such description. Rather, the same is true for the use of definite articles used to introduce claim recitations. Further, even if a specific number of introductions in a claim are clearly stated, those skilled in the art will generally recognize that such a description means “at least” the stated number. It will be appreciated that it should be interpreted (eg, the naked description “two descriptions” without other modifiers generally means at least two descriptions, or two or more descriptions) ).

Claims (43)

A master oscillator having an output operably connected to a first input of the phase detector;
A slave oscillator having an output operably connected to a second input of the phase detector;
A communication system comprising a forward gain adaptation module having a first input operably connected to a raw error terminal of a phase detector. The forward gain adaptation module having a first input operably connected to a raw error terminal of a phase detector,
A variable gain amplifier of a forward gain adaptation module operatively connected to the raw error terminal of the phase detector;
The communication system according to claim 1, further comprising an integrator of a forward gain adaptation module operatively connected to the variable gain amplifier of the forward gain adaptation module and the slave oscillator. The variable gain amplifier of the forward gain adaptation module connected to the raw error terminal of the phase detector is
A preceding multiplier having a first input operably connected to the raw error terminal of the phase detector and a second input operably connected to the master oscillator;
3. The communication system of claim 2, wherein the variable gain amplifier of the forward gain adaptation module has an input operatively connected to the output of the preceding multiplier. The integrator of the forward gain adaptation module operatively connected to the variable gain amplifier of the forward gain adaptation module and the slave oscillator comprises:
A first input operably connected to an output of the integrator of the forward gain adaptation module; a second input operably connected to an input of the master oscillator; and operative to an input of the slave oscillator. A subsequent multiplier having a connected output;
The communication system of claim 2, wherein the integrator of the forward gain adaptation module has an input operatively connected to the output of the variable gain amplifier of the forward gain adaptation module. The integrator of the forward gain adaptation module having an input operatively connected to the output of the variable gain amplifier of the forward gain adaptation module;
5. A leak factor variable gain amplifier having an input operably connected to an integrator of the forward gain adaptation module, and an output operably connected to an input of the integrator of the forward gain adaptation module. The communication system described. A first input operably connected to an output of the integrator of the forward gain adaptation module; a second input operably connected to an input of the master oscillator; and operative to an input of the slave oscillator. And the subsequent multiplier having a connected output,
5. A communication system according to claim 4, comprising a proportionally distributed variable gain amplifier having an input operably connected to the output of the preceding multiplier and an output operably connected to the second input of the subsequent multiplier. .   The communication system according to claim 1, wherein the communication system comprises a handheld telephone or a communication base station.   The slave oscillator having an output operatively connected to the second input of the phase detector has a ΣΔ-modulator operatively connected between the output of the slave oscillator and the second input of the phase detector. The communication system according to claim 1, further comprising:   The communication system according to claim 7, wherein the ΣΔ modulator includes at least one of a voltage controlled oscillator and a summing junction. Adjust the feed forward gain of the phase locked loop according to the raw error signal of the phase locked loop,
A control method of a communication system, comprising adjusting a phase-locked loop sub-oscillator according to a feed forward gain. Adjusting the feed forward gain of the phase locked loop in response to the raw error signal of the phase locked loop,
11. The method of claim 10, comprising controlling a time rate of change of feedforward gain that is proportional to the time history of the raw error signal. Controlling the time rate of change of the feedforward gain proportional to the time history of the raw error signal is
Create the product of the phase-locked loop main oscillator input and the raw error signal,
Integrate this product
12. The method of claim 11, comprising adjusting a feed forward gain in response to the product integral. Integrating the product is
13. The method of claim 12, comprising multiplying the product by the gain of the adaptation module to produce a scaled product at the adaptation module. Integrating the product is
Multiply the product by the gain of the adaptation module to produce a scaled product by the adaptation module;
Add the feedback integration result scaled by the leak factor to the product scaled by the adaptation module,
13. The method of claim 12, comprising integrating the result of adding the scaled product of the adaptation module with a feedback integration result scaled with a leak factor. Adjusting the feedforward gain according to the integral of the product is
13. The method of claim 12, comprising adding a product proportional distribution scaling version to the product integration result. Adjusting the phase-locked loop slave oscillator in response to the feedforward gain
11. The method of claim 10, comprising adjusting the input of the phase locked loop slave oscillator as a function of the product of the feed forward gain with the input of the phase locked loop. A master oscillator having an output operably connected to a first input of the phase detector;
A slave oscillator having an output operably connected to a second input of the phase detector;
A communication system comprising a forward gain adaptation module having a first input operably connected to a filtered error terminal of a phase detector. The forward gain adaptation module having a first input operably connected to a filtered error terminal of a phase detector,
A variable gain amplifier of a forward gain adaptation module operatively connected to the filtered error terminal of the phase detector;
18. The communication system of claim 17, further comprising an integrator of a forward gain adaptation module operably connected to the variable gain amplifier of the forward gain adaptation module and the slave oscillator. The variable gain amplifier of the forward gain adaptation module connected with the filtered error terminal of the phase detector is
A preceding multiplier having a first input operably connected to the filtered error terminal of the phase detector and a second input operably connected to the master oscillator;
19. The communication system of claim 18, wherein the variable gain amplifier of the forward gain adaptation module has an input operatively connected to the output of the preceding multiplier. The integrator of the forward gain adaptation module operatively connected to the variable gain amplifier of the forward gain adaptation module and the slave oscillator comprises:
A first input operably connected to an output of the integrator of the forward gain adaptation module; a second input operably connected to an input of the master oscillator; and operative to an input of the slave oscillator. A subsequent multiplier having a connected output;
19. The communication system of claim 18, wherein the integrator of the forward gain adaptation module has an input operatively connected to the output of the variable gain amplifier of the forward gain adaptation module. The integrator of the forward gain adaptation module having an input operatively connected to the output of the variable gain amplifier of the forward gain adaptation module;
21. A leak factor variable gain amplifier having an input operably connected to an integrator of the forward gain adaptation module, and an output operably connected to an integrator input of the forward gain adaptation module. The communication system described. A first input operably connected to an output of the integrator of the forward gain adaptation module; a second input operably connected to an input of the master oscillator; and operative to an input of the slave oscillator. And the subsequent multiplier having a connected output,
21. The communication system of claim 20, comprising a proportionally distributed variable gain amplifier having an input operatively connected to the output of a preceding multiplier and an output operably connected to a second input of the subsequent multiplier. .   18. A jammer cancellation module, further comprising a first input operably connected to a filtered error terminal of a phase detector and a first output operably connected to the slave oscillator. Communication system. The disturbance cancellation module having a first input operably connected to a filtered error terminal of a phase detector and a first output operably connected to the slave oscillator,
Comprising a first summing junction having a first input operably connected to a first output of the jamming cancellation module and a second input operably connected to the filtered error terminal;
24. The communication system of claim 23, wherein the slave oscillator is operatively connected to the output of the first summing junction. The slave oscillator operatively connected to the output of the first summing junction is
A first input operatively connected to the output of the first summing junction, a second input operably connected to the output of the forward gain adaptation module, and the slave oscillator are operatively connected. 25. The communication system of claim 24, further comprising a second summing junction having an output. The disturbance cancellation module having a first input operably connected to a filtered error terminal of a phase detector and a first output operably connected to the slave oscillator,
A variable gain amplifier of an interference cancellation module operatively connected to the filtered error terminal of the phase detector;
24. The communication system of claim 23, comprising: a variable gain amplifier of the disturbance cancellation module; and a disturbance cancellation module operably connected to the slave oscillator. The integrator of the disturbance cancellation module operatively connected to the variable gain amplifier of the disturbance cancellation module and the slave oscillator comprises:
27. The communication system of claim 26, further comprising an integrator of the disturbance cancellation module having an input operatively connected to the output of the variable gain amplifier of the disturbance cancellation module. The integrator of the disturbance cancellation module having an input operably connected to the output of the variable gain amplifier of the disturbance cancellation module,
A disturbance factor leak factor variable gain amplifier having an input operably connected to an output of the integrator of the disturbance cancellation module and an output operably connected to an input of the integrator of the disturbance cancellation module The communication system according to claim 27. The integrator of the disturbance cancellation module operatively connected to the variable gain amplifier of the disturbance cancellation module and the slave oscillator comprises:
27. A proportionally distributed variable gain amplifier of an interference cancellation module having an input operably connected to a filtered error terminal of a phase detector and an output operably connected to the slave oscillator. Communications system.   The communication system according to claim 17, wherein the communication system comprises a handheld telephone or a communication base station.   The slave oscillator having an output operatively connected to the second input of the phase detector has a ΣΔ-modulator operatively connected between the output of the slave oscillator and the second input of the phase detector. The communication system according to claim 17, further comprising:   32. The communication system according to claim 31, wherein the [Sigma] [Delta] -modulator comprises at least one of a voltage controlled oscillator and a summing junction. In response to the filtered error signal of the phase locked loop, the feed forward gain of the phase locked loop is adjusted,
Create a filtered error signal with interference cancellation,
A method for controlling a communication system, comprising adjusting a phase-locked loop slave oscillator in response to a feedforward gain and a filtered error signal with interference cancellation. Adjusting the feed forward gain of the phase locked loop in response to the filtered error signal of the phase locked loop;
34. The method of claim 33, comprising controlling a time rate of change of feedforward gain proportional to the time history of the filtered error signal. Controlling the time rate of change of the feedforward gain proportional to the time history of the filtered error signal is
Create the product of the phase-locked loop master oscillator input and the filtered error signal,
Integrate this product
35. The method of claim 34, comprising adjusting a feedforward gain in response to the product integral. Integrating the product is
36. The method of claim 35, comprising multiplying the product by the gain of the forward gain adaptation module to produce a scaled product with the forward gain adaptation module. Integrating the product is
Multiply the product by the gain of the forward gain adaptation module to produce a scaled product by the forward gain adaptation module;
Add the feedback integration result scaled by the leak factor to the product scaled by the forward gain adaptation module,
36. The method of claim 35, comprising integrating the result of adding the scaled product of the forward gain adaptation module with the feedback integration result scaled with the leak factor. Adjusting the feedforward gain according to the integral of the product is
36. The method of claim 35, comprising adding a product proportional distribution scaling version to the product integration result. Creating a filtered error signal with said jamming canceled
Integrate the filtered error signal,
34. The method of claim 33, comprising adding the result of the integration to a filtered error signal. Integrating the error signal is
40. The method of claim 39, comprising multiplying the product by the gain of the jamming cancellation module to produce a filtered error signal scaled by the jamming cancellation module. Integrating the filtered error signal is
Multiplying the product by the gain of the jamming cancellation module to produce a filtered error signal scaled by the jamming cancellation module;
Add the feedback integration result scaled by the leak factor of the jamming cancellation module to the filtered error signal scaled by the jamming cancellation module,
40. The method of claim 39, comprising integrating the result of adding the scaled filtered error signal of the disturbance cancellation module with the feedback integration result scaled by the leakage factor of the disturbance cancellation module. Creating the interference cancellation filtered error signal comprises:
Integrate the filtered error signal,
Adding the proportional distribution scaling version of the filtered error signal to the result of the integration of the filtered error signal;
34. The method of claim 33, comprising adding the result of the addition of the result of integrating the filtered error signal with a proportionally distributed scaling version of the filtered error signal to the filtered error signal. Adjusting the phase-locked loop slave oscillator in response to the feedforward gain and the disturbance cancellation filtered error signal,
34. Adjusting the input of the phase locked loop slave oscillator in response to adding the jammed canceled feed forward error signal to the product between the feed forward gain and the phase locked loop input. Method.

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