RU2581646C1 - Quasi-coherent modulator of quadrature phase-shift keying signals - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: invention relates to radio engineering and can be used in telecommunication systems and digital data transmission in radio systems. Device comprises tuned generator 1, reference oscillation generator 2, first and second phase detectors 3 and 4, a phase changer 5 on π/2, first and second voltage comparators 6 and 7, pulse generator 8, time delay line 9, XOR logical circuit 10, reversible counter 11, digital-analogue converter (DAC) 12, first adder 13, signal polarity switch 14, first signal multiplier 15, integrator 16, first scaling voltage divider 17, second adder 18 and loop gain setting and stabilising 19 unit (BUSPU) comprising first and second units for raising current voltage value to power of two 20 and 21, third adder 22, unit for raising current voltage value to power of ½ 23 and second voltage divider 24, and also includes keying control unit 25 (BUM) which includes second, third, fourth and fifth signal multipliers 26, 27, 28 and 29.

EFFECT: purpose of invention is integrated (simultaneous) improvement of main parameters of quasi-coherent modulator, particularly a wider capture range and retaining a synchronous operating mode, shorter time for entering synchronous operating mode, high accuracy and stability of shift-keyed phase samples in presence of destabilising factors affecting loop gain of device.

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Description

The invention relates to radio engineering and can be used in telecommunication systems and digital data transmission as part of radio systems.

The closest in technical essence and the achieved result (prototype) is a signal modulator of double phase telegraphy (USSR author's certificate SU 1390811 A1 “Modulator of signals of double phase telegraphy”, Sergo Ordzhonikidze Moscow Aviation Institute, V.E. Martirosov). The advantages of this scheme are the increased modulation speed and sufficient accuracy and stability of the installation of phase discrete in the conditions of a constant value of the loop gain of the device, which is achieved using a special additional digital control branch (prototype block 19) with an adjustable oscillator frequency. The device operates in two modes: the mode of setting the frequency and phase of oscillation of the tunable generator and the mode of synchronous operation of the modulator. In the frequency and phase adjustment mode, the output signal of the digital-to-analog converter (DAC), which has the form of a periodic linearly varying step voltage, increases at a speed determined by the pulse repetition rate generated by the counting pulse generator (GSI). If there is a frequency mismatch between the oscillation of the reference generator (OG) and the oscillation from the output of the adjustable generator (GH), the digital control branch monotonously and uniformly changes the GH frequency until the device is synchronized in frequency. Next, the phase of the output signal of the modulator is set, which is determined by the level of the reference voltage. Thus, the digital control branch ensures that the device enters the synchronous operation mode in frequency and determines the discrete phase setting in the synchronous operation mode. In this case, the higher bits of the reversible counter determine the frequency band of the synchronous operation of the quasicoherent modulator, and the lower bits of the reverse counter determine the accuracy of the discrete phase modulator. The synchronization time of the device in frequency is determined by the pulse repetition rate with GSI and the value of the initial frequency detuning. After completing the procedures for setting the frequency and phase, the device enters synchronous operation mode.

In synchronous operation, the first EXCLUSIVE OR logic circuit (prototype block 9) controls the signal switch (prototype block 8), connecting the output signal of the first polarity switch (prototype block 6) to its output when the logical signals at its inputs match, or the output signal the second switch polarity (block 7 of the prototype) otherwise. As a result, the voltage at the output of the signal switch is always positive, in the first and third quadrants of the phase mismatch between the oscillations of the reference generator and the tunable generator, it is supplied from the output of the phase detector with a sinusoidal discrimination characteristic (prototype block 2), in the second and fourth quadrants from the output of the phase detector with a cosine discriminatory characteristic (block 3 of the prototype). Thus, the nearest stable equilibrium points in the phase portrait of the system will be located at a distance π, in cases where both the initial and final states of the phase of the modulated signal belong to the quadrants of phase mismatch with even numbers, or when both the initial and final states of the phase belong to quadrants with odd numbers. In cases where there is a transition between the phase states of the modulated signal, one of which belongs to the quadrant with an even number, and the other belongs to the quadrant with odd numbers, the nearest points of stable equilibrium in the phase portrait of the system will be located at a distance π / 2.

The second and third logic circuits “EXCLUSIVE OR” (blocks 10 and 11 of the prototype) produce logical zeros at their outputs when the logical signals at their inputs coincide, or logical units otherwise. The output of the OR circuit (block 14 of the prototype) will be zero voltage in the presence of logical zeros at both its inputs, i.e. at the outputs of EXCLUSIVE OR logic circuits, or a voltage of a fixed level in the presence of at least one logical unit at its input. After the synchronous operation mode is established, the logic signals at the inputs of each EXCLUSIVE OR logic match and the voltage at the output of the OR logic is zero. When you change the logical level at any of the control inputs (conclusions 27, 28 of the prototype) of the device (or both at the same time), the output of the OR logic circuit changes the logical level of the signal to the opposite. In this case, the magnitude of the frequency control variable voltage generator changes abruptly and the synchronous operation mode of the device is temporarily disrupted. In the modulator, the phase synchronization process starts again with the reference oscillation, which leads to the establishment of the image point in the phase portrait of the device in a position corresponding to the neighboring point of stable equilibrium, which is π / 2 or π radians from the original equilibrium point, depending on the combination signals established at the control inputs of the device. This process is repeated each time the logic level is changed at any of the control inputs of the modulator. Thus, the quadrature phase shift keying of the output oscillation of the device is carried out.

As a disadvantage of the prototype circuit, it is possible to note the inefficient use of DAC bit depth. The low-order bits of the DAC are designed to set discrete (non-zero) levels of the manipulated phase of the output oscillator of the modulator. In this case, the capture and hold bands of the synchronous operation mode of the device are determined by the effect of only the high-order bits of the DAC. This limits the values of the capture and retention bands of the synchronous mode of operation of the device and reduces the accuracy of the installation of phase discrete during the modulation of the output oscillation.

The second significant drawback of the device is the long time it takes to enter the synchronous mode of operation with a significant initial frequency detuning, which is determined by the fixed and limited by the value of the upper repetition rate of the counted pulses of the DAC.

In addition, with this device, the accuracy and stability of setting the discrete values of the manipulated phase decreases when there are destabilizing factors affecting the loop gain of the device, such as spurious changes in the oscillation amplitudes of the reference and adjustable generators or a change in the transmission coefficients of phase detectors (PD), which is typical for using the device at increased operating frequencies.

The proposed scheme of a quasicoherent modulator of signals of quadrature phase shift keying has the following advantages:

- All bits of the DAC are used to synchronize the device in frequency. In this case, the minimum voltage discrete from the DAC output corresponds to the full range of the signal voltage from the PD output. This ensures the expansion of the bands of capture and retention of the synchronous mode of operation of the device at a given digit capacity of the DAC.

- The speed of entering the synchronous operation mode depends on the current value of the beat frequency at the PD outputs and, correspondingly, the higher, the higher the frequency mismatch. This provides a minimum and practically fixed value for the time of entering the synchronous operation mode at any values of the initial frequency detuning.

- The device is protected from the influence of destabilizing factors on the loop gain, since it is installed and stabilized using the installation and stabilization unit of the loopback amplifier BUSPU.

The quasi-coherent modulator of quadrature phase-shift keying signals contains a tunable generator 1, a reference oscillator 2, a first and second phase detectors 3 and 4, a phase shifter 5 on π / 2, a first and second voltage comparators 6 and 7, a pulse shaper 8, a pulse delay line 9, EXCLUSIVE OR logic 10, reversible counter 11, digital-to-analog converter (DAC) 12, first adder 13, signal polarity switch 14, first signal multiplier 15, integrator 16, first scaling voltage divider 17, the second adder 18 and the loop gain setting and stabilization unit (BUSPU) 19, comprising the first and second blocks for raising the current voltage value to the second power 20 and 21, the third adder 22, the current voltage value raising unit for ½ power 23 and the second voltage divider 24, and also contains a control unit 25 manipulation (BOOM), including a second, third, fourth and fifth multipliers of signals 26, 27, 28 and 29.

The device operates in two modes: initial synchronization mode and synchronous operation mode.

1. In the initial synchronization mode, when the device is turned on, the outputs of the first 3 and second 4 phase detectors produce quadrature beating components with a frequency corresponding to the initial frequency detuning Δω = ω _Э - ω ₀ , where ω _Э is the oscillation frequency of the reference generator 2 (EG), ω ₀ - the oscillation frequency of the tunable generator 1 at the initial value of the control voltage U _p (p - regulatory). In FIG. 2, 3, stress diagrams are shown at the points of the device circuit.

The output of the second phase detector 4 is shown in FIG. 2a, FIG. 3a, and the output of the first phase detector 3 in FIG. 2b, FIG. 3b for the cases of ω _Oe greater than ω ₀ and ω _Oe less than ω _0, respectively. The first 6 and second 7 voltage comparators from the output signals of the phase detectors form the logic signals shown in FIG. 2c, d and FIG. 3c, d. FIG. 2c corresponds to the output of the second comparator 7, FIG. 2d - the output signal of the first comparator 6 when ω _{E is} greater than ω ₀ ; similarly to FIG. 3c and FIG. 3d for the output signals of the second 7 and the first 6 comparators with ω _E less than ω ₀ . The pulse generator 8 generates short pulses at times corresponding to the trailing edge of the output pulse signal of the second comparator 7. In FIG. 2d and FIG. 3d shows these pulses passing through line 9 of the time delay. The output of the logic circuit "XOR" 10 at greater ω ω _{E 0} shown in FIG. 2e, and when _E is less than ω ω ₀ - FIG. 3rd. From the diagrams of FIG. 2d, e and FIG. 3d, f it follows that the code recorded in the reversible counter 11, and therefore the output voltage of the DAC 12 increase with ω _E greater than ω ₀ and decrease with ω _E less than ω ₀ . Diagrams of the output voltage of the DAC 12 are shown in FIG. 2g (for ω _E greater than ω ₀ ) and 3zh (for ω _E less than ω ₀ ).

Thus, when the signal at the input of the system output voltage of DAC 12 stepwise increases (if ω _e greater ω ₀₎ or decreased stepwise (when ω _e is less than ω _0), whereby the frequency being adjusted generator 1 varies in the direction of decreasing the current frequency error Δω )

When reducing the current frequency mismatch Δω to a value corresponding to the capture band of the analog branch of the GHG frequency control, including the first phase detector 3, the signal polarity switch 14, the first signal multiplier 15, the second adder 18, the integrator 16 and the first adder 13, the synchronous mode is established modulator operation.

The output signal of the signal polarity switch 14 for a case of ω _E greater than ω _{0 is} shown in FIG. 2l, and for the case of ω _E less than ω _{0 is} shown in FIG. 3l.

The output signal of the first adder 13 for a case of ω _E greater than ω _{0 is} shown in FIG. 2h, and for the case of ω _E less than ω _{0 is} shown in FIG. 3s

The formation of counting pulses for the reversible counter based on the oscillations of the differential frequency from the output of the phase detectors inside the digital branch of the GHG frequency control (including blocks 6, 7, 8, 9, 10, 11, 12, and 13) leads to a significant reduction in the time it takes to enter the synchronous operation mode quasicoherent modulator. In this case, the use of the entire width of the reversible counter in the process of synchronizing the device in frequency leads to the expansion of the capture bands and holding the synchronous mode of operation of the device.

For the correct functioning of the device and to increase the accuracy and stability of setting discretes of the manipulated phase of the output signal of the modulator, it is necessary to ensure the coordination of local discriminatory characteristics of the digital and analog branches of the GH frequency control. A single discrete ΔU _{DAC of the} step voltage generated at the DAC output should correspond to the full amplitude of the signal voltage at the output of the polarity switch equal to 2A ₀ . For this purpose, the reference voltage U _{op of the} digital-to-analog converter is used to form single analog voltage steps from the output of the DAC (ΔU _DAC = U _op / 2 ^q , where q is the resolution of the DAC) and to calculate the normalized (required) amplitude value in the first voltage divider 17 the phase mismatch signal from the output of the phase detector (A ₀ = U _op / 2 ^{q + 1} ). Further, with the help of the installation and stabilization unit of loop amplification, the actually arising value of the phase mismatch signal amplitude is reduced to the normalized (required) value (A ₀ = U _op / 2 ^{q + 1} ).

The installation and stabilization of the required loop gain coefficient of the analog control branch is carried out in the current time scale and proceeds as follows. The quadrature components of the beats with a frequency Δω from the outputs of the first and second phase detectors 3 and 4 are fed to the inputs of the first and second blocks of raising the current voltage value to the second power of 20 and 21, respectively. In FIG. 2a, b and FIG. 3a, b, respectively, for cases of ω _E greater than ω ₀ and ω _E less than ω ₀ , the signals from the outputs of the phase detectors are shown with varying amplitudes of the EG and GH signals or changing transmission coefficients of the phase detectors. The output signals of blocks 20 and 21 are fed to the first and second inputs of the third adder 22. The signal from the output of the third adder 22 is fed to the input of the block raising the current voltage value to ½ degree 23, the output of which voltage A _real (real - real) is supplied to the first input (input denominator dividing fractions) of the second voltage divider 24. The second input (input dividing the numerator of the fraction) of the second voltage divider 24 ₀ A constant voltage is supplied, the level of which corresponds to the nominal (desired) amplitude value output sig als phase detectors. The signal at the output of the second voltage divider 24 (shown in Fig. 2k and Fig. 3k, respectively, for cases of ω _e greater than ω ₀ and ω _e less than ω ₀ ) corresponds to the instantaneous current deviation of the amplitude value of the output signals of the phase detectors from the nominal value of A ₀ and represents a correction factor supplied to the second input of the first multiplier 15. The output signal of the first multiplier 15 for a case of ω _E greater than ω _{0 is} shown in FIG. 2l, and for the case of ω _E less than ω _{0 is} shown in FIG. 3l.

If we introduce the following notation: U _braid , U _syn — voltage at the output of the second and first phase detectors, respectively (braid — cosine, sin — sinus), A _real — instantaneous current value of the amplitude of the output signal of the first phase detector, U _op — reference voltage of the DAC, A ₀ - nominal (required) value of the amplitude from the output of the first phase detector, k _st - correction coefficient of the loop gain (st - stabilization) coefficient, e (t) - voltage at the output of the polarity switch 14, e * (t) - output signal block 15, then performed in BUSPU p The procedure for correcting the loop gain of a system can be described by the following relationships:

Due to the foregoing, a pairing of transmission coefficients of the analogue GHG frequency control branch (its local discriminatory characteristic is shown in Fig. 2l, Fig. 3l) and the digital control branch (its local discriminatory characteristic is shown in Fig. 2g, Fig. 3g) is implemented. This provides "stitching" and "linearization" (see diagrams of Fig. 2c, Fig. 3z) of the global discriminatory characteristics of the claimed device, which ensures the correct operation of the modulator in the presence of changes and fluctuations in the amplitudes of the EG and GH oscillations or when the transfer coefficients of phase detectors change . This increases the accuracy and stability of the installation of discrete manipulated phase in the presence of destabilizing factors affecting the loop gain of the device.

After the synchronization process is completed, the device goes into synchronous operation mode.

2. In the synchronous operation mode of the device, the process of manipulating the oscillation phase of the tunable generator into four positions is performed - -π / 4, π / 4, 3π / 4 and 5π / 4 radians in accordance with the symbol values of the two input modulating sequences α = ± 1 and β = ± 1. To achieve this goal, the first adder 13 provides a fourth input to which the first special voltage stand formed by the multiplier 26 is supplied, the absolute value of which is equal to A ₀ and manipulated in terms of polarity by the symbol stream of the modulating sequence α = ± 1. In addition, a second adder 18 is introduced into the device, the second input of which is formed by multipliers 28 and 29 with a second special voltage substitution with an absolute value equal to (√2 / 2) A ₀ and polarity-controlled by the symbol stream generated in the multiplier 27 of the modulating sequence γ = α β = ± 1. The use of the auxiliary sequence γ = α · β = ± 1 is necessary to ensure the correct operation of the modulator in the interval of phase mismatch values (π / 2; 3π / 2), on which, due to the use of the polarity switch in the demodulator structure, the phase deviation of the phase mismatch signal in the analog branch control the frequency of the tunable generator.

Thus, the manipulation control unit (BOOM) implements the procedures for generating absolute values and polarity manipulation of two special voltage supports controlling the discrete positions of the phase of the output oscillator of the modulator. The process of modulating the phase of the output oscillation in the proposed device is illustrated with the involvement of its phase portrait, shown in FIG. four.

In this device, the points of stable equilibrium of the phase portrait (corresponding to the synchronous operation mode) are located with a period of π. This is due to the use of a polarity switch in the analogue branch of the GHG frequency control and the presence of an integrator in the circuit. A phase portrait of the system with positive and negative polarity of the first special voltage stand is shown respectively in FIG. 4c and FIG. 4g The phase portrait of the system when eliminating the polarity from the switch structure for the cases of positive and negative polarity of the first special voltage stand is shown in FIG. 4a and FIG. 4b, respectively. Using the first special voltage support, points corresponding to the phase mismatches between the GHG oscillation and the EG oscillation of -45 °, 135 ° (points A ₁ and A ₁ ^* in Fig. 4c) or 45 °, 225 ° are established as points of stable equilibrium of the system (points A ₂ and A ₂ ^* in Fig. 4d).

In the initial state, when the modulator is operating in synchronous mode, the polarity of the symbols of the input modulating sequences is positive (α = 1 and β = 1), and accordingly the first and second special voltage supports also have a positive polarity. As the initial position of the phase manipulation process, a point of stable equilibrium A ₁ corresponding to the previously introduced phase mismatch equal to minus 45 ° is selected. Point A _{1 of the} phase portrait of the device will correspond to an advance of the oscillation phase from the PG output of the EG oscillation phase by 45 °.

By changing the sign of the first special voltage stand supplied to the fourth input of the first adder, the phase of the output oscillation of the device is manipulated by π radians. It is performed as follows: when the polarity of the symbol of the modulating sequence α is changed, at the output of the first adder, a surge of the voltage GH frequency control occurs, as a result of which the device will be knocked out of this stable equilibrium point (the synchronous operation mode of the device is temporarily disturbed). Next, the quasi-coherent modulator is re-synchronized at the next nearest stable equilibrium point A ₁ *, which is π radian from the initial equilibrium point.

By changing the polarity of the second special voltage stand, the phase of the output oscillation of the device is manipulated by π / 2 radians. When the polarity of the symbol of the modulating sequence β is changed, the output of the first adder triggers a surge in the frequency GH frequency control, as a result of which the device will also be knocked out of this point of stable equilibrium. Since the polarity of the second special voltage stand has changed, the phase portrait of the device will change the position of the points of stable equilibrium, their locations will correspond to the positions of the points A ₂ and A ₂ * (the phase portrait will be shifted along the ordinate by √2A ₀ ). As a result, the quasi-coherent modulator is re-synchronized at the nearest stable equilibrium point A ₂ , which is π / 2 radians from the original equilibrium point A ₁ .

The phase adjustment of the output oscillation of the device by 3π / 2 occurs with a simultaneous change in the polarity of the symbols in both modulating sequences α = ± 1 and β = ± 1.

When manipulating the polarity of the second special voltage stand, the synchronous operation between the points of stable equilibrium occurs, which correspond to the phase of the output oscillation of the modulator -45 ° and 45 ° or 135 ° and 225 °. When manipulating the polarity of the first special voltage stand, a transition occurs between the points of stable equilibrium, which correspond to the phase positions of the modulator -45 ° and 135 ° or between 45 ° and 225 °. This process is repeated many times in accordance with a change in the polarity of the symbols of the modulating sequences α = ± 1 and β = ± 1.

Thus, in the proposed device, the initial synchronization of the tunable generator and the quadrature manipulation of the phase of its oscillations are carried out according to the values: -π / 4, π / 4, 3π / 4 and 5π / 4 radians relative to the phase of the oscillation of the reference generator.

Claims (2)

1. A quasi-coherent modulator of quadrature phase-shift keying signals, comprising a reference generator, as well as a series-connected reverse counter, a digital-to-analog converter, a first adder, a tunable generator, the output of which is also an output of the device, a first phase detector, the second input of which is connected to the output of the reference generator, and a polarity switch, as well as a series-connected phase shifter on π / 2, the input of which is connected to the output of the adjustable generator, and the second phase de anector, the second input of which is connected to the output of the reference generator, characterized in that a second voltage comparator is connected in series, the first input of which is connected to the output of the second phase detector, and the second input is connected to a common bus, pulse shaper and time delay line, output which is connected to the counting input of the reversible counter, as well as series-connected first voltage comparator, the first input of which is connected to the output of the first phase detector, and the second input d is connected to the common bus, and the circuit is “EXCLUSIVE OR”, the second input of which is connected to the output of the second voltage comparator, and the output is connected to the control input of the reversible counter, and also the loop gain installation and stabilization unit (BUSPU), the first multiplier are introduced signals, the second input of which is connected to the output of the signal polarity switch, a second adder, the output of which, in addition, is connected to the second input of the first adder, and an integrator, the output of which is connected to the third the input of the first adder, and also introduced the first scaling voltage divider, the input of which is the reference voltage of the digital-to-analog converter, and the manipulation control unit (BOOM) containing the second signal multiplier, the first input of which is connected to the output of the first scaling voltage divider, and to the second input of which the input modulating sequence α = ± 1 arrives, and the output is connected to the fourth input of the first adder, as well as the third of the signals to the inputs of which the input modulating sequences α = ± 1 and β = ± 1 are received, the fourth signal multiplier, the second input of which is connected to the output of the first scaling voltage divider and the fifth signal multiplier, the second input of which receives a constant voltage corresponding to the phase mismatch, equal to π / 4, and the output of which is connected to the second input of the second adder. 2. The modulator according to claim 1, characterized in that the loop gain setting and stabilization unit (BUSPU) comprises series-connected the first block for raising the current voltage value to the second degree, the input of which is connected to the output of the first phase detector, the third adder, the block for raising the current value voltage of ½ degree and a second voltage divider connected at the input of the denominator of the division fraction, whose output is the output of the BUSPU and whose second input, which is the numerator of the division fraction, is connected to the output of the first refinement of the voltage divider and, in addition, comprises a second construction unit current voltage value to a second degree, whose input is connected to the output of the second phase detector, and an output connected to the second input of the third adder.

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