RU2566813C1 - Quasi-coherent demodulator of binary phase-shift keyed signals - Google Patents

Abstract

FIELD: physics, radio.

SUBSTANCE: invention relates to radio engineering and can be used in telecommunication systems and digital data transmission in radio systems. The device includes tunable generator 1, a reference oscillator 2, first and second phase detectors 3 and 4, a π/2 phase changer 5, first and second voltage comparators 6 and 7, a pulse former 8, a time delay line 9, an XOR logic circuit 10, a bidirectional counter 11, a digital-to-analogue converter (DAC) 12, a first adder 13, a signal polarity switch 14, a first signal multiplier 15, an integrator 16, a first scaling voltage divider 17, a second adder 18 and a loop gain setting and stabilising unit 19, having first and second units for raising the current voltage value to the power of two 20 and 21, a third adder 22, a unit for raising the current voltage value to the power of 1/2 23 and a second voltage divider 24; the device also includes a keying control unit 25, which includes second, third, fourth and fifth signal multipliers 26, 27, 28 and 29.

EFFECT: overall improvement of basic parameters of the quasi-coherent modulator, particularly: a wider capture range and maintaining a synchronous operating mode, shorter time for entering synchronous operating mode, high accuracy and stability of shift-keyed phase samples in the presence of destabilising factors affecting loop gain of the device.

2 cl, 4 dwg

Description

The invention relates to radio engineering and can be used in telecommunication systems and digital data transmission as part of radio systems.

The closest in technical essence and the achieved result (prototype) is a phase telegraph signal demodulator (USSR author's certificate SU 1392631 A1. "Phase telegraph signal demodulator". Sergo Ordzhonikidze Moscow Aviation Institute, V.E. Martirosov). The advantages of this scheme are increased noise immunity at significant information transfer rates and large ranges of initial frequency detuning under conditions of a constant value of the loop gain of the device, which is achieved using a special additional digital control branch (block 7 of the prototype) with an adjustable oscillator frequency.

The device operates as follows.

In the absence of an input signal from the demodulator, zero voltage is applied to the input of the phase mismatch search and fixing unit (prototype block 7), the reverse counter is turned on in the direction in one direction, and a continuously increasing linearly increasing voltage is generated at the DAC output, which modulates the frequency of the tunable generator through the adder, thus performing a search for the input signal of the demodulator in frequency.

When a signal appears at the input of the demodulator, a beating voltage with a ramp frequency appears at the output of the phase detector. The first amplitude comparator (block 2 of the prototype), together with the polarity switch, rectifies the voltage of the beats. When the frequencies of the input and reference oscillations approach each other, the beats cease, a constant voltage varying in level arises at the output of the phase detector and, accordingly, the polarity switch. When this voltage is exceeded above the reference level set by the reference voltage source (prototype block 9), the unidirectional counting of the reverse counter is stopped, the search mode is stopped, and the demodulator goes into synchronous operation mode.

In this device, the phase disagreement of oscillations is fixed at the inputs of the phase detector at a level corresponding to the specified voltage from the output of the reference voltage source (block 9 of the prototype).

When you manipulate the phase by 180 ° of the input signal of the demodulator, which is in synchronous operation, the voltage at the output of the phase detector retains its value, but changes its polarity to the opposite, which leads to a change in the state of the logical output of the first amplitude comparator (prototype block 2). The signal at the output of the polarity switch remains unchanged due to the controlled action from the output of the first amplitude comparator, i.e. Thus, the insensitivity of the tunable generator to information manipulation of the phase of the input signal of the demodulator is ensured.

As a disadvantage of the prototype circuit, it is possible to note the inefficient use of DAC bit depth. The low-order bits of the DAC are designed to set discrete (non-zero) levels of the phase of the output oscillation of the tunable generator relative to the phase of the input signal. In this case, the capture and hold bands of the synchronous operation mode of the device are determined by the effect of only the high-order bits of the DAC. This limits the values of the capture and hold bands of the synchronous operation mode of the device and reduces the accuracy of the phase discrete setting when setting a fixed phase mismatch during the demodulation of the input signal.

The second significant drawback of the device is the long time it takes to enter the synchronous mode of operation with a significant initial frequency detuning, which is determined by the fixed and limited by the value of the upper repetition rate of the counted pulses of the DAC.

In addition, with this device, the accuracy and stability of the setting of phase discrete values decreases when there are destabilizing factors affecting the loop gain of the device, such as spurious changes in the amplitudes of the input oscillations and oscillations from the output of the tunable generator or a change in the transmission coefficients of phase detectors (PD), which typical when using the device at higher operating frequencies.

The proposed scheme of a quasi-coherent demodulator of binary phase-shift keying signals has the following advantages:

- All bits of the DAC are used to synchronize the device in frequency. In this case, the minimum voltage discrete from the DAC output corresponds to the full range of the signal voltage from the PD output. This ensures the expansion of the bands of capture and retention of the synchronous mode of operation of the device at a given digit capacity of the DAC;

- the speed of entering the synchronous operation mode depends on the current value of the beat frequency at the PD outputs and, correspondingly, the higher, the greater the frequency mismatch. This provides a minimum and practically fixed value of the time of entering the synchronous operation mode at any values of the initial frequency detuning;

- the device is protected from the influence of destabilizing factors on the loop gain, since it is installed and stabilized using the installation and stabilization unit of the loopback amplifier BUSPU.

степень 23 и второй делитель напряжений 24.The quasi-coherent binary phase-shift signal demodulator contains a tunable generator 1, a phase shifter 2 by π / 2, a first and second phase detectors 3 and 4, a switch 5 of signal polarity, a first and second voltage comparators 6 and 7, a pulse shaper 8, a time delay line 9, EXCLUSIVE OR logic 10, reversible counter 11, digital-to-analog converter (DAC) 12, first adder 13, first signal multiplier 14, integrator 15, first scaling voltage divider 17, second signal multiplier 18 and block 19 installation and stabilization of loop amplification (BUSPU), containing the first and second blocks for raising the current voltage value to the second power of 20 and 21, the second adder 22, the block for raising the current voltage value in $$\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$$

degree 23 and the second voltage divider 24.

The device operates in two modes: initial synchronization mode and synchronous operation mode.

1. In the initial synchronization mode, when the device is turned on, the outputs of the first 3 and second 4 phase detectors produce quadrature beating components with a frequency corresponding to the initial frequency detuning Δω = ω _s -ω ₀ , where ω _s is the oscillation frequency of the input signal, ω ₀ is the frequency oscillations of the tunable generator 1 at the initial value of the control voltage U _p (p - regulatory). In FIG. 2, 3, stress diagrams are shown at the points of the device circuit.

The output of the second phase detector 4 is shown in FIG. 2a, FIG. 3a, and the output signal of the first phase detector 3 in FIG. 2b, FIG. 3b for cases _with ω _c greater than ω ₀ and ω _c less than ω _0, respectively. The first 6 and second 7 voltage comparators (KH) from the output signals of the phase detectors form the logic signals shown in FIG. 2c, d and FIG. 3c, d. FIG. 2, corresponds to the output signal of the second comparator 7, FIG. 2, d - the output signal of the first comparator 6 when ω _with more than ω ₀ ; similarly to FIG. 3c and FIG. 3e for the output signals of the second 7 and the first 6 comparators for ω _с less than ω ₀ . The pulse generator 8 generates short pulses at times corresponding to the trailing edge of the output pulse signal of the second comparator 7. In FIG. 2d and FIG. 3d shows these pulses passing through the time delay line 9. The output of the “EXCLUSIVE OR” logic circuit 10 when ω _{c is} greater than ω _{0 is} shown in FIG. 2e, and for ω _с less than ω ₀ , in FIG. 3, e. From the diagrams of FIG. 2d, e and FIG. 3d, f it follows that the code recorded in the reversible counter 11, and therefore the output voltage of the DAC 12 increase at ω _s more than ω ₀ and decrease at ω _s less than ω ₀ . Diagrams of the output voltage of the DAC 12 are shown in FIG. 2, g (for ω _с greater than ω ₀ ) and 3, g (for ω _с less than ω ₀ ).

Thus, when a signal appears at the input of the system, the output voltage of the DAC 12 increases stepwise (at ω _с greater than ω ₀ ) or decreases stepwise (at ω _с less than ω ₀ ), as a result of which the frequency of the tunable oscillator 1 changes to decrease the current frequency mismatch Δω .

When the current frequency mismatch Δω is reduced to a value corresponding to the capture band of the analog branch of the GHG frequency control, which includes the first phase detector 3, the signal polarity switch 5, the first signal multiplier 14, the integrator 15 and the first adder 13, the synchronous operation of the demodulator is established.

The output signal of the signal polarity switch 5 for the case of ω _with greater than ω _{0 is} shown in FIG. 2, l, and for the case of ω _с less than ω _{0 is} shown in FIG. 3, l

The output signal of the first adder 13 for the case of ω _with greater than ω _{0 is} shown in FIG. 2c, and for the case of ω _c less than ω _{0 is} shown in FIG. 3, c.

The formation of counting pulses for the reversible counter based on the oscillations of the differential frequency from the output of the phase detectors inside the digital branch of the GHG frequency control (including blocks 6, 7, 8, 9, 10, 11, 12, and 13) leads to a significant reduction in the time it takes to enter the synchronous operation mode quasicoherent demodulator. In this case, the use of the entire capacity of the reversible counter during the synchronization of the device in frequency leads to the expansion of the capture bands and the retention of the synchronous mode of operation of the device.

For the correct functioning of the device and increase the accuracy and stability of demodulation of the input signal by the demodulator, it is necessary to ensure the coordination of local discriminatory characteristics of the digital and analog branches of the GH frequency control. A single discrete ΔU of the _DAC formed at the output of the step-by-step DAC must correspond to the full amplitude of the signal voltage at the output of the polarity switch, equal to 2A ₀ . For this purpose, the reference voltage U _{op of the} digital-to-analog converter is used to form single analog voltage steps from the DAC output (ΔU _DAC = U _op / 2 ^q , where q is the DAC bit capacity) and to calculate the normalized (required) amplitude value in the first voltage divider 17 the phase mismatch signal from the output of the phase detector (A ₀ = U _op / 2 ^{q + 1} ). Then, using the installation and stabilization unit of loop gain 19, the actually arising value of the phase mismatch signal amplitude is reduced to the normalized (required) value (A ₀ = U _op / 2 ^{q + 1} ).

The installation and stabilization of the required loop gain coefficient of the analog control branch is carried out in the current time scale and proceeds as follows.

степень 23, с выхода которого напряжение А_реал (реал - реальное) поступает на первый вход (вход знаменателя дроби деления) второго делителя напряжений 24. На второй вход (вход числителя дроби деления) второго делителя напряжений 24 поступает постоянное напряжение А₀, уровень которого соответствует номинальному (требуемому) значению амплитуды выходных сигналов фазовых детекторов. Сигнал на выходе второго делителя напряжений 24 (показанный на фиг. 2,к и фиг. 3,к соответственно для случаев ω_с больше ω₀ и ω_с меньше ω₀) соответствует мгновенному текущему отклонению значения амплитуды выходных сигналов фазовых детекторов от номинального значения A₀ и представляет собой корректирующий коэффициент, подаваемый на второй вход первого перемножителя 14. Выходной сигнал первого перемножителя 14 для случая ω_с больше ω₀ показан на фиг. 2,л, а для случая ω_с меньше ω₀ показан на фиг. 3,л.The quadrature components of the beats with a frequency Δω from the outputs of the first and second phase detectors 3 and 4 are fed to the inputs of the first and second blocks of raising the current voltage value to the second power of 20 and 21, respectively. In FIG. 2a, b and FIG. 3a, b, respectively, for cases _with ω _with greater than ω ₀ and ω _with less than ω ₀ , the signals from the outputs of the phase detectors are shown for changing signal amplitudes at the input of the device and from the GHG output or changing transmission coefficients of phase detectors. The output signals of blocks 20 and 21 are fed to the first and second inputs of the second adder 22. The signal from the output of the second adder 22 is fed to the input of the block for raising the current voltage value to $$\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$$

degree 23, from the output of which voltage A _real (real - real) is supplied to the first input (input of the denominator of the fraction fraction) of the second voltage divider 24. The second voltage (input of the numerator of the fraction fraction) of the second voltage divider 24 receives a constant voltage A ₀ , the level of which corresponds to the nominal (required) value of the amplitude of the output signals of the phase detectors. The signal at the output of the second voltage divider 24 (shown in Fig. 2, k and Fig. 3, k, respectively, for cases ω _with greater than ω ₀ and ω _with less than ω ₀ ) corresponds to the instantaneous current deviation of the amplitude value of the output signals of the phase detectors from the nominal value A ₀ and represents the correction coefficient applied to the second input of the first multiplier 14. The output signal of the first multiplier 14 for the case of ω _with greater than ω _{0 is} shown in FIG. 2, l, and for the case of ω _с less than ω _{0 is} shown in FIG. 3, l

If we introduce the following notation: U _braid , U _syn — voltage at the output of the second and first phase detectors, respectively (braid — cosine, sin — sinus), A _real — instantaneous current value of the amplitude of the output signal of the first phase detector, U _op — reference voltage of the DAC, A ₀ is the nominal (required) value of the amplitude from the output of the first phase detector, k _c is the correction coefficient of the loop gain (st - stabilization), e (t) is the voltage amplitude at the output of the polarity switch 5, e * (t) is the signal to block output 14, then executed in BUSPU, the procedure for correcting the loop gain of a system can be described by the following relationships:

one $$A_{Re\mathrm{but}l}={(U_{\mathrm{to}\mathrm{about}\mathrm{from}}^2+U_{\mathrm{from}\mathrm{and}n}^2)}^{\mathrm{one}/2}$$

2. And ₀ = U _op / 2 ^{q + 1}

3. k _article = A ₀ / A _real

4. e * (t) = e (t) · k _Article

As a result of the above, a pairing of transmission coefficients of the analogue GHG frequency control branch (its local discriminatory characteristic is shown in Fig. 2, l, Fig. 3, l) and the digital control branch (its local discriminatory characteristic is shown in Fig. 2, g, Fig. 3g). This provides "stitching" and "linearization" (see diagrams of Fig. 2, h, Fig. 3, h) of the global discriminatory characteristics of the claimed device, which ensures the correct operation of the demodulator in the presence of changes and fluctuations in the amplitude of oscillations of the input signal and the GHG signal or when changing the transfer coefficients of phase detectors, that is, in the presence of destabilizing factors affecting the loop gain of the device.

After the synchronization process is completed, the device goes into synchronous operation mode.

2. In the synchronous operation mode of the device, the process of demodulation of the input oscillation is carried out, as a result of which estimates α * of the symbol values of the transmitted information sequence α are obtained. To eliminate the influence of phase manipulation of the input signal on the reference oscillation of the adjustable oscillator generated in the demodulator, a fourth input is provided in the first adder 13, to which a special voltage stand is supplied, the absolute value of which is equal to A ₀ and polarity-manipulated in the second multiplier 18 by the stream of demodulated estimates of input signal symbols α * = ± 1.

In this device, the points of stable equilibrium of the phase portrait (corresponding to the synchronous operation mode) are located with a period π, as shown in FIG. 4, c. This type of phase portrait is due to the use of a polarity switch in the analog branch of the GHG frequency control and the presence of an integrator in the circuit. The phase portrait when removing polarity from the structure of the switch is shown in FIG. 4 a. A signal from the output of the first voltage comparator shown in FIG. 4b (pulse signal), which also shows the signal from the output of the second PD 4 (cosine co-signal).

When the device is turned on, the initial synchronization of the demodulator occurs, after which the oscillation from the GHG output and the input oscillation are in-phase or are out of phase. The steady state corresponds to one of the points of stable equilibrium A or A * in the phase portrait of the device (see Fig. 4, c). Suppose, as a result of synchronization, the device turned out to be at point A (in-phase oscillations). During phase manipulation by 180 ° of the input signal of the demodulator, which is in synchronous operation, the voltage at the output of the second phase detector retains its value, but changes its polarity to the opposite, which leads to a change in the state of the logical output of the second voltage comparator 7. There is a surge in the control of the GHG frequency voltage, as a result of which the device will be knocked out of the point of stable equilibrium. Since the polarity of the logical signal at the output of the second voltage comparator changes, the image point C moves to the interval of the phase portrait, where the closest point of stable equilibrium is A * (see Fig. 4, c). That is, the phase of the signal from the GHG output changes by 180 °, adjusting to the phase change in the input signal. To avoid re-synchronization of the GHG in the position with a phase shift of 180 °, a special voltage stand is applied to the fourth input of the first adder, which shifts the system image point back to the interval with the nearest stable equilibrium point A. This stand is polarity-controlled by the signal from the output of the second a voltage comparator, the polarity of the signal at the output of which will change each time you manipulate the phase of the input signal and remain constant over the transmission interval of the sim ol. The estimates of the transmitted symbols α * = ± 1 are taken from the output of the second voltage comparator.

Thus, synchronization of the tunable generator of the quasi-coherent demodulator of binary phase manipulation and demodulation of the input signal in it is carried out and maintained.

Claims (2)

1. A quasi-coherent demodulator of binary phase-shift keying signals, comprising a reversible counter, a digital-to-analog converter, a first adder, an adjustable oscillator, a first phase detector, the second input of which is connected to the demodulator input, and a signal polarity switch, characterized in that for the purpose of complex (simultaneous ) improving the basic parameters of a quasi-coherent demodulator, namely: expanding the capture bands and holding the synchronous operation mode, reducing the input time In the synchronous mode of operation, to increase noise immunity in the presence of destabilizing factors affecting the loop gain of the device, a π / 2 phase shifter is introduced into the device, the input of which is connected to the output of the tunable generator, the second phase detector, the second input of which is connected to the input of the demodulator , a second voltage comparator, the second input of which is connected to a common bus, a pulse shaper and a time delay line, the output of which is connected to the counting input ohm of the reversible counter, and the first voltage comparator is connected in series, the first input of which is connected to the output of the first phase detector, and the second input is connected to the common bus, and the circuit is EXCLUSIVE OR, the second input of which is connected to the output of the second voltage comparator, and the output is connected to the control of the counting polarity by the input of the reversing counter, and also the loop gain setting and stabilization unit (BUSPU), the first signal multiplier, the second input to is connected to the output of the signal polarity switch, and the output is additionally connected to the second input of the first adder, and the integrator, the output of which is connected to the third input of the first adder, is also connected in series with the first scaling voltage divider, the input of which is the reference voltage of the digital-to-analog converter, and the second signal multiplier, the output of which is connected to the fourth input of the first adder and the second input of which is connected to the output of the second voltage comparator. 2. The demodulator according to claim 1, characterized in that the loop gain installation and stabilization unit (BUSPU) comprises series-connected the first block for raising the current voltage value to the second degree, the input of which is connected to the output of the first phase detector, the second adder, the block for raising the current value voltage in $$\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$$

the degree and the second voltage divider connected at the input of the denominator of the division fraction, the output of which is the output of the BUSPU and the second input of which is the numerator of the division fraction, is connected to the output of the first scaling voltage divider, and, in addition, contains a second block for raising the current voltage value to the second degree whose input is connected to the output of the second phase detector, and the output is connected to the second input of the second adder.

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