RU2567002C1 - Quasi-coherent modulator of binary phase-shift keyed signals - Google Patents

Abstract

FIELD: physics, radio.

SUBSTANCE: invention relates to radio engineering and can be used in telecommunication systems and digital data transmission in radio systems. The device includes tunable generator 1, a reference oscillator 2, first and second phase detectors 3 and 4, a π/2 phase changer 5, first and second voltage comparators 6 and 7, a pulse former 8, a time delay line 9, an XOR logic circuit 10, a bidirectional counter 11, a digital-to-analogue converter 12, a first adder 13, a signal polarity switch 14, a first signal multiplier 15, an integrator 16, a first scaling voltage divider 17, a second adder 18 and a loop gain setting and stabilising unit 19, having first and second units for raising the current voltage value to the power of two 20 and 21, a second adder 22, a unit for raising the current voltage value to the power of S 23 and a second voltage divider 24.

EFFECT: overall improvement of basic parameters of the quasi-coherent modulator, particularly: a wider capture range and maintaining a synchronous operating mode, shorter time for entering synchronous operating mode, high accuracy and stability of shift-keyed phase samples in the presence of destabilising factors affecting loop gain of the device.

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Description

The invention relates to radio engineering and can be used in telecommunication systems and digital data transmission as part of radio systems.

The closest in technical essence and the achieved result (prototype) is a phase telegraph signal modulator (USSR author's certificate SU 1392628 A1 “Phase telegraph signal modulator”, Sergo Ordzhonikidze Moscow Aviation Institute, V.E. Martirosov). The advantages of this scheme are the increased modulation speed and sufficient accuracy and stability of the installation of phase discrete in the conditions of a constant value of the loop gain of the device, which is achieved using a special additional digital control branch (block 10 of the prototype) with the frequency of the tunable generator. The device operates in two modes: the mode of setting the frequency and phase of oscillation of the tunable generator and the mode of synchronous operation of the modulator. In the frequency and phase adjustment mode, the output signal of the digital-to-analog converter (DAC), which has the form of a periodic linearly varying step voltage, increases at a speed determined by the pulse repetition rate generated by the counting pulse generator (GSI). If there is a frequency mismatch between the oscillation of the reference generator (EG) and the oscillation from the output of the adjustable generator (GH), the digital control branch monotonously and uniformly changes the GH frequency until the device is synchronized in frequency. Next, the phase of the output signal of the modulator is set, which is determined by the level of the reference voltage. Thus, the digital control branch ensures that the device enters the synchronous operation mode in frequency and determines the discrete phase setting in the synchronous operation mode. In this case, the highest bits of the reverse counter determine the frequency band of the synchronous mode of the quasicoherent modulator, and the lower bits of the reverse counter determine the accuracy of the discrete phase modulator. The synchronization time of the device in frequency is determined by the pulse repetition rate with GSI and the value of the initial frequency detuning.

After establishing a synchronous mode of operation at the output of the EXCLUSIVE OR logic, the signal is 0 if the logical signals at its inputs match. Otherwise, the output signal of the EXCLUSIVE OR logic circuit is equal to 1. When the logic level of the modulating signal arriving at the control input of the EXCLUSIVE OR circuit is changed, the logical level is reversed at its output. In this case, the magnitude of the frequency control variable voltage generator changes abruptly and the synchronous operation mode of the device is temporarily disrupted. In the modulator, the synchronization process with the reference oscillation starts again, which leads to the establishment of the image point in the phase portrait of the device in a position corresponding to the neighboring point of stable equilibrium, which is π radian from the original equilibrium point. The use of an amplitude comparator (AK) and a polarity switch (KP) in the structure of the modulator leads to the fact that the period of arrangement of the points of stable equilibrium of the device in the phase portrait is π. That is, the modulator is re-synchronized in a position out of phase with respect to the original one. This process is repeated every time the logic level is changed at the control input of the modulator. Thus, binary phase manipulation of the output oscillation of the device is carried out.

As a disadvantage of the prototype circuit, it is possible to note the inefficient use of DAC bit depth. The low-order bits of the DAC are designed to set the discrete (non-zero) level of the modulator output phase manipulated by π. In this case, the capture and hold bands of the synchronous operation mode of the device are determined by the effect of only the high-order bits of the DAC. This limits the values of the capture and retention bands of the synchronous mode of operation of the device and reduces the accuracy of the installation of phase discrete during the modulation of the output oscillation.

The second significant drawback of the device is the long time it takes to enter the synchronous mode of operation with a significant initial frequency detuning, which is determined by the fixed and limited by the value of the upper repetition rate of the counted pulses of the DAC.

In addition, with this device, the accuracy and stability of setting discrete values of π-phase-manipulated discs decreases when there are destabilizing factors affecting the loop gain of the device, such as spurious changes in the oscillation amplitudes of the reference and tunable oscillators or a change in the transfer coefficient of the phase detector (PD), which is typical when using the device at higher operating frequencies.

The proposed scheme of a quasicoherent modulator of signals of binary phase manipulation has the following advantages:

- All bits of the DAC are used to synchronize the device in frequency. In this case, the minimum voltage discrete from the DAC output corresponds to the full range of the signal voltage from the PD output. This ensures the expansion of the bands of capture and retention of the synchronous mode of operation of the device at a given digit capacity of the DAC.

- The speed of entering the synchronous operation mode depends on the current value of the beat frequency at the output of the PD and, accordingly, the higher, the higher the frequency mismatch. This provides a minimum and practically fixed value for the time of entering the synchronous operation mode at any values of the initial frequency detuning.

- The device is protected from the influence of destabilizing factors on the loop gain, since it was installed and stabilized using the installation and stabilization unit of the loopback amplifier BUSPU.

The quasi-coherent binary phase-shift signal modulator (Fig. 1) contains a tunable generator 1, a reference oscillator 2, a first and second phase detectors 3 and 4, a phase shifter 5 on π / 2, a first and second voltage comparator 6 and 7, a pulse shaper 8, a time delay line 9, an “EXCLUSIVE OR” logic circuit 10, a reversible counter 11, a digital-to-analog converter 12, a first adder 13, a signal polarity switch 14, a first signal multiplier 15, an integrator 16, a first scaling voltage divider 17, the second signal multiplier 18 and the loop gain setting and stabilization unit (BUSPU) 19, comprising the first and second blocks for raising the current voltage value to the second power 20 and 21, the second adder 22, the current voltage value raising unit in ½ power 23 and the second voltage divider 24 .

The device operates in two modes: initial synchronization mode and synchronous operation mode.

1. In the initial synchronization mode, when the device is turned on, the outputs of the first 3 and second 4 phase detectors produce quadrature beating components with a frequency corresponding to the initial frequency detuning Δω = ω _Э - ω ₀ , where ω _Э is the oscillation frequency of the reference generator 2, ω ₀ - the oscillation frequency of the tunable generator 1 at the initial value of the control voltage U _p (p - regulatory). In FIG. 2, 3, stress diagrams are shown at the points of the device circuit.

The output of the second phase detector 4 is shown in FIG. 2a, FIG. 3a, and the output of the first phase detector 3 is in FIG. 2b, FIG. 3b for the cases of ω _Oe greater than ω ₀ and ω _Oe less than ω _0, respectively. The first 6 and second 7 voltage comparators from the output signals of the phase detectors form the logic signals shown in FIG. 2c, d and FIG. 3c, d. FIG. 2c corresponds to the output of the second comparator 7, FIG. 2d - the output signal of the first comparator 6 when ω _{E is} greater than ω ₀ ; similarly to FIG. 3c and FIG. 3d for the output signals of the second 7 and the first 6 comparators with ω _E less than ω ₀ . The pulse generator 8 generates short pulses at times corresponding to the trailing edge of the output signal of the second comparator 7. In FIG. 2d and FIG. 3d shows these pulses passing through line 9 of the time delay. The output of the logic circuit "XOR" 10 at greater ω ω _{E 0} shown in FIG. 2e, and when _E is less than ω ω ₀ - FIG. 3rd. From the diagrams of FIG. 2d, e and FIG. 3d, f it follows that the code recorded in the reversible counter 11, and therefore the output voltage of the DAC 12 increase with ω _E greater than ω ₀ and decrease with ω _E less than ω ₀ . Diagrams of the output voltage of the DAC 12 are shown in FIG. 2g (for ω _E greater than ω ₀ ) and 3zh (for ω _E less than ω ₀ ).

Thus, when the signal at the input of the system output voltage of DAC 12 stepwise increases (if ω _e greater ω ₀₎ or decreased stepwise (when ω _e is less than ω _0), whereby the frequency being adjusted generator 1 varies in the direction of decreasing the current frequency error Δω .

When reducing the current frequency mismatch Δω to a value corresponding to the capture band of the analog branch of the GHG frequency control, including the first phase detector 3, the signal polarity switch 14, the first signal multiplier 15, the integrator 16, the first adder 13 and the tunable generator 1, synchronous mode of operation of the modulator.

The output signal of the signal polarity switch 14 for a case of ω _E greater than ω _{0 is} shown in FIG. 2l, and for the case of ω _E less than ω _{0 is} shown in FIG. 3l.

The output signal of the first adder 13 for a case of ω _E greater than ω _{0 is} shown in FIG. 2h, and for the case of ω _E less than ω _{0 is} shown in FIG. 3s

The formation of counting pulses for a reversible counter based on the oscillations of the differential frequency from the output of the phase detectors inside the digital branch of the GHG frequency control (including blocks 6, 7, 8, 9, 10, 11, and 12) leads to a significant reduction in the time it takes to enter the synchronous operation mode of a quasicoherent modulator . In this case, the use of the entire capacity of the reversible counter during the synchronization of the device in frequency leads to the expansion of the capture bands and the retention of the synchronous mode of operation of the device.

For the correct functioning of the device and to increase the accuracy and stability of setting discretes of the manipulated phase of the output signal of the modulator, it is necessary to ensure the coordination of local discriminatory characteristics of the digital and analog branches of the GH frequency control. A single discrete ΔU _{DAC of the} step voltage generated at the DAC output should correspond to the full amplitude of the signal voltage at the output of the polarity switch equal to 2A ₀ . For this purpose, the reference voltage U _{op of the} digital-to-analog converter is used to form single analog voltage steps from the output of the DAC (ΔU _DAC = U _op / 2 ^q , where q is the resolution of the DAC) and to calculate the normalized (required) amplitude value in the first voltage divider 17 the phase mismatch signal from the output of the phase detector (A ₀ = U _op / 2 ^{q + 1} ). Further, with the help of the installation and stabilization unit of loop amplification, the actually arising value of the phase mismatch signal amplitude is reduced to the normalized (required) value (A ₀ = U _op / 2 ^{q + 1} ).

The installation and stabilization of the required loop gain coefficient of the analog control branch is carried out in the current time scale and proceeds as follows. The quadrature components of the beats with a frequency Δω from the outputs of the first and second phase detectors 3 and 4 are fed to the inputs of the first and second blocks of raising the current voltage value to the second power of 20 and 21, respectively. In FIG. 2a, b and FIG. 3a, b, respectively, for cases of ω _E greater than ω ₀ and ω _E less than ω ₀ , the signals from the outputs of the phase detectors are shown with varying amplitudes of the EG and GH signals or changing transmission coefficients of the phase detectors. The output signals of blocks 20 and 21 are fed to the first and second inputs of the second adder 22. The signal from the output of the second adder 22 is fed to the input of the block raising the current voltage value to ½ degree 23, from the output of which voltage A _real (real - real) is supplied to the first input (input denominator dividing fractions) of the second voltage divider 24. The second input (input dividing the numerator of the fraction) of the second voltage divider 24 ₀ A constant voltage is supplied, the level of which corresponds to the nominal (desired) amplitude value output signa s phase detectors. The signal at the output of the second voltage divider 24 (shown in Fig. 2k and Fig. 3k, respectively, for cases of ω _e greater than ω ₀ and ω _e less than ω ₀ ) corresponds to the instantaneous current deviation of the amplitude value of the output signals of the phase detectors from the nominal value A ₀ and a correction factor supplied to the second input of the first multiplier 15. The output signal of the first multiplier 15 for a case of ω _E greater than ω _{0 is} shown in FIG. 2l, and for the case of ω _E less than ω _{0 is} shown in FIG. 3l.

If we introduce the following notation: U _braid , U _syn — voltage at the output of the second and first phase detectors, respectively (braid — cosine, sin — sinus), A _real — instantaneous current value of the amplitude of the output signal of the first phase detector, U _op — PAP reference voltage, A ₀ - nominal (required) value of the amplitude from the output of the first phase detector, k _st - correction coefficient of the loop gain coefficient (st - stabilization), e (t) - voltage at the output of the voltage comparator 14, e * (t) - output signal block 15, then run in BUSPU The procedure for correcting the value of the loop gain of the system can be described by the following relationships:

Due to the foregoing, a pairing of transmission coefficients of the analogue GHG frequency control branch (its local discriminatory characteristic is shown in Fig. 2l, Fig. 3l) and the digital control branch (its local discriminatory characteristic is shown in Fig. 2g, Fig. 3g) is implemented. This provides "stitching" and "linearization" (see diagrams of Fig. 2h, Fig. 3h) of the global discriminatory characteristics of the claimed device and ensures the correct operation of the modulator in the presence of changes and fluctuation of the amplitudes of the EG and GH oscillations or when the transfer coefficients of the phase detectors change. After the synchronization process is completed, the device goes into synchronous operation mode.

2. In the synchronous operation mode of the device, the process of manipulating the oscillation phase of the tunable generator into two positions 0 or π radians is carried out. To this end, a fourth input is provided in the first adder 13, to which a special voltage support is applied with an absolute value equal to A ₀ and polarity-manipulated by the symbol stream of the modulating sequence α = ± 1 in the second multiplier 18.

In this device, the points of stable equilibrium of the phase portrait (corresponding to the synchronous operation mode) are located with a period π, as shown in Fig. 4c. This type of phase portrait is due to the use of a polarity switch in the analog branch of the GHG frequency control and the presence of an integrator in the circuit. The phase portrait when removing polarity from the structure of the switch is shown in FIG. 4a. The signal from the output of the second voltage comparator shown in FIG. 4b (pulse signal), which also shows the signal from the output of the second PD (cosine signal).

When the device is turned on, the initial synchronization of the modulator occurs, which corresponds to one of the points of stable equilibrium in the phase portrait of the device. When the polarity of the symbol of the modulating sequence α is changed at the output of the first adder, a surge of the voltage GH frequency control occurs, as a result of which the device will be knocked out of this point of stable equilibrium. Next, the quasi-coherent modulator is re-synchronized at the next nearest stable equilibrium point, which is π radian from the original equilibrium point. This process is repeated many times in accordance with a change in the polarity of the symbols of the modulating sequence α = ± 1.

Thus, in the proposed device, the initial synchronization of the tunable generator and binary manipulation of the phase of its oscillation is carried out: 0 or π radian relative to the phase of the generator of the reference oscillation.

Claims (2)

1. A quasi-coherent binary phase-shift signal modulator comprising a reference oscillator, as well as a series-connected reverse counter, a digital-to-analog converter, a first adder, an adjustable oscillator, the output of which is also an output of the device, a first phase detector, the second input of which is connected to the output of the reference generator, and polarity switch, characterized in that in order to comprehensively (simultaneously) improve the basic parameters of the quasi-coherent modulator, namely: capture and hold bands of the synchronous operation mode, reducing the time of entering the synchronous operation mode, increasing the accuracy and stability of setting discretes of the manipulated phase in the presence of destabilizing factors affecting the loop gain of the device, a phase shifter connected to π / 2, the input of which is connected with the output of the adjustable generator, the second phase detector, the second input of which is connected to the output of the reference generator, the second voltage comparator, W The second input of which is connected to a common bus, a pulse shaper and a time delay line, the output of which is connected to a counting input of a reversible counter, and the first voltage comparator is connected in series, the first input of which is connected to the output of the first phase detector, and the second input is connected to a common bus , EXCLUSIVE OR logic circuit, the second input of which is connected to the output of the second voltage comparator, and the output is connected to the counter polarity control input of the reverse counter, and also entered sequentially connected loop gain installation and stabilization unit (BUSPU), a first signal multiplier, the second input of which is connected to the output of the signal polarity switch, and the output, in addition, is connected to the second input of the first adder, and an integrator whose output is connected to the third input of the first adder and also introduced in series connected the first scaling voltage divider, to the input of which the reference voltage of the digital-to-analog converter is supplied, and the second signal multiplier, the output to which is connected to the fourth input of the first adder and to the second input of which a binary sequence of characters equal in value to plus or minus one is supplied that modulates the phase of the device output signal. 2. The quasi-coherent modulator according to claim 1, characterized in that the loop gain setting and stabilization unit (BUSPU) comprises serially connected a first block for raising the current voltage value to a second degree, the input of which is connected to the output of the first phase detector, a second adder, a block for raising the current voltage values of ½ degree and a second voltage divider connected at the input of the denominator of the division fraction, the output of which is the output of the BUSPU and the second input of which is the numerator of the division fraction, sub li ne to the output of the first scaling of the voltage divider and, in addition, it comprises a second construction unit current value to a second voltage level of an input of which is connected to the second output of the phase detector and an output connected to the second input of the second adder.

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