JP2011524463A - 光透過性デバイス用導電性構造 - Google Patents
光透過性デバイス用導電性構造 Download PDFInfo
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- TVIVIEFSHFOWTE-UHFFFAOYSA-K tri(quinolin-8-yloxy)alumane Chemical compound [Al+3].C1=CN=C2C([O-])=CC=CC2=C1.C1=CN=C2C([O-])=CC=CC2=C1.C1=CN=C2C([O-])=CC=CC2=C1 TVIVIEFSHFOWTE-UHFFFAOYSA-K 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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Abstract
【選択図】図1
Description
Claims (28)
- 光透過性デバイス用導電性構造であって、
第1のプロセス条件を用いて形成される第1の透明導電性材料層と、
直接前記第1の層上に形成される少なくとも1つの他の透明導電性材料層であって、前記第1のプロセス条件とは異なる第2のプロセス条件を用いて形成される少なくとも1つの他の透明導電性材料層とを備え、
前記少なくとも1つの他の透明導電性材料層の形成中に、前記第1の層が、前記光透過性デバイスに対する悪影響を低減させるためのバッファ層として機能する、構造。 - 前記第1のプロセス条件が、第1の堆積電力および第1の堆積温度を有し、
前記第2のプロセス条件が、第2の堆積電力および第2の堆積温度を有し、
前記第1の堆積電力、前記第1の堆積温度、および前記第2の堆積温度がそれぞれ、温度および堆積電力により引き起こされる、前記光透過性デバイスに対する悪影響が低減するように選択され、
前記第2の堆積電力が、前記少なくとも1つの他の透明導電性材料層の所望の膜品質をもたらすように選択される、請求項1に記載の構造。 - 1つまたは複数の金属層をさらに備え、前記第1の層が前記金属層の上に形成される、請求項1または2に記載の構造。
- 前記少なくとも1つの他の透明導電性材料層と、それが上に形成された前記第1の層が共に、前記デバイスの光出力を向上させるための屈折率整合構造として機能する、請求項1〜3のいずれか1項に記載の構造。
- 前記少なくとも1つの他の透明導電性材料層と、それが上に形成された前記第1の層が共に、前記デバイスの電流拡がりを向上させるように機能する、請求項1〜4のいずれか1項に記載の構造。
- 前記第1の層、および前記少なくとも1つの他の透明導電性材料層が、物理堆積技法、化学堆積技法、または両方を用いて形成される、請求項1〜5のいずれか1項に記載の構造。
- 前記第1の層が、直流(DC)マグネトロンスパッタリングを用いて形成される、請求項6に記載の構造。
- 前記第1の堆積電力が約10Wの電力である、請求項1〜7のいずれか1項に記載の構造。
- 前記少なくとも1つの他の透明導電性材料層が、高周波(RF)マグネトロンスパッタリングを用いて形成される、請求項6〜8のいずれか1項に記載の構造。
- 前記第2の堆積電力が約100Wの電力である、請求項1〜9のいずれか1項に記載の構造。
- 前記第1の層の堆積中の基板温度が、約60℃以下である、請求項1〜10のいずれか1項に記載の構造。
- 前記少なくとも1つの他の透明導電性材料層の堆積中の前記基板温度が、約60℃以下である、請求項1〜11のいずれか1項に記載の構造。
- 前記第1の層、および前記少なくとも1つの他の透明導電性材料層がそれぞれ、SnO2、Ga−In−Sn−O(GITO)、Zn−In−Sn−O(ZITO)、Ga−In−O(GIO)、Zn−In−O(ZIO)、In−Sn−O(ITO)、および他の透明導電性材料からなる群から選択される、1種または複数種の材料を含む、請求項1〜12のいずれか1項に記載の構造。
- 前記第1の層、および前記少なくとも1つの他の透明導電性材料層が、同じ透明導電性材料を含む、請求項13に記載の構造。
- 光透過性デバイス用導電性構造を形成する方法であって、
第1の透明導電性材料層を、第1のプロセス条件を用いて形成すること、
直接前記第1の層上に、少なくとも1つの他の透明導電性材料層を、前記第1のプロセス条件とは異なる第2のプロセス条件を用いて形成すること、を含み、
前記少なくとも1つの他の透明導電性材料層の形成中に、前記第1の層が、前記光透過性デバイスに対する悪影響を低減させるためのバッファ層として機能する、方法。 - 前記第1のプロセス条件が、第1の堆積電力および第1の堆積温度を有し、
前記第2のプロセス条件が、第2の堆積電力および第2の堆積温度を有し、
前記方法がさらに、
前記第1の堆積電力、前記第1の堆積温度、および前記第2の堆積温度をそれぞれ、温度および堆積電力により引き起こされる、前記光透過性デバイスに対する悪影響が低減するように選択すること、ならびに
前記第2の堆積電力を、前記少なくとも1つの他の透明導電性材料層の所望の膜品質をもたらすように選択することを含む、請求項15に記載の方法。 - 1つまたは複数の金属層を設けること、および前記第1の層を前記金属層の上に形成することをさらに含む、請求項15または16に記載の方法。
- 前記少なくとも1つの他の透明導電性材料層と、それが上に形成された前記第1の層が共に、前記デバイスの光出力を向上させるための屈折率整合構造として機能する、請求項15〜17のいずれか1項に記載の方法。
- 前記少なくとも1つの他の透明導電性材料層と、それが上に形成された前記第1の層が共に、前記デバイスの電流拡がりを向上させるように機能する、請求項15〜18のいずれか1項に記載の方法。
- 前記第1の層、および前記少なくとも1つの他の透明導電性材料層が、物理堆積技法、化学堆積技法、または両方を用いて形成される、請求項15〜19のいずれか1項に記載の方法。
- 前記第1の層が、直流(DC)マグネトロンスパッタリングを用いて形成される、請求項20に記載の方法。
- 前記第1の堆積電力が約10Wの電力である、請求項15〜21のいずれか1項に記載の方法。
- 前記少なくとも1つの他の透明導電性材料層が、高周波(RF)マグネトロンスパッタリングを用いて形成される、請求項20〜22のいずれか1項に記載の方法。
- 前記第2の堆積電力が約100Wの電力である、請求項15〜23のいずれか1項に記載の方法。
- 前記第1の層の堆積中の基板温度が、約60℃以下である、請求項15〜24のいずれか1項に記載の方法。
- 前記少なくとも1つの他の透明導電性材料層の堆積中の基板温度が、約60℃以下である、請求項15〜25のいずれか1項に記載の方法。
- 前記第1の層、および前記少なくとも1つの他の透明導電性材料層がそれぞれ、SnO2、Ga−In−Sn−O(GITO)、Zn−In−Sn−O(ZITO)、Ga−In−O(GIO)、Zn−In−O(ZIO)、In−Sn−O(ITO)、および他の透明導電性材料からなる群から選択される、1種または複数種の材料を含む、請求項15〜26のいずれか1項に記載の方法。
- 前記第1の層、および前記少なくとも1つの他の透明導電性材料層が、同じ透明導電性材料を含む、請求項27に記載の方法。
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