JP2011517856A5 - - Google Patents

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JP2011517856A5
JP2011517856A5 JP2011504199A JP2011504199A JP2011517856A5 JP 2011517856 A5 JP2011517856 A5 JP 2011517856A5 JP 2011504199 A JP2011504199 A JP 2011504199A JP 2011504199 A JP2011504199 A JP 2011504199A JP 2011517856 A5 JP2011517856 A5 JP 2011517856A5
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Japan
Prior art keywords
carbon
switching material
resistance switching
forming
memory element
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JP2011504199A
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JP5564035B2 (ja
JP2011517856A (ja
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Priority claimed from US12/418,855 external-priority patent/US8110476B2/en
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Claims (18)

  1. メモリセルを形成する方法であって、
    基板の上方にステアリング素子を形成するステップと、
    前記ステアリング素子に結合されるメモリ素子を形成するステップと、を含み、
    前記メモリ素子が２つの導電体層間に挟み込まれた炭素系抵抗スイッチング材料を含む金属−絶縁物−金属（ＭＩＭ）スタックを含み、前記炭素系抵抗スイッチング材料が２つの導電体層のうちの一方の上方に配置され、もう一方の導電体層が前記炭素系抵抗スイッチング材料の上方に配置され、前記炭素系抵抗スイッチング材料が１０原子層を超えない厚みを有する方法。
  2. 請求項１記載の方法において、
    前記ステアリング素子が、ｐ−ｎまたはｐ−ｉ−ｎダイオードを含む方法。
  3. 請求項２記載の方法において、
    前記ステアリング素子が、多結晶ダイオードを含む方法。
  4. 請求項１記載の方法において、
    前記メモリ素子が、可逆抵抗スイッチング素子を含む方法。
  5. 請求項４記載の方法において、
    前記炭素系抵抗スイッチング材料が、非晶質炭素を含む方法。
  6. 請求項１記載の方法において、
    前記メモリ素子を形成するステップが、３００℃〜６００℃の処理温度で実施されるプラズマ促進化学蒸着技法を用いて前記炭素系抵抗スイッチング材料を堆積することを含む方法。
  7. 請求項６記載の方法において、
    前記プラズマ促進化学蒸着技法が、３００℃〜４５０℃の処理温度で実施される方法。
  8. メモリセルを形成する方法であって、
    基板の上方にステアリング素子を形成するステップと、
    前記ステアリング素子に結合されるメモリ素子を形成するステップと、を含み、
    前記メモリ素子が２つの導電体層間に挟み込まれた炭素系抵抗スイッチング材料を含む金属−絶縁物−金属（ＭＩＭ）スタックを含み、前記炭素系抵抗スイッチング材料が２つの導電体層のうちの一方の上方に配置され、もう一方の導電体層が前記炭素系抵抗スイッチング材料の上方に配置され、
    前記炭素系抵抗スイッチング材料が、
    前記炭素系抵抗スイッチング材料の１原子層を含む１つの単層の厚みを有する炭素系抵抗スイッチング材料の層を形成するステップと、
    前記炭素系抵抗スイッチング材料の層に熱アニールを受けさせるステップと、を繰り返し実施することによって形成される方法。
  9. 請求項８記載の方法において、
    前記ステアリング素子が、ｐ−ｎまたはｐ−ｉ−ｎダイオードを含む方法。
  10. 請求項９記載の方法において、
    前記ステアリング素子が、多結晶ダイオードを含む方法。
  11. 請求項８記載の方法において、
    前記メモリ素子が、可逆抵抗スイッチング素子を含む方法。
  12. 請求項８記載の方法において、
    前記炭素系抵抗スイッチング材料が、非晶質炭素を含む方法。
  13. 請求項８記載の方法において、
    前記炭素系抵抗スイッチング材料の層を形成するステップが、３００℃〜６００℃の処理温度で実施されるプラズマ促進化学蒸着技法を用いて前記炭素系抵抗スイッチング材料を堆積することを含む方法。
  14. 請求項１３記載の方法において、
    前記プラズマ促進化学蒸着技法が、３００℃〜４５０℃の処理温度で実施される方法。
  15. 請求項８記載の方法において、
    前記熱アニールが、２５０℃〜８５０℃の処理温度で実施される方法。
  16. 請求項８記載の方法において、
    前記熱アニールが、３５０℃〜６５０℃の処理温度で実施される方法。
  17. 請求項８記載の方法において、
    前記熱アニールが、無酸化環境を用いて実施される方法。
  18. メモリセルであって、
    基板の上方のステアリング素子と、
    前記ステアリング素子に結合されるメモリ素子と、を備え、
    前記メモリ素子が２つの導電体層間に挟み込まれた炭素系抵抗スイッチング材料を含む金属−絶縁物−金属（ＭＩＭ）スタックを含み、前記炭素系抵抗スイッチング材料が２つの導電体層のうちの一方の上方に配置され、もう一方の導電体層が前記炭素系抵抗スイッチング材料の上方に配置され、前記炭素系抵抗スイッチング材料が１０原子層を超えない厚みを有するメモリセル。
JP2011504199A 2008-04-11 2009-04-10 炭素系メモリ素子を含むメモリセルおよびその形成方法 Expired - Fee Related JP5564035B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US4439908P 2008-04-11 2008-04-11
US61/044,399 2008-04-11
US12/418,855 2009-04-06
US12/418,855 US8110476B2 (en) 2008-04-11 2009-04-06 Memory cell that includes a carbon-based memory element and methods of forming the same
PCT/US2009/040183 WO2009126871A1 (en) 2008-04-11 2009-04-10 A memory cell that includes a carbon-based memory element and methods of forming the same

Publications (3)

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JP2011517856A JP2011517856A (ja) 2011-06-16
JP2011517856A5 true JP2011517856A5 (ja) 2012-05-17
JP5564035B2 JP5564035B2 (ja) 2014-07-30

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JP2011504199A Expired - Fee Related JP5564035B2 (ja) 2008-04-11 2009-04-10 炭素系メモリ素子を含むメモリセルおよびその形成方法

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US (2) US8110476B2 (ja)
EP (1) EP2263256B1 (ja)
JP (1) JP5564035B2 (ja)
KR (1) KR101597845B1 (ja)
CN (1) CN102067312B (ja)
TW (1) TW201010007A (ja)
WO (1) WO2009126871A1 (ja)

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