JP2011515786A - ダイナミックデータラッチ要求を備えたキャッシュ操作における適合アルゴリズム - Google Patents

ダイナミックデータラッチ要求を備えたキャッシュ操作における適合アルゴリズム Download PDF

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Publication number
JP2011515786A
JP2011515786A JP2011500833A JP2011500833A JP2011515786A JP 2011515786 A JP2011515786 A JP 2011515786A JP 2011500833 A JP2011500833 A JP 2011500833A JP 2011500833 A JP2011500833 A JP 2011500833A JP 2011515786 A JP2011515786 A JP 2011515786A
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Japan
Prior art keywords
data
volatile memory
data latches
latches
read
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JP2011500833A
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English (en)
Japanese (ja)
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JP2011515786A5 (enExample
Inventor
リ，ヤン
パオ−リン コー，アン
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SanDisk Corp
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SanDisk Corp
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Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of JP2011515786A publication Critical patent/JP2011515786A/ja
Publication of JP2011515786A5 publication Critical patent/JP2011515786A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5623—Concurrent multilevel programming and reading
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5643—Multilevel memory comprising cache storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2011500833A 2008-03-19 2009-02-19 ダイナミックデータラッチ要求を備えたキャッシュ操作における適合アルゴリズム Pending JP2011515786A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/051,462 US7961512B2 (en) 2008-03-19 2008-03-19 Adaptive algorithm in cache operation with dynamic data latch requirements
US12/051,462 2008-03-19
PCT/US2009/034573 WO2009117204A1 (en) 2008-03-19 2009-02-19 Adaptive algorithm in cache operation with dynamic data latch requirements

Publications (2)

Publication Number Publication Date
JP2011515786A true JP2011515786A (ja) 2011-05-19
JP2011515786A5 JP2011515786A5 (enExample) 2012-03-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011500833A Pending JP2011515786A (ja) 2008-03-19 2009-02-19 ダイナミックデータラッチ要求を備えたキャッシュ操作における適合アルゴリズム

Country Status (6)

Country Link
US (1) US7961512B2 (enExample)
JP (1) JP2011515786A (enExample)
KR (1) KR20100138943A (enExample)
CN (1) CN102037519A (enExample)
TW (1) TWI382310B (enExample)
WO (1) WO2009117204A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8130544B2 (en) * 2009-08-17 2012-03-06 Skymedi Corporation Method of reducing bit error rate for a flash memory
US8472280B2 (en) 2010-12-21 2013-06-25 Sandisk Technologies Inc. Alternate page by page programming scheme
US8432740B2 (en) 2011-07-21 2013-04-30 Sandisk Technologies Inc. Program algorithm with staircase waveform decomposed into multiple passes
US8750045B2 (en) 2012-07-27 2014-06-10 Sandisk Technologies Inc. Experience count dependent program algorithm for flash memory
US9934872B2 (en) 2014-10-30 2018-04-03 Sandisk Technologies Llc Erase stress and delta erase loop count methods for various fail modes in non-volatile memory
CN105718452A (zh) * 2014-12-01 2016-06-29 金蝶软件（中国）有限公司 数据查询方法和系统
US9224502B1 (en) 2015-01-14 2015-12-29 Sandisk Technologies Inc. Techniques for detection and treating memory hole to local interconnect marginality defects
US9269446B1 (en) 2015-04-08 2016-02-23 Sandisk Technologies Inc. Methods to improve programming of slow cells
US9564219B2 (en) 2015-04-08 2017-02-07 Sandisk Technologies Llc Current based detection and recording of memory hole-interconnect spacing defects
US9996280B2 (en) 2016-03-15 2018-06-12 Sandisk Technologies Llc Data register copying for non-volatile storage array operations
US9666307B1 (en) * 2016-09-14 2017-05-30 Micron Technology, Inc. Apparatuses and methods for flexible fuse transmission
JP2018156698A (ja) 2017-03-15 2018-10-04 東芝メモリ株式会社 メモリシステム
US10620879B2 (en) * 2017-05-17 2020-04-14 Macronix International Co., Ltd. Write-while-read access method for a memory device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001325796A (ja) * 2000-03-08 2001-11-22 Toshiba Corp 不揮発性半導体記憶装置
JP2003196989A (ja) * 2001-12-21 2003-07-11 Fujitsu Ltd 不揮発性半導体記憶装置
WO2007131062A2 (en) * 2006-05-05 2007-11-15 Sandisk Corporation Non-volatile memory with background data latch caching during read operations and methods therefor
JP2009536424A (ja) * 2006-05-05 2009-10-08 サンディスク コーポレイション 読み出し操作中にデータラッチでバックグラウンドキャッシングを行う不揮発性メモリとその方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6138206A (en) * 1997-06-12 2000-10-24 International Business Machines Corporation Data register for multicycle data cache read
KR100454119B1 (ko) * 2001-10-24 2004-10-26 삼성전자주식회사 캐쉬 기능을 갖는 불 휘발성 반도체 메모리 장치 및 그것의 프로그램, 읽기, 그리고 페이지 카피백 방법들
US6871257B2 (en) * 2002-02-22 2005-03-22 Sandisk Corporation Pipelined parallel programming operation in a non-volatile memory system
DE602004010795T2 (de) * 2004-06-24 2008-12-11 Stmicroelectronics S.R.L., Agrate Brianza Verbesserter Seitenspeicher für eine programmierbare Speichervorrichtung
US7242620B2 (en) * 2004-10-05 2007-07-10 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and an operation method thereof
US7463521B2 (en) 2005-04-01 2008-12-09 Sandisk Corporation Method for non-volatile memory with managed execution of cached data
US7206230B2 (en) 2005-04-01 2007-04-17 Sandisk Corporation Use of data latches in cache operations of non-volatile memories
US7336543B2 (en) * 2006-02-21 2008-02-26 Elite Semiconductor Memory Technology Inc. Non-volatile memory device with page buffer having dual registers and methods using the same
JP4896569B2 (ja) * 2006-04-10 2012-03-14 株式会社東芝 半導体集積回路装置及びそのダイナミックラッチのリフレッシュ方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001325796A (ja) * 2000-03-08 2001-11-22 Toshiba Corp 不揮発性半導体記憶装置
JP2003196989A (ja) * 2001-12-21 2003-07-11 Fujitsu Ltd 不揮発性半導体記憶装置
WO2007131062A2 (en) * 2006-05-05 2007-11-15 Sandisk Corporation Non-volatile memory with background data latch caching during read operations and methods therefor
JP2009536424A (ja) * 2006-05-05 2009-10-08 サンディスク コーポレイション 読み出し操作中にデータラッチでバックグラウンドキャッシングを行う不揮発性メモリとその方法

Also Published As

Publication number Publication date
TWI382310B (zh) 2013-01-11
CN102037519A (zh) 2011-04-27
KR20100138943A (ko) 2010-12-31
US20090237998A1 (en) 2009-09-24
WO2009117204A1 (en) 2009-09-24
US7961512B2 (en) 2011-06-14
TW200945032A (en) 2009-11-01

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