JP2011514616A - 高性能メモリコンパイラにおける進歩したビットライントラッキング - Google Patents
高性能メモリコンパイラにおける進歩したビットライントラッキング Download PDFInfo
- Publication number
- JP2011514616A JP2011514616A JP2010550745A JP2010550745A JP2011514616A JP 2011514616 A JP2011514616 A JP 2011514616A JP 2010550745 A JP2010550745 A JP 2010550745A JP 2010550745 A JP2010550745 A JP 2010550745A JP 2011514616 A JP2011514616 A JP 2011514616A
- Authority
- JP
- Japan
- Prior art keywords
- word line
- dummy
- bit line
- real
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 38
- 230000004044 response Effects 0.000 claims abstract description 13
- 238000012544 monitoring process Methods 0.000 claims abstract description 6
- 238000001514 detection method Methods 0.000 claims description 17
- 230000035800 maturation Effects 0.000 claims description 11
- 230000007246 mechanism Effects 0.000 claims description 10
- 230000003111 delayed effect Effects 0.000 claims description 8
- 230000010198 maturation time Effects 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 238000004891 communication Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000000342 Monte Carlo simulation Methods 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Static Random-Access Memory (AREA)
Abstract
Description
Claims (18)
- コンパイラメモリ読み出し動作を制御する方法であって、
リアルビットライン成熟速度と類似の速度でのダミービットラインの成熟に基づいて、所望のパルス幅を発生させる工程と、
前記コンパイラメモリの前記読み出し動作を有効とするように、前記所望のパルス幅でリアルワードラインを制御する工程と、
を具備する方法。 - 前記所望のパルス幅を発生させる工程は、リアルワードラインをアサートする前にダミーワードラインをアサートすること、及び検出マージンが閾値に到達するように、前記ダミービットラインの成熟時に前記ダミーワードラインを無効とすること、を具備する請求項1に記載の方法。
- 前記ダミービットラインは、内部クロック信号の発生に応答して直接成熟し始める請求項1に記載の方法。
- コンパイラメモリのためのセンスイネイブル時間を決定する方法であって、
リアルワードラインを有効とする前にダミーワードラインを有効とする工程と、
前記ダミーワードラインを有効とするのに応答してダミービットラインを成熟させる工程と、前記ダミービットラインはリアルビットラインが成熟する速度と類似の速度で成熟することと、
前記ダミービットラインをモニタすることにより閾電圧差が達成されたことを決定するのに応答して前記ダミーワードラインを無効とする工程と、
前記ダミーワードラインを有効とした後、予め規定された遅延でワードラインを有効とする工程と、
前記ダミーワードラインを無効とするのに応答してセンスイネイブル信号を発生させる工程と、
を具備する方法。 - 前記ダミーワードラインを無効とした後、前記予め規定された遅延で前記ワードラインを無効とする工程を更に具備する請求項4に記載の方法。
- 前記センスイネイブル信号を発生させる工程は、前記ダミーワードラインを無効とした後、前記予め規定された遅延よりも小さい遅延で行われる請求項5に記載の方法。
- 前記予め規定された遅延はプリデコーダゲート遅延に基づく請求項4に記載の方法。
- 前記予め規定された遅延はロウデコーダ及びワードラインドライバゲート遅延に基づく請求項7に記載の方法。
- 前記ワードラインを有効とする工程は、プリデコーダ、ロウデコーダ、及びワードラインドライバから前記内部クロック信号を受取った後に行われる請求項5に記載の方法。
- コンパイラメモリ回路であって、
内部クロック信号を発生させる制御回路と、
前記内部クロック信号を直接受取るダミーワードラインと、
前記内部クロック信号を直接受取るアドレス復号化回路と、
前記ダミーワードラインが前記内部クロック信号を受取った後のある期間、前記アドレス復号化回路から前記内部クロック信号を受取るワードラインと、
を具備する回路。 - 前記アドレス復号化回路はプリデコーダ、ロウデコーダ及びワードラインドライバを具備する請求項10に記載の回路。
- 複数のビットセル及び複数のビットラインを有するメモリアレイを更に具備する請求項10に記載の回路。
- 複数のセンスアンプを更に具備する請求項12に記載の装置。
- 少なくとも1つのプログラム可能なダミープルダウン機構を更に具備する請求項12に記載の回路。
- 前記ダミーワードラインは前記メモリアレイ内に配設される請求項12に記載の回路。
- 前記ダミーワードラインは前記制御回路に配設される請求項10に記載の回路。
- 前記アドレス復号化回路と同じ多数のゲート、同じゲートのタイプ、及び同じファンアウト負荷を有するダミーゲートシステムを更に具備し、前記ダミーゲートシステムはセンスイネイブルパス内に存在し、前記ダミーゲートシステムは、前記ワードラインで受取られる前に前記内部クロック信号が遅延されよりも短い期間だけ前記センスイネイブル信号が遅延されることを確実にする請求項10に記載の回路。
- メモリ読み出し動作を行う方法であって、
リアルビットラインの開始より既知の期間分だけ前にダミービットラインを開始する工程と、前記ダミービットラインは、前記リアルビットラインに関連して予想可能な成熟時間を有することと、
前記ダミービットラインの成熟することに基づいてワードラインを無効とすることを始動する工程と、
を具備する方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/048,676 US7859920B2 (en) | 2008-03-14 | 2008-03-14 | Advanced bit line tracking in high performance memory compilers |
US12/048,676 | 2008-03-14 | ||
PCT/US2009/035369 WO2009114286A1 (en) | 2008-03-14 | 2009-02-27 | Advanced bit line tracking in high performance memory compilers |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011514616A true JP2011514616A (ja) | 2011-05-06 |
JP5461444B2 JP5461444B2 (ja) | 2014-04-02 |
Family
ID=40581473
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010550745A Active JP5461444B2 (ja) | 2008-03-14 | 2009-02-27 | 高性能メモリコンパイラにおける進歩したビットライントラッキング |
Country Status (7)
Country | Link |
---|---|
US (1) | US7859920B2 (ja) |
EP (1) | EP2263234B1 (ja) |
JP (1) | JP5461444B2 (ja) |
KR (1) | KR101182503B1 (ja) |
CN (1) | CN102007540B (ja) |
TW (1) | TW201001437A (ja) |
WO (1) | WO2009114286A1 (ja) |
Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8116139B2 (en) * | 2010-01-29 | 2012-02-14 | Sandisk Technologies Inc. | Bit line stability detection |
US8279693B2 (en) | 2010-04-09 | 2012-10-02 | Qualcomm Incorporated | Programmable tracking circuit for tracking semiconductor memory read current |
US9224496B2 (en) | 2010-08-11 | 2015-12-29 | Shine C. Chung | Circuit and system of aggregated area anti-fuse in CMOS processes |
US9236141B2 (en) | 2010-08-20 | 2016-01-12 | Shine C. Chung | Circuit and system of using junction diode of MOS as program selector for programmable resistive devices |
US9711237B2 (en) | 2010-08-20 | 2017-07-18 | Attopsemi Technology Co., Ltd. | Method and structure for reliable electrical fuse programming |
US9460807B2 (en) | 2010-08-20 | 2016-10-04 | Shine C. Chung | One-time programmable memory devices using FinFET technology |
US9824768B2 (en) | 2015-03-22 | 2017-11-21 | Attopsemi Technology Co., Ltd | Integrated OTP memory for providing MTP memory |
US9818478B2 (en) | 2012-12-07 | 2017-11-14 | Attopsemi Technology Co., Ltd | Programmable resistive device and memory using diode as selector |
US8854859B2 (en) | 2010-08-20 | 2014-10-07 | Shine C. Chung | Programmably reversible resistive device cells using CMOS logic processes |
US10249379B2 (en) | 2010-08-20 | 2019-04-02 | Attopsemi Technology Co., Ltd | One-time programmable devices having program selector for electrical fuses with extended area |
US10229746B2 (en) | 2010-08-20 | 2019-03-12 | Attopsemi Technology Co., Ltd | OTP memory with high data security |
US10923204B2 (en) | 2010-08-20 | 2021-02-16 | Attopsemi Technology Co., Ltd | Fully testible OTP memory |
US9496033B2 (en) | 2010-08-20 | 2016-11-15 | Attopsemi Technology Co., Ltd | Method and system of programmable resistive devices with read capability using a low supply voltage |
US9070437B2 (en) | 2010-08-20 | 2015-06-30 | Shine C. Chung | Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink |
US9251893B2 (en) | 2010-08-20 | 2016-02-02 | Shine C. Chung | Multiple-bit programmable resistive memory using diode as program selector |
US10916317B2 (en) | 2010-08-20 | 2021-02-09 | Attopsemi Technology Co., Ltd | Programmable resistance memory on thin film transistor technology |
US8300491B2 (en) | 2010-08-26 | 2012-10-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple bitcells tracking scheme for semiconductor memories |
US8923085B2 (en) | 2010-11-03 | 2014-12-30 | Shine C. Chung | Low-pin-count non-volatile memory embedded in a integrated circuit without any additional pins for access |
US8988965B2 (en) | 2010-11-03 | 2015-03-24 | Shine C. Chung | Low-pin-count non-volatile memory interface |
US9019791B2 (en) | 2010-11-03 | 2015-04-28 | Shine C. Chung | Low-pin-count non-volatile memory interface for 3D IC |
US9496265B2 (en) | 2010-12-08 | 2016-11-15 | Attopsemi Technology Co., Ltd | Circuit and system of a high density anti-fuse |
JP2012128895A (ja) * | 2010-12-13 | 2012-07-05 | Toshiba Corp | 半導体記憶装置 |
US8976614B2 (en) * | 2011-02-11 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tracking scheme for memory |
US8848423B2 (en) | 2011-02-14 | 2014-09-30 | Shine C. Chung | Circuit and system of using FinFET for building programmable resistive devices |
US10192615B2 (en) | 2011-02-14 | 2019-01-29 | Attopsemi Technology Co., Ltd | One-time programmable devices having a semiconductor fin structure with a divided active region |
US10586832B2 (en) | 2011-02-14 | 2020-03-10 | Attopsemi Technology Co., Ltd | One-time programmable devices using gate-all-around structures |
JP5539916B2 (ja) * | 2011-03-04 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9136261B2 (en) | 2011-11-15 | 2015-09-15 | Shine C. Chung | Structures and techniques for using mesh-structure diodes for electro-static discharge (ESD) protection |
US9007804B2 (en) | 2012-02-06 | 2015-04-14 | Shine C. Chung | Circuit and system of protective mechanisms for programmable resistive memories |
KR101921964B1 (ko) * | 2012-03-05 | 2019-02-13 | 삼성전자주식회사 | 라인 메모리 및 이를 이용한 시모스 이미지 집적회로소자 |
US9064561B2 (en) * | 2012-04-02 | 2015-06-23 | Arm Limited | Handling of write operations within a memory device |
US8923069B2 (en) * | 2012-06-01 | 2014-12-30 | Lsi Corporation | Memory having self-timed edge-detection write tracking |
US8787099B2 (en) | 2012-06-20 | 2014-07-22 | Lsi Corporation | Adjusting access times to memory cells based on characterized word-line delay and gate delay |
US9105328B2 (en) * | 2012-07-31 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tracking signals in memory write or read operation |
US8773927B2 (en) * | 2012-09-07 | 2014-07-08 | Lsi Corporation | Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay |
US9076526B2 (en) | 2012-09-10 | 2015-07-07 | Shine C. Chung | OTP memories functioning as an MTP memory |
US9183897B2 (en) * | 2012-09-30 | 2015-11-10 | Shine C. Chung | Circuits and methods of a self-timed high speed SRAM |
US9324447B2 (en) | 2012-11-20 | 2016-04-26 | Shine C. Chung | Circuit and system for concurrently programming multiple bits of OTP memory devices |
JP2015008029A (ja) * | 2013-06-26 | 2015-01-15 | マイクロン テクノロジー, インク. | 半導体装置 |
US9111589B2 (en) | 2013-09-04 | 2015-08-18 | Qualcomm Incorporated | Memory timing circuit |
US9564193B2 (en) | 2013-09-27 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit to generate a sense amplifier enable signal |
CN103871461B (zh) * | 2014-03-31 | 2016-09-14 | 西安紫光国芯半导体有限公司 | 一种适用于静态随机存储器的写复制电路 |
US9412473B2 (en) | 2014-06-16 | 2016-08-09 | Shine C. Chung | System and method of a novel redundancy scheme for OTP |
US9640246B2 (en) * | 2014-09-22 | 2017-05-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory tracking scheme |
TWM507610U (zh) * | 2015-01-13 | 2015-08-21 | Switchlab Inc | 電聯接端子之扳動件固定結構 |
US9934833B2 (en) | 2015-03-24 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory circuit having tracking circuit including series-connected transistors |
US9418716B1 (en) * | 2015-04-15 | 2016-08-16 | Qualcomm Incorporated | Word line and bit line tracking across diverse power domains |
US9865316B2 (en) * | 2016-01-21 | 2018-01-09 | Qualcomm Incorporated | Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power |
US9978442B2 (en) * | 2016-09-07 | 2018-05-22 | Qualcomm Incorporated | Lower power high speed decoding based dynamic tracking for memories |
US11615859B2 (en) | 2017-04-14 | 2023-03-28 | Attopsemi Technology Co., Ltd | One-time programmable memories with ultra-low power read operation and novel sensing scheme |
US10535413B2 (en) | 2017-04-14 | 2020-01-14 | Attopsemi Technology Co., Ltd | Low power read operation for programmable resistive memories |
US10726914B2 (en) | 2017-04-14 | 2020-07-28 | Attopsemi Technology Co. Ltd | Programmable resistive memories with low power read operation and novel sensing scheme |
US11062786B2 (en) | 2017-04-14 | 2021-07-13 | Attopsemi Technology Co., Ltd | One-time programmable memories with low power read operation and novel sensing scheme |
US10269416B1 (en) * | 2017-10-20 | 2019-04-23 | Arm Limited | Dummy wordline tracking circuitry |
US10770160B2 (en) | 2017-11-30 | 2020-09-08 | Attopsemi Technology Co., Ltd | Programmable resistive memory formed by bit slices from a standard cell library |
US10497414B1 (en) * | 2018-06-08 | 2019-12-03 | Arm Limited | Circuitry for tracking bias voltage behavior |
US10580479B2 (en) * | 2018-06-26 | 2020-03-03 | Mediatek Singapore Pte. Ltd. | Self-time scheme for optimizing performance and power in dual rail power supplies memories |
US11211140B1 (en) * | 2019-09-24 | 2021-12-28 | Facebook Technologies, Llc | Device authentication based on inconsistent responses |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000516008A (ja) * | 1995-12-28 | 2000-11-28 | エルエスアイ ロジック コーポレーション | 低電力セルフタイミングメモリ装置およびその制御方法ならびに装置 |
JP2004164772A (ja) * | 2002-11-14 | 2004-06-10 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
JP2004199759A (ja) * | 2002-12-17 | 2004-07-15 | Fujitsu Ltd | 半導体記憶装置 |
JP2007018584A (ja) * | 2005-07-06 | 2007-01-25 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
JP2007250020A (ja) * | 2006-03-13 | 2007-09-27 | Toshiba Corp | 半導体記憶装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5724294A (en) | 1996-12-30 | 1998-03-03 | Intel Corporation | Self-tracking sense amplifier strobing circuit and method |
IT1301879B1 (it) | 1998-07-30 | 2000-07-07 | St Microelectronics Srl | Circuiteria a generatore di impulsi per temporizzare un dispositivodi memoria a basso consumo |
US6963515B2 (en) | 2003-05-08 | 2005-11-08 | Lsi Logic Corporation | Method and device for a scalable memory building block |
US7016245B2 (en) | 2004-02-02 | 2006-03-21 | Texas Instruments Incorporated | Tracking circuit enabling quick/accurate retrieval of data stored in a memory array |
US7142466B1 (en) | 2005-10-14 | 2006-11-28 | Texas Instruments Incorporated | Determining optimal time instances to sense the output of a memory array which can generate data outputs with variable delay |
US7646658B2 (en) * | 2007-05-31 | 2010-01-12 | Qualcomm Incorporated | Memory device with delay tracking for improved timing margin |
-
2008
- 2008-03-14 US US12/048,676 patent/US7859920B2/en active Active
-
2009
- 2009-02-27 JP JP2010550745A patent/JP5461444B2/ja active Active
- 2009-02-27 KR KR1020107022984A patent/KR101182503B1/ko active IP Right Grant
- 2009-02-27 EP EP09718832.0A patent/EP2263234B1/en active Active
- 2009-02-27 WO PCT/US2009/035369 patent/WO2009114286A1/en active Application Filing
- 2009-02-27 CN CN200980112998.1A patent/CN102007540B/zh active Active
- 2009-03-13 TW TW098108317A patent/TW201001437A/zh unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000516008A (ja) * | 1995-12-28 | 2000-11-28 | エルエスアイ ロジック コーポレーション | 低電力セルフタイミングメモリ装置およびその制御方法ならびに装置 |
JP2004164772A (ja) * | 2002-11-14 | 2004-06-10 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
JP2004199759A (ja) * | 2002-12-17 | 2004-07-15 | Fujitsu Ltd | 半導体記憶装置 |
JP2007018584A (ja) * | 2005-07-06 | 2007-01-25 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
JP2007250020A (ja) * | 2006-03-13 | 2007-09-27 | Toshiba Corp | 半導体記憶装置 |
Also Published As
Publication number | Publication date |
---|---|
CN102007540A (zh) | 2011-04-06 |
EP2263234B1 (en) | 2014-04-30 |
US20090231934A1 (en) | 2009-09-17 |
KR101182503B1 (ko) | 2012-09-13 |
KR20100127276A (ko) | 2010-12-03 |
US7859920B2 (en) | 2010-12-28 |
CN102007540B (zh) | 2014-08-06 |
TW201001437A (en) | 2010-01-01 |
JP5461444B2 (ja) | 2014-04-02 |
WO2009114286A1 (en) | 2009-09-17 |
EP2263234A1 (en) | 2010-12-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5461444B2 (ja) | 高性能メモリコンパイラにおける進歩したビットライントラッキング | |
CN110648700B (zh) | 自时序电路和相应的自时序方法 | |
CN109416919B (zh) | 重叠的预充电和数据写入 | |
US7499347B2 (en) | Self-timing circuit with programmable delay and programmable accelerator circuits | |
US6597629B1 (en) | Built-in precision shutdown apparatus for effectuating self-referenced access timing scheme | |
US20080298143A1 (en) | Memory device with delay tracking for improved timing margin | |
US8730750B1 (en) | Memory device with control circuitry for generating a reset signal in read and write modes of operation | |
US9928889B1 (en) | Bitline precharge control and tracking scheme providing increased memory cycle speed for pseudo-dual-port memories | |
JP2004145955A (ja) | 半導体記憶装置及びその制御方法 | |
US6876595B2 (en) | Decode path gated low active power SRAM | |
US9858217B1 (en) | Within-die special oscillator for tracking SRAM memory performance with global process variation, voltage and temperature | |
US10916275B1 (en) | Write driver and pre-charge circuitry for high performance pseudo-dual port (PDP) memories | |
US7054223B2 (en) | Semiconductor memory device | |
US7170805B2 (en) | Memory devices having bit line precharge circuits with off current precharge control and associated bit line precharge methods | |
US7339842B1 (en) | Timing control for sense amplifiers in a memory circuit | |
JP5071664B2 (ja) | 少なくとも1つのランダムアクセスメモリアレイを含む集積回路装置 | |
US20180151219A1 (en) | Memory device with determined time window | |
US5715201A (en) | Self-tracking delay-matching write pulse control circuit and method | |
Harel et al. | Replica bit-line technique for internal refresh in logic-compatible gain-cell embedded DRAM | |
KR20240026485A (ko) | 기록 듀얼 레일 sram 기록 최적화 전 약한 프리차지 | |
JP2001297592A (ja) | 不揮発性メモリ装置及び不揮発性メモリの駆動方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120910 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120925 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20121225 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130107 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130125 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130201 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130218 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130225 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130325 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130625 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130925 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20131002 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20131025 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20131101 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131122 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131217 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140115 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5461444 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |