JP2011508433A - 自然酸化物の成長を低減するためのプラズマクリーンプロセスによるパッシベーション層の形成 - Google Patents

自然酸化物の成長を低減するためのプラズマクリーンプロセスによるパッシベーション層の形成 Download PDF

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JP2011508433A
JP2011508433A JP2010539803A JP2010539803A JP2011508433A JP 2011508433 A JP2011508433 A JP 2011508433A JP 2010539803 A JP2010539803 A JP 2010539803A JP 2010539803 A JP2010539803 A JP 2010539803A JP 2011508433 A JP2011508433 A JP 2011508433A
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substrate
range
temperature
process chamber
plasma
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JP2011508433A5 (enExample
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ハイチュン ヤング
シン リアング ル
チェン テヒ カオ
メイ チャング
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Applied Materials Inc
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Applied Materials Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2010539803A 2007-12-21 2008-12-18 自然酸化物の成長を低減するためのプラズマクリーンプロセスによるパッシベーション層の形成 Pending JP2011508433A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/962,791 US7780793B2 (en) 2004-02-26 2007-12-21 Passivation layer formation by plasma clean process to reduce native oxide growth
PCT/US2008/087436 WO2009085958A2 (en) 2007-12-21 2008-12-18 Passivation layer formation by plasma clean process to reduce native oxide growth

Publications (2)

Publication Number Publication Date
JP2011508433A true JP2011508433A (ja) 2011-03-10
JP2011508433A5 JP2011508433A5 (enExample) 2013-04-11

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JP2010539803A Pending JP2011508433A (ja) 2007-12-21 2008-12-18 自然酸化物の成長を低減するためのプラズマクリーンプロセスによるパッシベーション層の形成

Country Status (6)

Country Link
US (1) US7780793B2 (enExample)
JP (1) JP2011508433A (enExample)
KR (1) KR20100114503A (enExample)
CN (1) CN101903984B (enExample)
TW (1) TWI438839B (enExample)
WO (1) WO2009085958A2 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015216208A (ja) * 2014-05-09 2015-12-03 東京エレクトロン株式会社 エッチング方法
WO2019235196A1 (ja) * 2018-06-08 2019-12-12 株式会社アルバック 酸化膜除去方法、および、酸化膜除去装置
JP2020522138A (ja) * 2017-05-26 2020-07-27 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 金属シリサイドの選択的堆積
JP2022506677A (ja) * 2018-11-13 2022-01-17 アプライド マテリアルズ インコーポレイテッド 金属シリサイドの選択的堆積及び酸化物の選択的除去

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WO2007092130A2 (en) * 2006-02-03 2007-08-16 Applied Materials, Inc. Dry etch and epitaxial deposition process and apparatus

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JP2015216208A (ja) * 2014-05-09 2015-12-03 東京エレクトロン株式会社 エッチング方法
JP2020522138A (ja) * 2017-05-26 2020-07-27 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 金属シリサイドの選択的堆積
WO2019235196A1 (ja) * 2018-06-08 2019-12-12 株式会社アルバック 酸化膜除去方法、および、酸化膜除去装置
JPWO2019235196A1 (ja) * 2018-06-08 2021-06-17 株式会社アルバック 酸化膜除去方法、および、酸化膜除去装置
JP2022506677A (ja) * 2018-11-13 2022-01-17 アプライド マテリアルズ インコーポレイテッド 金属シリサイドの選択的堆積及び酸化物の選択的除去
JP7503547B2 (ja) 2018-11-13 2024-06-20 アプライド マテリアルズ インコーポレイテッド 金属シリサイドの選択的堆積及び酸化物の選択的除去

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TW200935513A (en) 2009-08-16
TWI438839B (zh) 2014-05-21
KR20100114503A (ko) 2010-10-25
US7780793B2 (en) 2010-08-24
WO2009085958A2 (en) 2009-07-09
WO2009085958A3 (en) 2009-09-03
CN101903984A (zh) 2010-12-01
US20080160210A1 (en) 2008-07-03

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