JP2011505647A - ロックインジケータを有するマルチスレッドプロセッサ - Google Patents

ロックインジケータを有するマルチスレッドプロセッサ Download PDF

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Publication number
JP2011505647A
JP2011505647A JP2010537031A JP2010537031A JP2011505647A JP 2011505647 A JP2011505647 A JP 2011505647A JP 2010537031 A JP2010537031 A JP 2010537031A JP 2010537031 A JP2010537031 A JP 2010537031A JP 2011505647 A JP2011505647 A JP 2011505647A
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Japan
Prior art keywords
tlb
thread
lock
processor
control logic
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Pending
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JP2010537031A
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Japanese (ja)
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JP2011505647A5 (enExample
Inventor
コドレスキュ、ルシアン
プロンドケ、エリッチ・ジェイ．
ベンクマハンティ、スレッシュ・ケー
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Qualcomm Inc
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Qualcomm Inc
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Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2011505647A publication Critical patent/JP2011505647A/ja
Publication of JP2011505647A5 publication Critical patent/JP2011505647A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083—Power or thermal control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/52—Indexing scheme relating to G06F9/52
    • G06F2209/522—Manager
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2010537031A 2007-12-03 2008-12-03 ロックインジケータを有するマルチスレッドプロセッサ Pending JP2011505647A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/949,284 US8140823B2 (en) 2007-12-03 2007-12-03 Multithreaded processor with lock indicator
PCT/US2008/085402 WO2009073722A1 (en) 2007-12-03 2008-12-03 Multithreaded processor with lock indicator

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013034561A Division JP2013145568A (ja) 2007-12-03 2013-02-25 ロックインジケータを有するマルチスレッドプロセッサ

Publications (2)

Publication Number Publication Date
JP2011505647A true JP2011505647A (ja) 2011-02-24
JP2011505647A5 JP2011505647A5 (enExample) 2012-10-18

Family

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Family Applications (3)

Application Number Title Priority Date Filing Date
JP2010537031A Pending JP2011505647A (ja) 2007-12-03 2008-12-03 ロックインジケータを有するマルチスレッドプロセッサ
JP2013034561A Pending JP2013145568A (ja) 2007-12-03 2013-02-25 ロックインジケータを有するマルチスレッドプロセッサ
JP2014116111A Pending JP2014197408A (ja) 2007-12-03 2014-06-04 ロックインジケータを有するマルチスレッドプロセッサ

Family Applications After (2)

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JP2013034561A Pending JP2013145568A (ja) 2007-12-03 2013-02-25 ロックインジケータを有するマルチスレッドプロセッサ
JP2014116111A Pending JP2014197408A (ja) 2007-12-03 2014-06-04 ロックインジケータを有するマルチスレッドプロセッサ

Country Status (6)

Country Link
US (1) US8140823B2 (enExample)
EP (1) EP2232370B1 (enExample)
JP (3) JP2011505647A (enExample)
KR (1) KR101146359B1 (enExample)
CN (1) CN101884029B (enExample)
WO (1) WO2009073722A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
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JP2017530455A (ja) * 2014-09-08 2017-10-12 エイアールエム リミテッド 複数のスレッドを実行するデータ処理装置における共有リソース
JP2019525376A (ja) * 2016-08-17 2019-09-05 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドＡｄｖａｎｃｅｄ Ｍｉｃｒｏ Ｄｅｖｉｃｅｓ Ｉｎｃｏｒｐｏｒａｔｅｄ マルチスレッドモードにおける電力低減のための方法及び装置

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US8452947B2 (en) 2008-02-01 2013-05-28 International Business Machines Corporation Hardware wake-and-go mechanism and content addressable memory with instruction pre-fetch look-ahead to detect programming idioms
US8250396B2 (en) * 2008-02-01 2012-08-21 International Business Machines Corporation Hardware wake-and-go mechanism for a data processing system
US8145849B2 (en) * 2008-02-01 2012-03-27 International Business Machines Corporation Wake-and-go mechanism with system bus response
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US8612977B2 (en) 2008-02-01 2013-12-17 International Business Machines Corporation Wake-and-go mechanism with software save of thread state
US8171476B2 (en) 2008-02-01 2012-05-01 International Business Machines Corporation Wake-and-go mechanism with prioritization of threads
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CN103377086A (zh) * 2012-04-27 2013-10-30 华为技术有限公司 用于异步多核系统操作共享资源的方法、装置及系统
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US9501332B2 (en) * 2012-12-20 2016-11-22 Qualcomm Incorporated System and method to reset a lock indication
US10007323B2 (en) 2012-12-26 2018-06-26 Intel Corporation Platform power consumption reduction via power state switching
US9361116B2 (en) 2012-12-28 2016-06-07 Intel Corporation Apparatus and method for low-latency invocation of accelerators
US10140129B2 (en) 2012-12-28 2018-11-27 Intel Corporation Processing core having shared front end unit
US20140189333A1 (en) * 2012-12-28 2014-07-03 Oren Ben-Kiki Apparatus and method for task-switchable synchronous hardware accelerators
US9417873B2 (en) 2012-12-28 2016-08-16 Intel Corporation Apparatus and method for a hybrid latency-throughput processor
US10346195B2 (en) 2012-12-29 2019-07-09 Intel Corporation Apparatus and method for invocation of a multi threaded accelerator
US10114752B2 (en) * 2014-06-27 2018-10-30 International Business Machines Corporation Detecting cache conflicts by utilizing logical address comparisons in a transactional memory
US9665376B2 (en) * 2014-12-15 2017-05-30 International Business Machines Corporation Sharing program interrupt logic in a multithreaded processor
KR101638136B1 (ko) * 2015-05-14 2016-07-08 주식회사 티맥스 소프트 멀티 스레드 구조에서 작업 분배 시 스레드 간 락 경쟁을 최소화하는 방법 및 이를 사용한 장치
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Also Published As

Publication number Publication date
CN101884029A (zh) 2010-11-10
JP2013145568A (ja) 2013-07-25
CN101884029B (zh) 2014-09-03
KR20100101629A (ko) 2010-09-17
KR101146359B1 (ko) 2012-05-17
WO2009073722A1 (en) 2009-06-11
EP2232370A1 (en) 2010-09-29
JP2014197408A (ja) 2014-10-16
US8140823B2 (en) 2012-03-20
EP2232370B1 (en) 2015-11-04
US20090144519A1 (en) 2009-06-04

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