Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
  • G06F9/526—Mutual exclusion algorithms
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
  • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/10—Address translation
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/10—Address translation
  • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30003—Arrangements for executing specific machine instructions
  • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
  • G06F9/30083—Power or thermal control instructions
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30098—Register arrangements
  • G06F9/30101—Special purpose registers
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2209/00—Indexing scheme relating to G06F9/00
  • G06F2209/52—Indexing scheme relating to G06F9/52
  • G06F2209/522—Manager
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• multithreaded processors that can process multiple threads concurrently at an electronic device.
• multithreaded processors typically are designed so that some processing resources, such as caches, buses, or other resources, are shared by multiple threads.
• processing resources such as caches, buses, or other resources
• certain operations may only be reliably performed at a shared resource by a single thread. For example, unpredictable results can arise when a memory address is written to by two different threads concurrently.
• Software locks can be used to manage shared resources by providing a value in memory, such as a semaphore, that indicates whether the shared resource is unlocked and available for use by a particular process, or locked and unavailable for use.
• Software locks are typically set and released by software instructions and may be unreliable, such as when the software lock is accessed by poorly written or malicious software.
• a processor typically repeatedly executes instructions to check a value of the lock before continuing with program execution.
• each operation using the software lock introduces a processing delay due to accessing, comparing, and/or writing a value to the portion of memory storing the software lock.
• a system in a particular embodiment, includes a translation lookaside buffer (TLB) shared by multiple processing threads of a multithreaded processor.
• the system includes a TLB lock bit in a register of the multithreaded processor.
• the system also includes a control logic circuit configured to put a particular thread of the multiple processing threads to sleep in response to the TLB lock bit having a locked configuration when a TLB miss event associated with the particular thread is detected.
• a system in another particular embodiment, includes means for indicating a lock status of a shared resource in a multithreaded processor.
• the system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource.
• the system further includes means for unlocking the shared resource.
• a computer readable medium having processor executable instructions having processor executable instructions.
• the processor executable instructions cause a processor to handle an exception associated with a resource that is shared by multiple threads of a multi-threaded processor.
• the processor executable instructions also cause a processor to unlock a hardware lock for the resource after the exception has been handled.
• FIG. 1 is a block diagram of an embodiment of a system that includes a multithreaded processor with a lock indicator
• the TLB lock indicator 110 may include one or more bits of a global status register of the multithreaded processor core 102.
• the TLB lock indicator 110 may be responsive to control signals from the control logic circuit 106.
• the TLB lock indicator 110 has a locked configuration to indicate that at least one thread 112 or 114 is performing a write operation at the TLB 108 and that access to the TLB by other threads is restricted.
• TLB lock indicator 110 has an unlocked configuration, enabling normal access to the TLB 108 by the threads 112 and 114.
• the exception handler 122 may be operable to fetch and execute instructions that enable recovery from the TLB miss event. For example, the exception handler 122 may process instructions causing the requested virtual address that triggered the TLB miss event to be located at a non-core memory resource, such as a page table. The exception handler 122 may write or program a translation of the virtual address into the TLB 108. The exception handler 122 may also be configured to execute a return instruction to exit an exception handling mode. The return instruction may be operable to return the thread 112 to a non- exception state and may request the control logic circuit 106 to unlock the TLB lock indicator 110. Alternatively, the return instruction may unlock the TLB lock indicator 110 upon return from the exception state without sending an unlock request to the control logic circuit 106.
• the control logic circuit 106 may lock the TLB 108 using the TLB lock indicator 110 to exclude other threads from modifying data at the TLB 108 while exception handling instructions respond to the TLB miss event.
• the TLB lock indicator 110 may include one or more bits in a global control register that may be set by the control logic circuit 106 to indicate that the TLB 108 is locked from access by the other threads.
• the control logic circuit 106 is configured to set the TLB lock indicator 110 via a built-in hardware process and not by executing instructions of a software process, enabling a faster response to the TLB miss event, improved processor performance, and reduced vulnerability to malicious or poorly- behaved software applications. Additional performance benefits are enabled by using a global register bit in the multithreaded processor core 102 as the TLB lock indicator 110.
• the control logic circuit 106 may be configured to directly set, clear, and determine a status of the TLB lock indicator 110, so that a response to a TLB miss event may be significantly faster than storing or retrieving a lock indicator value such as a semaphore at the non-processor core memory 104.
• control logic circuit 106 may instruct the thread 112 or 114 that generated the TLB miss event to launch the exception handler 122 or 132 to respond to the TLB miss event.
• the control logic circuit 106 may unlock the TLB lock indicator 110.
• the second thread 114 may also request a virtual address translation that results in a TLB miss event.
• the control logic circuit 106 may determine that the TLB lock indicator 110 is in a locked configuration, and may instruct the second thread 114 to go to sleep. For example, the control logic circuit 106 may instruct the second thread 114 to save a current state, to record an address of a last executed packet that caused the TLB miss event, and to enter a wait state during which the second thread 114 does not process instructions. Additional threads may encounter TLB miss events while the TLB lock indicator 110 remains locked and may also be put to sleep by the control logic circuit 106.
• the control logic circuit 106 When the control logic circuit 106 is informed that the TLB miss event associated with the first thread 112 has been handled, such as via a return instruction executed by the exception handler 122, the control logic circuit 106 unlocks the TLB lock indicator 110 and determines whether one or more processing threads are asleep due to the TLB 108 being locked. If so, the control logic circuit 106 awakens one or more of the sleeping threads, such as the second thread 114, to resume processing.
• the second thread 114 may be awakened and may replay the instruction packet that was executed immediately prior to the second thread 114 being put to sleep and that resulted in the TLB miss event.
• the replayed instruction packet may repeat a request for translation of a virtual address at the TLB 108.
• the virtual address translation requested by the second thread may potentially be stored in the TLB 108. If not, a second TLB miss event occurs, and in response the control logic circuit 106 resets the TLB lock indicator 110 to the locked configuration and instructs the exception handler 132 of the second thread 114 to begin processing instructions to handle the second TLB miss event.
• FIG. 2 a particular illustrative embodiment of a processing system that includes a hardware lock for a shared resource is depicted and generally designated 200.
• the processing system 200 includes a memory 202 that is coupled to an instruction cache 210 via a bus interface 208.
• the processing system 200 also includes a data cache 212 that is coupled to the memory 202 via the bus interface 208.
• the instruction cache 210 is coupled to a sequencer 214 via a bus 211.
• the sequencer 214 can also receive general interrupts 216, which may be retrieved from an interrupt register (not shown).
• the instruction cache 210 is coupled to the sequencer 214 via a plurality of current instruction registers, which may be coupled to the bus 211 and associated with particular threads of the processing system 200.
• the processing system 200 is an interleaved multi-threaded processor including six threads.
• the bus 211 is a sixty-four (64)-bit bus and the sequencer 214 is configured to retrieve instructions from the memory 202 via instruction packets that include multiple instructions having a length of thirty-two (32) bits each.
• the bus 211 is coupled to a first instruction execution unit 218, a second instruction execution unit 220, a third instruction execution unit 222, and a fourth instruction execution unit 224.
• Each instruction execution unit 218, 220, 222, 224 can be coupled to a general register file 226 via a second bus 228.
• the general register file 226 can also be coupled to the sequencer 214 and to the data cache 212 via a third bus 230.
• the sequencer 214 includes or is otherwise coupled to a control logic circuit 270 that has access to thread-specific supervisor control registers 232 and to global control registers 234.
• the control logic circuit 270 is further coupled to a translation lookaside buffer (TLB) 272.
• TLB 272 is accessible to one or more of the execution units 218, 220, 222, and 224 to provide virtual-to-physical address translations and to signal a TLB miss event to the control logic circuit 270 when a requested address is not stored at the TLB 272.
• each thread-specific supervisor control register 232 includes multiple bit fields, such as a sleep field 280, an exception field 282, and a resume address field 284.
• the sleep field 280 may store one or more values or bit settings that indicate whether the associated thread is to transition between an active state and a sleep state.
• the exception field 282 may store one or more values to indicate a general exception or a particular type of exception, such as a TLB miss exception.
• the resume address field 284 may store an address or pointer to locate an instruction or execution packet to resume execution when the thread awakens. For example, when a thread is put to sleep in response to a TLB miss event that occurs while the TLB 272 is locked, the thread may store the address of the instruction that caused the TLB miss event to the resume address field 284. In a particular embodiment, when a value of the sleep field 280 transitions from a sleep indicator to an awake indicator, the associated thread may reload the instruction or execution packet indicated by the value stored at the resume address field 284 and begin execution.
• the control logic circuit 270 may further be configured to receive an instruction or signal from the exception handler when the TLB miss event has been handled, such as when the virtual address translation which caused the TLB miss event has been programmed to the TLB 272. In response, the control logic circuit 270 may be configured to unlock the TLB lock 292, and to check the thread wake FIFO 290 to determine whether one or more threads should be awakened. If so, the control logic circuit 270 is configured to awaken one or more of the threads, in order of storage at the thread wake FIFO 290, in an order of processing at the processing system 200, or in an order determined via one or more algorithms, such as based on a thread priority, by other mechanisms, or any combination thereof.
• the control logic circuit 270 may be configured to respond to a TLB miss event that occurs while the TLB lock 292 has a locked status, such as during exception handling by another thread that includes modifying at least one entry at the TLB 272.
• the control logic circuit 270 may be configured to write to the thread-specific supervisor control registers 232 to instruct the thread associated with the recent TLB miss event to store an address of a recent instruction or execution packet to the resume address field 284 and to go to sleep without initiating an exception handler associated with the recent TLB miss event.
• the control logic 270 may also be configured to not increment a program counter associated with the current thread when the current thread is put to sleep.
• the control logic circuit 270 may further be configured to store an identifier of the current thread at the thread wake FIFO 290.
• a TLB miss event associated with a thread of a multi-threaded processor is received.
• the TLB miss event occurs at a software managed TLB.
• a TLB lock indicator is checked.
• the TLB lock indicator may include one or more register bits of a global control register, such as the TLB lock 292 of FIG. 2. Proceeding to 306, a determination is made whether the TLB lock indicator is locked or unlocked.
• the TLB lock indicator is set to unlocked. Concurrently with unlocking the TLB lock indicator, processing returns from the exception handler, at 328. In a particular embodiment, the TLB lock indicator is automatically unlocked upon returning from the exception handler.
• TLB access is reserved for thread 0, and thread 0 encounters a TLB miss event 402.
• a signal 403 is sent to the control unit.
• the control unit processes a check lock operation 404.
• the check lock operation 404 determines whether the TLB lock indicator is in a locked or unlocked configuration. In the illustrative embodiment of FIG. 4, the check lock operation 404 determines that the TLB lock indicator is in an unlocked state 406.
• FIG. 5 also shows a display controller 526 that is coupled to the digital signal processor 510 and to a display 528. Moreover, an input device 530 is coupled to the digital signal processor 510. Additionally, a memory 532 is coupled to the digital signal processor 510. A coder/decoder (CODEC) 534 can also be coupled to the digital signal processor 510. A speaker 536 and a microphone 538 can be coupled to the CODEC 534.
• CODEC coder/decoder
• FIG. 5 also indicates that a wireless controller 540 can be coupled to the digital signal processor 510 and to a wireless antenna 542.
• a power supply 544 is coupled to the on-chip system 522.
• the display 528, the input device 530, the speaker 536, the microphone 538, the wireless antenna 542, and the power supply 544 are external to the on-chip system 522. However, each is coupled to a component of the on- chip system 522.
• control logic circuit 566 need not be limited to controlling requests to access the TLB 564 in conjunction with the TLB lock indicator 568. Instead, the control logic circuit 566 may be operable to control access to one or more other shared resources, such as the display controller 526, the CODEC 534, the wireless controller 540, any other component of the DSP 510 or coupled to the DSP 510, or any combination thereof.
• a software module may reside in RAM memory, flash memory, ROM memory, PROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
• An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
• the storage medium may be integral to the processor.
• the processor and the storage medium may reside in an ASIC.
• the ASIC may reside in a computing device or a user terminal.
• the processor and the storage medium may reside as discrete components in a computing device or user terminal.

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• Memory System Of A Hierarchy Structure (AREA)

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• 2007
  • 2007-12-03 US US11/949,284 patent/US8140823B2/en active Active
• 2008
  • 2008-12-03 KR KR1020107014736A patent/KR101146359B1/ko not_active Expired - Fee Related
  • 2008-12-03 CN CN200880119089.6A patent/CN101884029B/zh active Active
  • 2008-12-03 WO PCT/US2008/085402 patent/WO2009073722A1/en not_active Ceased
  • 2008-12-03 EP EP08856823.3A patent/EP2232370B1/en active Active
  • 2008-12-03 JP JP2010537031A patent/JP2011505647A/ja active Pending
• 2013
  • 2013-02-25 JP JP2013034561A patent/JP2013145568A/ja active Pending
• 2014
  • 2014-06-04 JP JP2014116111A patent/JP2014197408A/ja active Pending

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