JP2011217257A - Semiconductor integrated circuit, and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, capable of switching an operating mode of a functional module to another operating mode while the functional module is reset, and to provide an image forming apparatus.SOLUTION: The semiconductor integrated circuit includes: a functional module 25 which is reset when a system reset signal is asserted; a signal retainer 20 which is connected to a controller 10 for output to the functional module 25 a switching request signal requesting to accept setting of other operating mode other than an operating mode being set to the functional module 25, and retains the switching request signal when the switching request signal is received; a signal output unit 21 for receiving the switching request signal retained in the signal retainer 20 and for output of the switching request signal to the functional module 25; and a signal output controller 23 for transferring the switching request signal retained in the signal holder 20 to the signal output unit 21 when the system reset signal is asserted, and outputs the switching request signal toward the functional module 25.

Description

  The present invention relates to a semiconductor integrated circuit and an image forming apparatus.

  Conventionally, there are functional modules having a plurality of different operation modes. This type of functional module has various modes such as a test mode for performing an operation test of the functional module and a normal operation mode for performing an original operation of the functional module. This type of functional module executes the set operation mode when any one of the operation modes is set.

  For this type of functional module, for example, the operation mode is set as follows. In the technique described in Patent Document 1, an input is input during normal operation of a circuit while the reset signal is asserted so that the operation mode of the circuit is set after assertion of the reset signal input to the circuit is completed. The voltage level of the terminal used as the terminal is pulled up or pulled down.

  The voltage level of the pulled up or pulled down terminal is latched in the circuit after the assertion of the reset signal is completed, and is used as an operation mode signal for setting the operation mode. Thus, the operation mode is set after the assertion of the reset signal is completed.

  Further, in the technique described in Patent Document 2, when a system reset is input to the circuit and the current setting is reset, the circuit reads out and reads out the operation mode data stored in the nonvolatile memory. The operation mode before the system reset is input is reset by data.

Japanese Patent Laid-Open No. 10-256488 Japanese Patent Laid-Open No. 9-148843

  By the way, in the technique described in Patent Document 1, the operation mode of the circuit is set after the assertion of the reset signal input to the circuit is completed, and the operation mode of the circuit is set while the reset signal is asserted. It is not configured to be.

  In the technique described in Patent Document 1 described above, since the operation mode is set by pulling up or pulling down the voltage level of the terminal, a resistor for pulling up or pulling down the voltage level of the terminal, etc. A dedicated component for setting the operation mode is required.

  Furthermore, in the technique described in Patent Document 2, after the system reset is input to the circuit and the current setting is reset, the operation mode stored in the nonvolatile memory is reset, and the system to the circuit is reset. • It is not configured to set the operation mode of the circuit during reset input.

  Therefore, for example, when switching an operation mode set in a functional module that requires switching of the operation mode during reset, such as a CPU, to another operation mode, the techniques described in Patent Documents 1 and 2 are used. It cannot be applied.

  Also, as in Patent Document 1, when setting the operation mode by controlling the voltage level of the terminal, a dedicated component for controlling the voltage level of the terminal is required. For this reason, it is desired to reduce the number of parts without requiring dedicated components.

  The present invention is proposed in order to solve the above-described problem. When a functional module is being reset, the operation mode of the functional module can be switched to another operation mode without controlling the terminal of the functional module. An object of the present invention is to provide a semiconductor integrated circuit and an image forming apparatus.

  A semiconductor integrated circuit according to one aspect of the present invention includes a functional module that is reset when a system reset signal is asserted, in which one of a plurality of different operation modes is set, and the functional module A switching request signal for requesting to accept a setting of an operation mode other than the operation mode set for the functional module among the operation modes when the system reset signal is not asserted. A signal holding unit that holds the switching request signal when the switching request signal is received from the control unit, and receives the switching request signal held in the signal holding unit, to the functional module When the system reset signal is asserted, and the signal output unit to output to the signal holding unit A signal output control unit for transmitting the held switching request signal to the signal output unit and outputting the signal to the functional module, wherein the functional module is asserted by the system reset signal. When the switching request signal output from the signal output unit is received, the setting of the operation mode requested by the switching request signal is received (claim 1).

  According to this configuration, the switching request signal for requesting the functional module to accept the setting of the operation mode other than the operation mode set in the functional module by the control unit before entering the resetting state is the signal Output toward the holding unit.

  The switching request signal output to the signal holding unit is held in the signal holding unit, and the held switching request signal is output when the system reset signal is asserted and the functional module is reset. The signal is transmitted to the signal output unit by the control unit and output from the signal output unit toward the functional module.

  In addition, when the system module reset signal is asserted and the functional module receives the switching request signal output from the signal output unit, the functional module sets the operation mode requested by the switching request signal. Accept.

  In other words, according to this configuration, the switching request signal output by the control unit is held before the functional module and the control unit are in a reset state, and the functional module and the control unit are in a reset state. At this time, the held switching request signal is output to the function module being reset to cause the function module to switch the function mode.

  Thereby, while the functional module is being reset, the operation mode of the functional module can be switched to another operation mode without controlling the terminal of the functional module.

  In the above configuration, the signal holding unit is a first D-type flip-flop that receives and holds the switching request signal output from the control unit at the D terminal and outputs the held switching request signal from the Q terminal. The signal output unit receives and holds the switching request signal output from the Q terminal of the first D-type flip-flop at the D terminal, and holds the held switching request signal through the Q terminal. The signal output control unit includes a first input terminal connected to a Q terminal of the first D-type flip-flop, and the second D-type flip-flop that outputs to the functional module. A second input terminal connected to the Q terminal of the D-type flip-flop; an output terminal connected to the D terminal of the second D-type flip-flop; and the system reset signal. And the control request terminal receives the switching request signal output from the Q terminal of the first D-type flip-flop toward the first input terminal. When the system reset signal is asserted, it is preferable to output to the D terminal of the second D-type flip-flop through the output terminal.

  According to this configuration, the first D-type flip-flop constituting the signal holding unit receives and holds the switching request signal from the control unit before the reset state. The switching request signal held in the first D-type flip-flop is converted into a second D-type flip-flop that constitutes a signal output unit by a multiplexer when the functional module and the control unit are in a reset state. Is output.

  Then, the switching request signal output to the second D-type flip-flop is output by the second D-type flip-flop toward the functional module being reset.

  As a result, a configuration in which the operation mode of the functional module is switched without controlling the terminal of the functional module while the functional module is being reset can be realized using an inexpensive D-type flip-flop or multiplexer.

  An image forming apparatus according to another aspect of the present invention includes the semiconductor integrated circuit according to claim 1 or 2, wherein the functional module forms image data representing an image of a document on a recording sheet. The image forming module is configured, and the control unit controls the image forming module. According to this configuration, it is possible to provide an image forming apparatus that exhibits the effects of the first or second aspect.

  According to the present invention, the switching request signal output by the control unit is held before the functional module and the control unit are in a reset state, and the functional module and the control unit are in a reset state. In addition, the held switching request signal is output to the function module being reset to cause the function module to switch the function mode.

  Thereby, while the functional module is being reset, the operation mode of the functional module can be switched to another operation mode without controlling the terminal of the functional module.

1 is a schematic cross-sectional view of an image forming apparatus according to an embodiment of the present invention. FIG. 2 is a functional block diagram illustrating an example of a schematic configuration of the image forming apparatus illustrated in FIG. 1. 1 is a block diagram showing an example of a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention. 4 is a timing chart showing an example of the operation of the semiconductor integrated circuit shown in FIG.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of a semiconductor integrated circuit and an image forming apparatus according to the invention will be described with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted.

  FIG. 1 is a schematic sectional view of an image forming apparatus according to an embodiment of the present invention. As shown in FIG. 1, the image forming apparatus A includes an image reading unit 200 and an apparatus main body 3. The image reading unit 200 includes a document feeding unit 210, a scanner unit 220, a CIS 231, a user interface unit I, and a reversing mechanism described later.

  The document feeder 210 includes an ADF (Automatic Document Feeder), and includes a document tray 211, a pickup roller 212, a platen 213, a paper discharge roller 214, and a paper discharge tray 215. A document to be read is placed on the document tray 211. Documents placed on the document tray 211 are picked up one by one by the pickup roller 212 and sequentially conveyed to the platen 213 through the gap. Documents that have passed through the platen 213 are sequentially discharged to the discharge tray 215 by the discharge rollers 214.

  Of the positions facing the peripheral surface of the platen 213, a timing sensor (not shown) for detecting paper is installed at a predetermined position before the reading position P in the document transport direction. The document transport timing to the reading position P is achieved based on the output request. The timing sensor is configured by, for example, a photo interrupter.

  The scanner unit 220 optically reads an image of a document and generates image data. The scanner unit 220 includes a glass 221, a light source 222, a first mirror 223, a second mirror 224, a third mirror 225, a first carriage 226, a second carriage 227, an imaging lens 228, and a CCD (Charged Coupled Device) 229. .

  In the scanner unit 220, a white fluorescent lamp such as a cold cathode fluorescent tube is used as the light source 222, and the first mirror 223, the second mirror 224, the third mirror 225, the first carriage 226, the second carriage 227, and the imaging. A lens 228 guides light from the document to the CCD 229. Since the scanner unit 220 is configured using a white fluorescent lamp such as a cold cathode fluorescent tube as the light source 222, the scanner unit 220 is superior in color reproducibility to a CIS 231 described later in which a three-color LED or the like is used as the light source.

  On the glass 221, a document is manually placed by the user when reading the document without using the document feeder 210. The light source 222 and the first mirror 223 are supported by the first carriage 226, and the second mirror 224 and the third mirror 225 are supported by the second carriage 227.

  As a document reading method of the image reading unit 200, the scanner unit 220 reads a document placed on the glass 221 and the document is read by the document feeding unit 210 (ADF). There is an ADF reading mode for reading.

  In the flatbed reading mode, the light source 222 irradiates a document placed on the glass 221, and reflected light for one line in the main scanning direction is reflected in the order of the first mirror 223, the second mirror 224, and the third mirror 225. Then, the light enters the imaging lens 228. The light incident on the imaging lens 228 is imaged on the light receiving surface of the CCD 229.

  The CCD 229 is a one-dimensional image sensor and processes the image data of one line of the document in an overlapping manner. The first carriage 226 and the second carriage 227 are configured to be movable in a direction orthogonal to the main scanning direction (sub-scanning direction, arrow Y direction). When reading for one line is completed, the first carriage 226 and the second carriage 227 are moved in the sub-scanning direction. The first carriage 226 and the second carriage 227 move, and the next line is read.

  In the ADF reading mode, the document feeder 210 takes in the documents placed on the document tray 211 one by one by the pickup roller 212. At this time, the first carriage 226 and the second carriage 227 are disposed at a predetermined reading position P located below the reading window 230.

  When the document is transported by the document feeder 210, when the document passes over the reading window 230 provided in the transport path from the platen 213 to the paper discharge tray 215, the light source 222 irradiates the document, and the main scanning one line. The reflected light is reflected in the order of the first mirror 223, the second mirror 224, and the third mirror 225 and enters the imaging lens 228. The light incident on the imaging lens 228 is imaged on the light receiving surface of the CCD 229. Subsequently, the document is conveyed by the document feeder 210 and the next line is read.

  Further, the document feeder 210 has a document reversing mechanism including a setting guide 216, a reversing roller 217, and a reversing conveyance path 218. This document reversing mechanism reverses the front and back of the original whose surface has been read by the first ADF reading and transports it again to the reading window 230, whereby the CCD 229 reads the back side again.

  This document reversing mechanism operates only when reading both sides, and does not operate when reading one side. After reading the back side during single-sided reading and double-sided reading, the setting guide 216 is switched to the upper side, and the document that has passed through the platen 213 is discharged to the discharge tray 215 by the discharge roller 214.

  After the front side reading at the time of double-sided reading, the setting guide 216 is switched to the lower side, and the document that has passed through the platen 213 is conveyed to the reverse conveyance path 218 by the reverse roller 217. Thereafter, the setting guide 216 is switched to the upper side, and the reverse roller 217 rotates in the reverse direction to feed the document again to the platen 213. Hereinafter, a mode in which both sides of a document are read using the document reversing mechanism is referred to as a double-sided reversal reading mode.

  Further, when the image reading unit 200 according to the present embodiment causes the CCD 229 (scanner unit 220) to read the surface of the document while the document is being conveyed as described above in the ADF reading mode, the image reading unit 200 substantially overlaps (substantially parallel). Thus, the back side of the document can be read by the CIS 231. In this case, the surface of the document conveyed from the document tray 211 by the document feeder 210 is read by the CCD 229 when passing through the reading window 230, and the back surface is read when passing through the location where the CIS 231 is arranged. In CIS231, RGB three-color LEDs or the like are used as light sources.

  By using the CCD 229 and the CIS 231 in this way, it is possible to read both the front and back sides of a document by a single document transport operation (one pass) from the document tray 211 to the discharge tray 215 by the document feeding unit 210. Hereinafter, a mode in which both sides of a document are read using the CCD 229 and the CIS 231 in this way is referred to as a double-sided simultaneous reading mode.

  The double-sided reverse reading mode and the double-sided simultaneous reading mode are provided as reading modes when performing double-sided reading of a document using the ADF reading mode. The double-sided reverse reading mode is used when you want to match the image quality of both-side printed images, while the double-sided simultaneous reading mode gives priority to shortening the reading time even if there is a difference in the image quality of both-side printed images Used in cases. Note that the image forming apparatus A in the present embodiment is initially set to the double-sided simultaneous reading mode, and when the image forming instruction is input without performing any mode setting operation in the reading mode, the double-sided simultaneous reading mode is set. A document image reading operation is performed in the reading mode.

  The image processing apparatus A includes an apparatus main body 3 and a stack tray 6 disposed on the left side of the apparatus main body 3. The apparatus main body 3 includes a plurality of paper feed cassettes 461, a paper feed roller 462 that feeds recording paper from the paper feed cassette 461 one by one and transports it to the image forming unit 40, and a recording paper transported from the paper feed cassette 461. And an image forming unit 40 for forming an image. The apparatus body 3 also includes a paper feed tray 471 and a feed roller 472 that feeds the originals placed on the paper feed tray 471 one by one toward the image forming unit 40.

  The image forming unit 40 includes a charge removing device 421 that removes residual charges from the surface of the photosensitive drum 43, a charging device 422 that charges the surface of the photosensitive drum 43 after charge removal, and image data acquired by the scanner unit 220. Based on the electrostatic latent image, an exposure device 423 that outputs a laser beam to expose the surface of the photosensitive drum 43 to form an electrostatic latent image on the surface of the photosensitive drum 43. Above, developing devices 44K, 44Y, 44M, and 44C that form toner images of cyan (C), magenta (M), yellow (Y), and black (K), and various colors formed on the photosensitive drum 43. A transfer drum 49 on which the toner image is transferred and superimposed, a transfer device 41 for transferring the toner image on the transfer drum 49 to the paper, and the paper on which the toner image is transferred to the toner by heating The and a fixing device 45 for fixing on the paper.

  Note that toner is supplied to cyan, magenta, yellow, and black colors from a toner cartridge (not shown). Further, conveyance rollers 463 and 464 that convey the recording paper that has passed through the image forming unit 40 to the stack tray 6 or the discharge tray 48 are provided.

  When forming images on both sides of the recording paper, the image forming unit 40 forms an image on one side of the recording paper, and then the recording paper is nipped by the conveyance roller 463 on the discharge tray 48 side. In this state, the conveyance roller 463 is reversed to switch back the recording paper, and the recording paper is sent to the paper conveyance path L and conveyed again to the upstream area of the image forming unit 40, and an image is formed on the other surface by the image forming unit 40. After the formation, the recording paper is discharged to the stack tray 6 or the discharge tray 48.

  Further, in front of the apparatus main body 3, a display unit 106 configured with a touch panel and a user interface unit I including an operation unit 105 having various operation buttons are exposed in front of the apparatus main body 3. Is provided.

  FIG. 2 is a functional block diagram showing an example of a schematic configuration of the image forming apparatus shown in FIG. As shown in FIG. 2, the image forming apparatus A includes a user interface unit I, a control module 1 having a CPU (control unit) 10, a ROM (Read Only Memory) 101, a RAM (Random Access Memory) 102, and an image reading unit 200. An image forming unit 40, an image processing unit 100 for performing predetermined image processing on the image data, and a FAX communication unit 104 for performing facsimile communication through a public line.

  In the image forming apparatus A, the ROM 101 and the RAM 102 store various programs necessary for the operation of the image forming apparatus A.

  Further, in the image forming apparatus A, the operation unit 105, the display unit 106, the image reading unit 200, the image forming unit 40, the image processing unit 100, and the FAX communication unit 104 are respectively an ASIC (Application Specific Integrated Circuit), A functional module including an FPGA (Field Programmable Gate Array) is provided.

  The operation unit 105 includes an operation module 105A as a functional module. The display unit 106 includes a display module 106A as a functional module. The image reading unit 200 includes an image reading module 200A as a functional module. The image forming unit 40 includes an image forming module 40A as a functional module.

  The image processing unit 100 includes an image processing module 100A as a functional module. The FAX communication unit 104 includes a FAX communication module as a function module.

  In the image forming apparatus A, the operation unit 105, the display unit 106, the image reading unit 200, the image forming unit 40, the image processing unit 100, and the FAX communication unit 104 are semiconductor integrated circuits according to an embodiment of the present invention. It is composed.

  FIG. 3 is a block diagram showing an example of a schematic configuration of a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 3, the semiconductor integrated circuit 2 is connected to the control module 1 through a system bus B.

  The semiconductor integrated circuit 2 includes a first D-type flip-flop (signal holding unit; hereinafter referred to as a first flip-flop) 20 and a second D-type flip-flop (signal output unit; hereinafter referred to as a second flip-flop) 21. And a multiplexer (signal output control unit) 23 and a functional module 25.

  The first flip-flop 20 operates by receiving a clock signal (SYSTEM_CLOCK) (see FIG. 4) having a period T generated from the clock signal generation source 22. The D terminal of the first flip-flop 20 is connected to the system bus B. On the system bus B, there is disposed a register (not shown) that receives and holds data consisting of one of values 1 and 0 output from the CPU 10.

  When the CPU 10 sets the operation mode of the functional module 25, when the system reset signal (SYSTEM_RESET_N) is not asserted, the CPU 10 outputs data having a value of 1 or 0 to the register and sets the register. .

  The first flip-flop 20 outputs the data from the Q terminal while receiving and holding the data set in the register through the D terminal of the first flip-flop 20.

  Further, in the first flip-flop 20, the first input terminal 23A of the multiplexer 23 is connected to the Q terminal. The data held in the first flip-flop 20 is output to the first input terminal 23 A of the multiplexer 23 through the Q terminal of the first flip-flop 20. The data output to the first input terminal 23A of the multiplexer 23 is output to the second flip-flop 21 when the first input terminal 23A is selected by the multiplexer 23.

  Similarly to the first flip-flop 20, the second flip-flop 21 also operates by receiving a clock signal (SYSTEM_CLOCK) (see FIG. 4) having a period T generated from the clock signal generation source 22. The second flip-flop 21 holds the data input to the D terminal of the second flip-flop 21 and outputs the data from the Q terminal toward the functional module 25.

  The output terminal 23D of the multiplexer 23 is connected to the D terminal of the second flip-flop 21. In the second flip-flop 21, the Q terminal is connected to the functional module 25.

  In the second flip-flop 21, when the first input terminal 23A is selected by the multiplexer 23, the data output from the Q terminal of the flip-flop 20 is input to the D terminal. The second flip-flop 21 holds the data input to the D terminal and outputs the data to the functional module 25 through the Q terminal.

  Furthermore, one point of the connection line between the Q terminal of the second flip-flop 21 and the functional module 25 is connected to the second input terminal 23 </ b> B of the multiplexer 23. As a result, the data output from the Q terminal of the second flip-flop 21 toward the functional module 25 is fed back to the second input terminal 23B of the multiplexer 23.

  The multiplexer 23 has a first input terminal 23 </ b> A connected to the Q terminal of the first flip-flop 20, and a second input terminal 23 </ b> B to which one point of a connection line between the Q terminal of the second flip-flop 21 and the functional module 25 is connected. And an output terminal 23D and a control terminal 23C.

  A reset signal output unit 24 that outputs a system reset signal (SYSTEM_RESET_N) is connected to the control terminal 23C, and the control terminal 23C receives a system reset signal output from the reset signal output unit 24. The reset signal output unit 24 asserts and deasserts the reset signal.

  The multiplexer 23 selects the second input terminal 23B when the system reset signal (SYSTEM_RESET_N) accepted at the control terminal 23C is not asserted, and the system reset signal (SYSTEM_RESET_N) accepted at the control terminal 23C is asserted. If so, the first input terminal 23A is selected.

  Thereby, the multiplexer 23 outputs the data received at the second input terminal 23B from the output terminal 23D when the system reset signal is not asserted, and from the output terminal 23D when the system reset signal is asserted. The data received at the first input terminal 23A is output.

  The functional module 25 receives data output from the Q terminal of the second flip-flop 21 and sets an operation mode based on the data. The function module 25 sets, for example, the operation mode A when the data is the value “1”, and sets the operation mode B when the data is the value “0”, for example.

  The functional module 25 is connected to the reset signal output unit 24 and is reset when the system reset signal output from the reset signal output unit 24 is asserted.

FIG. 4 is a timing chart showing an example of the operation of the semiconductor integrated circuit shown in FIG.
In FIG. 4, “CPU output” means data that is output from the CPU 10 and that is set to a register (not shown) and has a value of 1 or 0.

  In the semiconductor integrated circuit 2, the functional module 25 has two operation modes, an operation mode A and an operation mode B.

  Hereinafter, a process of switching the operation mode set in the function module 25 from the operation mode B to the operation mode A will be described in which the operation mode B is set in the function module 25.

  Until the time T0 when processing for switching the operation mode of the functional module 25 from the operation mode B to the operation mode A is started, the register outputs the CPU 10 and causes the function module 25 to set the operation mode B. Data consisting of the value “0” used for this purpose is set.

  In addition, until the time T0 arrives, data having a value “0” is set in the register. Therefore, the first flip-flop 20 receives data having a value “0” and stores the data. The data is output toward the first input terminal 23A of the multiplexer 23 while being held.

  However, since the reset signal output from the reset signal output unit 24 is not asserted until the time T0 has arrived, the multiplexer 23 selects the second input terminal 23B.

  Therefore, data consisting of the value “0” output from the first flip-flop 20 to the first input terminal 23A of the multiplexer 23 is not output to the second flip-flop 21 until the time T0 arrives.

  On the other hand, since the multiplexer 23 selects the second input terminal 23B until the time T0 arrives, the operation mode B is set in the functional module 25 fed back from the output side of the second flip-flop 21. Data consisting of the value “0” used for the output is output to the functional module 25.

  Thereafter, when the time T0 arrives, the CPU 10 sends data consisting of a value “1” to the function module 25 in order to switch the operation mode of the function module 25 from the operation mode B to the operation mode A. When it arrives, it outputs to the register as a switching request signal for requesting to accept the setting of the operation mode A other than the operation mode B set in the functional module 25. At this time, the register sets data consisting of the value “1” received from the CPU 10 therein.

  When the time T0 arrives, the first flip-flop 20 receives data consisting of the value “1” set in the register at the D terminal, and the time T1 when the clock signal rises only after the data is received at the D terminal. Until the time T1 arrives, the stored data is output.

  Thereafter, the first flip-flop 20 repeats the same processing until the data having the value “0” is set in the register by the CPU 10, whereby the data having the value “1” set in the register is The output continues toward the first input terminal 23A of the multiplexer 23.

  The multiplexer 23 selects the first input terminal 23A when the system reset signal is asserted at time T2. Thereby, when the time T2 has arrived, the second flip-flop 21 receives the data consisting of the value “1” output from the first flip-flop 20 at the D terminal.

  The second flip-flop 21 holds the data received at the D terminal of the second flip-flop 21 until the time T3 when the clock signal rises for the first time after the data is received at the D terminal, and the time T3 When the data arrives, the stored data is output to the functional module 25 through the Q terminal of the second flip-flop 21.

  Thereafter, the second flip-flop 21 outputs the value “V” output through the first input terminal 23A of the multiplexer 23 and the output terminal 23D of the multiplexer until the time T4 when the assertion of the system reset signal ends. 1 ”is received, and the data is output to the functional module 25 while holding the data.

  As a result, the functional module 25 has the value “1” from the second flip-flop 21 between the time T3 when the assertion of the system reset signal is started and the time T4 when the assertion of the system reset signal ends. Since the data can be received, the operation mode set in the function module 25 is changed from the currently set operation mode B to the operation requested by the switching request signal while the function module 25 is being reset. It is possible to switch to mode A.

  Then, when the time T4 arrives and the assertion of the system reset signal ends, the multiplexer 23 selects the second input terminal 23B.

  The second flip-flop 21 is held immediately before the time T4 arrives at the time T4 when the second input terminal 23B is selected by the multiplexer 23, and is output toward the functional module 25 when the time T4 arrives. The feedback of data consisting of the value “1” is accepted. Then, the second flip-flop 21 outputs the data fed back to the second flip-flop 21 at time T4 toward the functional module 25 when the clock signal rises for the first time after the time T4 has elapsed.

  Thereafter, the second flip-flop 21 repeatedly outputs the data to the functional module 25 while receiving and holding the data fed back from the output side of the second flip-flop 21.

  As described above, according to the semiconductor integrated circuit 2, when the system reset signal is asserted and the functional module 25 is reset, the data set in the register by the CPU 10 is transferred to the first flip-flop 20, the multiplexer 23, And, it is transmitted to the functional module 25 through the second flip-flop 21.

  Thereby, while the functional module 25 is being reset, the operation mode of the functional module 25 can be switched to another operation mode without controlling the terminal of the functional module 25.

A Image forming apparatus 1 Control module 10 CPU
20 first D-type flip-flop 21 second D-type flip-flop 23 multiplexer 23A first input terminal 23B second input terminal 23C control terminal 23D output terminal 25 functional module

Claims (3)

A functional module that is set when any one of a plurality of different operation modes is set and a system reset signal is asserted; and
When the system reset signal is not asserted, the switching request signal for requesting the functional module to accept setting of an operation mode other than the operation mode set in the functional module among the operation modes. A signal holding unit which is connected to the output control unit and holds the switching request signal when the switching request signal is received from the control unit;
A signal output unit that receives the switching request signal held in the signal holding unit and outputs the signal to the functional module;
A signal output control unit that transmits the switching request signal held in the signal holding unit to the signal output unit and outputs the signal to the functional module when the system reset signal is asserted. And
The functional module accepts the setting of the operation mode requested by the switching request signal when the switching request signal output from the signal output unit is received when the system reset signal is asserted. A semiconductor integrated circuit. The signal holding unit includes a first D-type flip-flop that receives and holds the switching request signal output from the control unit at a D terminal and outputs the held switching request signal from a Q terminal. ,
The signal output unit receives and holds the switching request signal output from the Q terminal of the first D-type flip-flop at the D terminal, and outputs the held switching request signal to the functional module through the Q terminal. A second D-type flip-flop
The signal output controller is
A first input terminal connected to a Q terminal of the first D-type flip-flop; a second input terminal connected to a Q terminal of the second D-type flip-flop; and the second D-type flip-flop. An output terminal connected to the D terminal of the system, and a control terminal for receiving the system reset signal.
The output when the switching request signal output from the Q terminal of the first D-type flip-flop toward the first input terminal is accepted by the control terminal is asserted. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit outputs the signal to a D terminal of the second D-type flip-flop through a terminal. A semiconductor integrated circuit according to claim 1 or 2 is provided,
The functional module constitutes an image forming module that forms image data representing an image of a document on a recording sheet,
The image forming apparatus, wherein the control unit controls the image forming module.

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