JP5514609B2 - Unauthorized rewrite detection circuit and image forming apparatus - Google Patents

Description

  The present invention relates to a stacking and image forming apparatus.

  One of the integrated circuits is a programmable logic device such as an FPGA (Field Programmable Gate Array). Since this type of programmable logic device allows a user to execute a desired function, it has recently been rapidly spread in place of an ASIC (Application Specific Integrated Circuit) in which a function that can be executed in advance is determined. .

  An example of this type of programmable logic device is described in Patent Document 1. The semiconductor device described in Patent Document 1 is connected to a system LSI. An FPGA is arranged in the semiconductor device, and a non-volatile memory in which circuit data for the FPGA to function as a NAND interface circuit to which the system LSI can be connected is connected to the FPGA. .

  In this semiconductor device, circuit data stored in the nonvolatile memory is sent to the FPGA. Then, the FPGA forms a NAND interface circuit to which the system LSI can be connected.

JP 2007-26504 A

  However, since the circuit data for executing the function of the programmable logic device is stored in advance in a storage unit such as a nonvolatile memory, it is easy for a third party to rewrite the circuit data stored in the storage unit. In addition, the function of the programmable logic device can be changed to another function.

  For this reason, the programmable logic device may perform a process unexpected by the user. For example, when a chip having a certain function is connected to the FPGA, when the FPGA is rewritten with circuit data for executing a function for analyzing the chip, the FPGA performs processing for analyzing the chip. Execute.

  Therefore, it is possible to appropriately determine that the circuit data for executing the function of the programmable logic device has been rewritten by a third party, and to take measures so that the programmable logic device does not perform an unexpected process by the user. desired.

  By the way, since the storage unit is connected to a programmable logic device and not connected to a control unit such as a CPU (system LSI in Patent Document 1), unless the read circuit of the storage unit is configured in the programmable logic device, the control unit However, the storage unit connected to the programmable logic device cannot be accessed.

  In addition, it is conceivable that the readout circuit of the storage unit is configured in the programmable logic device, and the control unit reads out the circuit data of the storage unit and examines the circuit data. Even when updated, rewriting is detected.

  Therefore, after the programmable logic device is energized and a circuit based on the circuit data stored in the storage unit is configured, when the programmable logic device actually operates, the control unit performs the operation of the programmable logic device. Only after confirmation will it be detected that the circuit data has been illegally rewritten.

  In this case, if the function based on the rewritten circuit data is executed for a long time, it is inconvenient for stabilizing the operation of the device incorporating the programmable logic device.

  The present invention is proposed in order to solve the above problem, and does not access a storage unit storing circuit data for driving a programmable logic device and detects illegal rewriting of circuit data. It is an object of the present invention to provide an unauthorized rewrite detection circuit and an image forming apparatus that can detect an unauthorized rewrite of circuit data by reducing a necessary energization time of a programmable logic device.

An unauthorized rewrite detection circuit according to an aspect of the present invention is information for defining a state of a terminal of a programmable logic device, and represents a terminal type indicating which terminal is an input terminal or an output terminal. And state definition information indicating terminal settings indicating whether the terminal type is the input terminal is pulled up or pulled down , and logic circuit information indicating a logic circuit inside the programmable logic device A first storage unit in which circuit data for driving the programmable logic device is stored in advance, the circuit data stored in the first storage unit is read, and the terminal is included in the circuit data And the logic circuit information included in the circuit data in a state indicated by the state definition information. By configuring the logic circuit represented and starting an operation based on the configured logic circuit, the pulled-up input terminal is set to high level, the pulled-down input terminal is set to low level, and the output terminal and programmable logic devices that the voltage level corresponding to the initial state of the logic circuit described above arrangement and a power supply unit for supplying drive power to the programmable logic device being connected to the terminal, the state of the terminal, the A terminal state detection unit that detects whether the terminal is at a high level or a low level, and a state that the terminal should take immediately after the circuit data is read by the programmable logic device , the voltage level of the terminal is high. second storage state information indicating whether the low level is a level previously stored And after the supply of the driving power by the power supply unit is started, the terminal state detected by the terminal state detection unit is stored in the second storage unit in advance within a preset period. The terminal status detected by the terminal status detection unit is determined to be different from the status indicated by the status information stored in advance in the second storage unit. And a control unit that detects unauthorized rewriting of circuit data stored in the first storage unit when they are different from each other (claim 1).

  According to this configuration, the circuit data including the state definition information for defining the state of the terminals of the programmable logic device and the information representing the logic circuit inside the programmable logic device, stored in the first storage unit. It is determined as follows that there has been unauthorized rewriting.

  That is, according to this configuration, the terminal state of the programmable logic device detected by the terminal state detection unit within the preset period after the supply of driving power to the programmable logic device is started, and the second The control unit determines whether or not the state of the terminal to be taken immediately after the circuit data is read by the programmable logic device indicated by the state information stored in advance in the storage unit.

  As a result of this determination, when the state of the terminal detected by the terminal state detection unit is different from the state indicated by the state information stored in advance in the second storage unit, the control unit is stored in the first storage unit. Detects unauthorized rewrite of circuit data.

  Thereby, the state of the terminal of the programmable logic device can be confirmed and the illegal rewriting of the circuit data can be detected within a preset period after the supply of driving power to the programmable logic device is started.

  Therefore, the energization time of the programmable logic device required for detecting the illegal rewriting of the circuit data is shortened without accessing the storage unit storing the circuit data for driving the programmable logic device, and the circuit data Unauthorized rewriting can be detected.

  In addition, since it is possible to determine whether or not the circuit data is illegally rewritten by detecting the state of the terminal, a dedicated terminal for determining the presence or absence of unauthorized rewriting is not required. Therefore, it is possible to determine whether or not circuit data stored in a storage unit connected to a general-purpose programmable logic device is rewritten.

  In the above configuration, when the control unit detects unauthorized rewriting of the circuit data, the control unit performs a drive stop process for stopping the programmable logic device from being driven based on the circuit data stored in the first storage unit. It is preferable to execute (Claim 2).

  According to this configuration, when illegal rewriting occurs, the programmable logic device stops driving based on the circuit data stored in the first storage unit. As a result, even if the programmable logic device starts unexpected processing by the user when circuit data is illegally rewritten, the time for the programmer logic device to perform unexpected processing by the user is minimized. be able to.

  The said structure WHEREIN: It is preferable that the said control part stops supply of the drive power of the said programmable logic device by the said electric power supply part as the said drive stop process (Claim 3).

  According to this configuration, when unauthorized rewriting occurs, the supply of drive power to the programmable logic device is stopped. Thereby, it can stop driving a programmable logic device based on circuit data memorized by the 1st storage part.

  In the above configuration, the programmable logic device further includes a reset terminal that receives a reset signal, and is configured to be reset when a reset signal received by the reset terminal is asserted. Preferably, a reset signal output unit that outputs the reset signal to a reset terminal is further provided, and the control unit asserts the reset signal as the drive stop process.

  According to this configuration, when there is an illegal rewrite, the programmable logic device is reset, and the circuit data loaded inside the programmable logic device is cleared.

  Thereby, it can stop driving a programmable logic device based on circuit data memorized by the 1st storage part.

  The said structure WHEREIN: The said programmable logic device, the said 1st memory | storage part, the said electric power supply part, the said terminal state detection part, the said 2nd memory | storage part, and the said control part are arrange | positioned on the board | substrate, The said programmable logic It is preferable that the power line for supplying the driving power of the device to the programmable logic device is disposed in the inner layer without being exposed on the surface of the substrate.

  According to this configuration, the power line for supplying the driving power of the programmable logic device to the programmable logic device is arranged in the inner layer without being exposed on the surface of the substrate.

  Thereby, since it becomes difficult for a third party to visually recognize the power line, it is possible to prevent the third party from cutting the power line so that the driving stop process of the programmable logic device is not performed.

  In the above configuration, the programmable logic device, the first storage unit, the power supply unit, the terminal state detection unit, the second storage unit, the control unit, and the reset signal output unit are arranged on a substrate. Preferably, a reset signal line for outputting the reset signal to the reset terminal is disposed in the inner layer without being exposed on the surface of the substrate.

  According to this configuration, the reset signal line for outputting the reset signal to the reset terminal is arranged on the inner layer of the substrate.

  This makes it difficult for a third party to visually recognize the reset signal line, so that the third party crafts the reset signal line so that the drive stop process of the programmable logic device is not performed (for example, cutting the reset signal line) It becomes difficult.

An image forming apparatus according to another aspect of the present invention includes an unauthorized rewrite detection circuit according to any one of claims 1 to 6 and image processing for performing image processing on image data representing an image of a document. And an image forming unit that forms the image data on a recording sheet, and the image processing unit is configured by the programmable logic device (claim 7).

  According to this configuration, it is possible to provide an image forming apparatus that exhibits the effects of any one of claims 1 to 6.

  According to the present invention, it is possible to check the state of a terminal of the programmable logic device and detect unauthorized rewriting of circuit data within a preset period after the supply of driving power to the programmable logic device is started. it can.

  Therefore, the energization time of the programmable logic device required for detecting the illegal rewriting of the circuit data is shortened without accessing the storage unit storing the circuit data for driving the programmable logic device, and the circuit data Unauthorized rewriting can be detected.

1 is a schematic cross-sectional view of an image forming apparatus according to an embodiment of the present invention. FIG. 2 is a functional block diagram illustrating an example of a schematic configuration of the image forming apparatus illustrated in FIG. 1. It is a functional block diagram showing an example of a schematic configuration of an unauthorized rewrite detection circuit according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a cross section of the unauthorized rewrite detection circuit illustrated in FIG. 3 and illustrating the arrangement of power lines. FIG. 4 is a diagram illustrating a cross section of the unauthorized rewrite detection circuit illustrated in FIG. 3 and illustrating the arrangement of reset signal lines. It is the flowchart which showed an example of operation | movement of a control module.

  Hereinafter, an embodiment of an unauthorized rewrite detection circuit and an image forming apparatus according to the present invention will be described with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted.

  FIG. 1 is a schematic sectional view of an image forming apparatus according to an embodiment of the present invention. As shown in FIG. 1, the image forming apparatus A includes an image reading unit 200 and an apparatus main body 3. The image reading unit 200 includes a document feeding unit 210, a scanner unit 220, a CIS 231, a user interface unit I, and a reversing mechanism described later.

  The document feeder 210 includes an ADF (Automatic Document Feeder), and includes a document tray 211, a pickup roller 212, a platen 213, a paper discharge roller 214, and a paper discharge tray 215. A document to be read is placed on the document tray 211. Documents placed on the document tray 211 are picked up one by one by the pickup roller 212 and sequentially conveyed to the platen 213 through the gap. Documents that have passed through the platen 213 are sequentially discharged to the discharge tray 215 by the discharge rollers 214.

  Of the positions facing the peripheral surface of the platen 213, a timing sensor (not shown) for detecting paper is installed at a predetermined position before the reading position P in the document transport direction. The document transport timing to the reading position P is achieved based on the output request. The timing sensor is configured by, for example, a photo interrupter.

  The scanner unit 220 optically reads an image of a document and generates image data. The scanner unit 220 includes a glass 221, a light source 222, a first mirror 223, a second mirror 224, a third mirror 225, a first carriage 226, a second carriage 227, an imaging lens 228, and a CCD (Charged Coupled Device) 229. .

  In the scanner unit 220, a white fluorescent lamp such as a cold cathode fluorescent tube is used as the light source 222, and the first mirror 223, the second mirror 224, the third mirror 225, the first carriage 226, the second carriage 227, and the imaging. A lens 228 guides light from the document to the CCD 229. Since the scanner unit 220 is configured using a white fluorescent lamp such as a cold cathode fluorescent tube as the light source 222, the scanner unit 220 is superior in color reproducibility to a CIS 231 described later in which a three-color LED or the like is used as the light source.

  On the glass 221, a document is manually placed by the user when reading the document without using the document feeder 210. The light source 222 and the first mirror 223 are supported by the first carriage 226, and the second mirror 224 and the third mirror 225 are supported by the second carriage 227.

  As a document reading method of the image reading unit 200, the scanner unit 220 reads a document placed on the glass 221 and the document is read by the document feeding unit 210 (ADF). There is an ADF reading mode for reading.

  In the flatbed reading mode, the light source 222 irradiates a document placed on the glass 221, and reflected light for one line in the main scanning direction is reflected in the order of the first mirror 223, the second mirror 224, and the third mirror 225. Then, the light enters the imaging lens 228. The light incident on the imaging lens 228 is imaged on the light receiving surface of the CCD 229.

  The CCD 229 is a one-dimensional image sensor and processes the image data of one line of the document in an overlapping manner. The first carriage 226 and the second carriage 227 are configured to be movable in a direction orthogonal to the main scanning direction (sub-scanning direction, arrow Y direction). When reading for one line is completed, the first carriage 226 and the second carriage 227 are moved in the sub-scanning direction. The first carriage 226 and the second carriage 227 move, and the next line is read.

  In the ADF reading mode, the document feeder 210 takes in the documents placed on the document tray 211 one by one by the pickup roller 212. At this time, the first carriage 226 and the second carriage 227 are disposed at a predetermined reading position P located below the reading window 230.

  When the document is transported by the document feeder 210, when the document passes over the reading window 230 provided in the transport path from the platen 213 to the paper discharge tray 215, the light source 222 irradiates the document, and the main scanning one line. The reflected light is reflected in the order of the first mirror 223, the second mirror 224, and the third mirror 225 and enters the imaging lens 228. The light incident on the imaging lens 228 is imaged on the light receiving surface of the CCD 229. Subsequently, the document is conveyed by the document feeder 210 and the next line is read.

  Further, the document feeder 210 has a document reversing mechanism including a switching guide 216, a reversing roller 217, and a reversing conveyance path 218. This document reversing mechanism reverses the front and back of the original whose surface has been read by the first ADF reading and transports it again to the reading window 230, whereby the CCD 229 reads the back side again.

  This document reversing mechanism operates only when reading both sides, and does not operate when reading one side. After reading the back side during single-sided reading and double-sided reading, the switching guide 216 is switched to the upper side, and the document that has passed through the platen 213 is discharged to the discharge tray 215 by the discharge roller 214.

  After the front side reading at the time of double-sided reading, the switching guide 216 is switched to the lower side, and the document that has passed through the platen 213 is transported to the reverse transport path 218 by the reverse roller 217. Thereafter, the switching guide 216 is switched upward, and the reverse roller 217 rotates in the reverse direction to re-feed the document to the platen 213. Hereinafter, a mode in which both sides of a document are read using the document reversing mechanism is referred to as a double-sided reversal reading mode.

  Further, when the image reading unit 200 according to the present embodiment causes the CCD 229 (scanner unit 220) to read the surface of the document while the document is being conveyed as described above in the ADF reading mode, the image reading unit 200 substantially overlaps (substantially parallel). Thus, the back side of the document can be read by the CIS 231. In this case, the surface of the document conveyed from the document tray 211 by the document feeder 210 is read by the CCD 229 when passing through the reading window 230, and the back surface is read when passing through the location where the CIS 231 is arranged. In CIS231, RGB three-color LEDs or the like are used as light sources.

  By using the CCD 229 and the CIS 231 in this way, it is possible to read both the front and back sides of a document by a single document transport operation (one pass) from the document tray 211 to the discharge tray 215 by the document feeding unit 210. Hereinafter, a mode in which both sides of a document are read using the CCD 229 and the CIS 231 in this way is referred to as a double-sided simultaneous reading mode.

  The double-sided reverse reading mode and the double-sided simultaneous reading mode are provided as reading modes when performing double-sided reading of a document using the ADF reading mode. The double-sided reverse reading mode is used when you want to match the image quality of both-side printed images, while the double-sided simultaneous reading mode gives priority to shortening the reading time even if there is a difference in the image quality of both-side printed images Used in cases. Note that the image forming apparatus A in the present embodiment is initially set to the double-sided simultaneous reading mode, and when the image forming instruction is input without performing any mode setting operation in the reading mode, the double-sided simultaneous reading mode is set. A document image reading operation is performed in the reading mode.

  The image processing apparatus A includes an apparatus main body 3 and a stack tray 6 disposed on the left side of the apparatus main body 3. The apparatus main body 3 includes a plurality of paper feed cassettes 461, a paper feed roller 462 that feeds recording paper from the paper feed cassette 461 one by one and transports it to the image forming unit 40, and a recording paper transported from the paper feed cassette 461. And an image forming unit 40 for forming an image. The apparatus body 3 also includes a paper feed tray 471 and a feed roller 472 that feeds the originals placed on the paper feed tray 471 one by one toward the image forming unit 40.

  The image forming unit 40 includes a charge removing device 421 that removes residual charges from the surface of the photosensitive drum 43, a charging device 422 that charges the surface of the photosensitive drum 43 after charge removal, and image data acquired by the scanner unit 220. Based on the electrostatic latent image, an exposure device 423 that outputs a laser beam to expose the surface of the photosensitive drum 43 to form an electrostatic latent image on the surface of the photosensitive drum 43. Above, developing devices 44K, 44Y, 44M, and 44C that form toner images of cyan (C), magenta (M), yellow (Y), and black (K), and various colors formed on the photosensitive drum 43. A transfer drum 49 on which the toner image is transferred and superimposed, a transfer device 41 for transferring the toner image on the transfer drum 49 to the paper, and the paper on which the toner image is transferred to the toner by heating The and a fixing device 45 for fixing on the paper.

  Note that toner is supplied to cyan, magenta, yellow, and black colors from a toner cartridge (not shown). Further, conveyance rollers 463 and 464 that convey the recording paper that has passed through the image forming unit 40 to the stack tray 6 or the discharge tray 48 are provided.

  When forming images on both sides of the recording paper, the image forming unit 40 forms an image on one side of the recording paper, and then the recording paper is nipped by the conveyance roller 463 on the discharge tray 48 side. In this state, the conveyance roller 463 is reversed to switch back the recording paper, and the recording paper is sent to the paper conveyance path L and conveyed again to the upstream area of the image forming unit 40, and an image is formed on the other surface by the image forming unit 40. After the formation, the recording paper is discharged to the stack tray 6 or the discharge tray 48.

  Further, in front of the apparatus main body 3, a display unit 106 configured with a touch panel and a user interface unit I including an operation unit 105 having various operation buttons are exposed in front of the apparatus main body 3. Is provided.

  FIG. 2 is a functional block diagram showing an example of a schematic configuration of the image forming apparatus shown in FIG. As illustrated in FIG. 2, the image forming apparatus A includes a user interface unit I, a control module 1 including a CPU (control unit) 10, a ROM (Read Only Memory) 101, and a RAM (Random Access Memory). 102, an image reading unit 200, an image forming unit 40, an image processing unit 100 that performs predetermined image processing on image data, a network interface 103 for connecting to a communication network such as a LAN, and facsimile communication through a public line A FAX communication unit 104 is provided.

  In the image forming apparatus A, the ROM 101 and the RAM 102 store various data necessary for the operation of the image forming apparatus A.

  In the image forming apparatus A, the operation unit 105, the display unit 106, the image processing unit 100, the network interface 103, and the FAX communication unit 104 are each an FPGA (Field Programmable Gate Array) that is one of programmable logic devices. ).

  In the image forming apparatus A, the operation unit 105, the display unit 106, the image reading unit 200, the image forming unit 40, the image processing unit 100, the network interface 103, and the FAX communication unit 104 are each an FPGA 2 according to the present invention. It is incorporated in the unauthorized rewrite detection circuit according to the embodiment.

  FIG. 3 is a functional block diagram showing an example of a schematic configuration of an unauthorized rewrite detection circuit according to an embodiment of the present invention.

  The unauthorized rewrite detection circuit C shown in FIG. 3 is configured by arranging a control module 1, an FPGA 2, and an EEPROM (first storage unit) 4 on a substrate B.

  The FPGA 2 is configured to be able to set which terminal T to use as an input terminal, an output terminal, or an input / output terminal. The FPGA 2 is configured to be able to set either pull-up or pull-down for the input terminal and the input / output terminal in the input state. Such setting is set by circuit data to be described later.

  The EEPROM 4 stores circuit data composed of state definition information for defining the state of the terminal T and logic circuit information representing a logic circuit inside the FPGA 2. The EEPROM 4 is connected to the FPGA 2, and circuit data stored in the EEPROM 4 is read by the FPGA 2.

  The FPGA 2 is driven based on circuit data read from the EEPROM 4. This circuit data indicates the state that the terminal T should take after the circuit data is read by the FPGA 2 for each terminal T in the state definition information.

  For example, the state definition information indicates a terminal type that indicates which of the input terminal, the output terminal, and the input / output terminal for each terminal T. The state definition information indicates terminal settings indicating whether the terminal T is pulled up or pulled down for the terminal T whose terminal type is an input terminal and the terminal T whose terminal type is an input / output terminal. .

  The FPGA 2 reads the above circuit data, sets each terminal T to the state indicated by the state definition information, and configures a logic circuit represented by the circuit information. Then, the FPGA 2 starts an operation based on the configured circuit. Then, a signal corresponding to the initial state of the circuit is output from the output terminal.

  In addition to the CPU 10, the control module 1 includes a power supply unit 11, a terminal state detection unit 12, a reset signal output unit 13, and an EEPROM (second storage unit) 14. In the control module 1, the power supply unit 11, the terminal state detection unit 12, the reset signal output unit 13, and the EEPROM 14 are each connected to the CPU 10 and controlled by the CPU 10.

  In the present embodiment, the power supply unit 11, the terminal state detection unit 12, the reset signal output unit 13, and the EEPROM 14 are incorporated in the control module 1. However, the present invention is not limited to this example, and may be arranged independently of the control module 1.

  The power supply unit 11 includes a power feeding terminal T1, and the power receiving terminal T3 of the FPGA 2 is connected to the power feeding terminal T1. The power supply unit 11 supplies drive power for driving the FPGA 2 from the power supply terminal T1 to the power reception terminal T2 through the power line L2. Thereby, the FPGA 2 receives the driving power.

  The EEPROM 14 stores state information indicating the state that each terminal T should take immediately after the circuit data stored in the EEPROM 4 is read by the FPGA 2 in order for the CPU 10 to perform illegal rewrite determination processing described later. .

  For example, the state information indicates whether the voltage level of the terminal T is high level or low level for each terminal T set as one of the input terminal, the output terminal, and the input / output terminal. .

  The terminal state detection unit 12 is connected to the CPU 10 and the FPGA 2, and relays a signal output to the FPGA 2 by the CPU 10 and a signal output to the CPU 10 by the FPGA 2.

  The terminal state detection unit 12 is connected to a plurality of terminals T of the FPGA 2 through the signal line L1, and detects the state of each terminal T immediately after the FPGA 2 reads the circuit data stored in the EEPROM 4.

  The terminal state detection unit 12 determines the state of each terminal T as follows, for example. That is, the terminal state detection unit 12 detects whether the voltage level of the signal line L1 is high level or low level for each signal line L1.

  The terminal state detection unit 12 detects that the voltage level of the terminal T to which the signal line L1 having a high voltage level is connected is high, and is connected to the signal line L1 having a low voltage level. It is detected that the voltage level of the terminal T is low.

  The CPU 10 detects whether or not the circuit data has been illegally rewritten based on the state of each terminal T detected by the terminal state detection unit 12. That is, the CPU 10 determines whether or not the state detected by the terminal state detection unit 12 for each terminal T is different from the state stored for the terminal T in the EEPROM 14. If different, the CPU 10 stores the state in the EEPROM 4. It is detected that there is an illegal rewrite of the circuit data being read.

  The reset signal output unit 13 includes a reset signal output terminal T2, and a reset signal input terminal (reset terminal) T4 of the FPGA 2 is connected to the reset signal output terminal T2. The reset signal output unit 13 supplies a reset signal for resetting the FPGA 2 from the reset signal output terminal T2 to the reset signal input terminal T4 through the reset signal line L3.

  When resetting the FPGA 2, the reset signal output unit 13 asserts the reset signal so that the reset signal is switched from the high level to the low level or from the low level to the high level. The FPGA 2 is reset when the reset signal input to the reset signal input terminal T4 is asserted, and clears the circuit data loaded therein.

  FIG. 4 shows a cross section of the unauthorized rewrite detection circuit shown in FIG. 3 and is a diagram for explaining the arrangement of the power line L2. FIG. 5 shows a cross section of the unauthorized rewrite detection circuit shown in FIG. 3, and is a diagram for explaining the arrangement of the reset signal line L3.

  As shown in FIG. 4, the control module 1 and the FPGA 2 are, for example, leadless packages such as a BGA (Ball grid array) package. The power supply unit 11 is provided in such a package, and a power feeding terminal T1 and a power receiving terminal T3 are disposed in the lower part of the package. Between the power feeding terminal T1 and the power receiving terminal T3, a power feeding line L2 that is not exposed on the surface of the substrate B and is located only in the inner layer is disposed.

  Further, as shown in FIG. 5, the leadless package is provided with a reset signal output unit 13, and a reset signal output terminal T2 and a reset signal input terminal T4 are arranged below the package. Between the reset signal output terminal T2 and the reset signal input terminal T4, a reset signal line L3 that is not exposed on the surface of the substrate B and is located only in the inner layer is disposed.

  As a result, it becomes difficult for a third party to visually recognize the power line L2 and the reset signal line L3, and the power line L2 and the reset signal line L3 are crafted by the third party, and the drive stop process described later is hindered. Can be prevented.

  From the viewpoint of preventing a drive stop process described later from being hindered, a control line L4 between the power supply unit 11 and the CPU 10 and a control line L5 between the reset signal output unit 13 and the CPU 10 are provided on the substrate. You may arrange | position in the inner layer of B.

  Hereinafter, the operation of the control module 1 including the unauthorized rewrite determination process and the drive stop process will be described. FIG. 6 is a flowchart showing an example of the operation of the control module 1.

  The control module 1 starts supply of drive power to the FPGA 2 by the power supply unit 11 (step S1). Thereby, the FPGA 2 reads the circuit data stored in the EEPROM 4 and starts driving based on the circuit data.

  Then, the pulled-up input terminal becomes high level, the pulled-down input terminal becomes low level, and the output terminal becomes a signal level corresponding to the initial state of the circuit. As a result, the voltage level is high at each terminal T of the FPGA 2. It will be in either the level or low level state.

  Next, the control module 1 detects the state of the terminal T for each terminal T of the FPGA 2 by the terminal state detection unit 12 (step S2). Examples of the method for detecting the state of the terminal T include the method described above.

  Next, the control module 1 determines, for each terminal T, whether or not the state of the terminal T detected by the terminal state detection unit 12 matches the state of the terminal T stored in advance in the EEPROM 14 by the CPU 10. (Step S3; unauthorized rewrite determination process).

  In step S3, when the state of the terminal T detected by the terminal state detection unit 12 does not match the state of the terminal T stored in advance in the EEPROM 14 for any one terminal T (NO in step S4), the CPU 10 On the other hand, it is determined that the circuit data has been illegally rewritten, and the drive stop process is performed (step S5).

  On the other hand, when all the terminals T match in step S3 (YES in step S3), the control module 1 does not perform the drive stop process. Therefore, the FPGA 2 continues driving based on the circuit data, and as a result, actually starts the operation based on the circuit data.

  The drive stop process (step S5) by the CPU 10 is, for example, the following process. That is, the CPU 10 outputs a control signal for requesting the power supply unit 11 to stop the supply of drive power to the FPGA 2 through the control line L4, and stops the supply of drive power to the FPGA 2 by the power supply unit 11. Thereby, the driving of the FPGA 2 is stopped.

  Alternatively, the CPU 10 asserts the reset signal by outputting a control signal requesting to assert the reset signal output to the FPGA 2 to the reset signal output unit 13 through the control line L5. As a result, the circuit data loaded in the FPGA 2 is cleared, and the driving of the FPGA 2 is stopped.

  As described above, according to the unauthorized rewrite detection circuit C, circuit data is read by the FPGA 2, and the state of each terminal T is set to a high level or a low level according to the signal level corresponding to the state definition information or the initial state of the circuit. Then, it is determined whether or not the circuit data is illegally rewritten.

  For this reason, it is possible to detect the presence or absence of unauthorized rewriting of circuit data after the supply of drive power to the FPGA 2 is started and before the state of the circuit configured in the FPGA 2 changes from the initial state to another state. it can.

  As a result, the EEPROM 4 storing circuit data for driving the FPGA 2 is not accessed, and the energization time of the FPGA 2 necessary for detecting unauthorized rewriting of the circuit data is shortened to detect unauthorized rewriting of the circuit data. can do.

  Further, according to the illegal rewrite detection circuit C, the drive stop process is performed when it is determined that the circuit data has been illegally rewritten. Therefore, when the circuit data is illegally rewritten, the circuit configured in the FPGA 2 The FPGA drive can be stopped until the state changes from the initial state to another state.

  Therefore, even if the circuit data is rewritten and the FPGA 2 starts a process unexpected by the user, the execution time of the process can be suppressed as much as possible.

A Image forming apparatus B Substrate C Unauthorized rewrite detection circuit 2 FPGA
4, 14 EEPROM
10 CPU
11 Power Supply Unit 12 Terminal State Detection Unit 13 Reset Signal Output Unit L2 Power Line L3 Reset Signal Line T Terminal

Claims (7)

It is information for defining the state of the terminal of the programmable logic device , and indicates a terminal type indicating whether the terminal is an input terminal or an output terminal, and the terminal type is the input terminal. A circuit for driving the programmable logic device, comprising state definition information indicating terminal settings indicating whether the terminal is to be pulled up or pulled down , and logic circuit information indicating an internal logic circuit of the programmable logic device A first storage unit in which data is stored in advance;
The circuit data stored in the first storage unit is read, the terminal is set to a state indicated by the state definition information included in the circuit data, and is represented by the logic circuit information included in the circuit data. Configured to start the operation based on the configured logic circuit, the pulled-up input terminal is set to high level, the pulled-down input terminal is set to low level, and the output terminal is set to and programmable logic devices that the voltage level corresponding to the initial state of the logic circuit described above arrangement,
A power supply for supplying drive power to the programmable logic device;
A terminal state detection unit connected to the terminal and detecting the state of the terminal depending on whether the terminal is at a high level or a low level ;
Second state in which state information indicating whether the voltage level of the terminal is high or low is stored in advance as a state that the terminal should take immediately after the circuit data is read by the programmable logic device. A storage unit;
A state in which the state of the terminal detected by the terminal state detection unit is stored in advance in the second storage unit within a preset period after the supply of the driving power by the power supply unit is started. It is determined whether or not the state indicated by the information is different, and when the terminal state detected by the terminal state detecting unit is different from the state indicated by the state information stored in advance in the second storage unit A control unit for detecting unauthorized rewriting of circuit data stored in the first storage unit;
An unauthorized rewrite detection circuit comprising: The controller is
The drive stop process for stopping the drive of the programmable logic device based on the circuit data stored in the first storage unit when the illegal rewrite of the circuit data is detected is performed. The unauthorized rewrite detection circuit according to 1. The controller is
The unauthorized rewrite detection circuit according to claim 2, wherein as the drive stop process, supply of drive power to the programmable logic device by the power supply unit is stopped. The programmable logic device further includes a reset terminal for receiving a reset signal, and is configured to be reset when a reset signal received by the reset terminal is asserted,
The unauthorized rewrite detection circuit further includes a reset signal output unit that outputs the reset signal to the reset terminal,
The unauthorized rewrite detection circuit according to claim 2, wherein the control unit asserts the reset signal as the drive stop process. The programmable logic device, the first storage unit, the power supply unit, the terminal state detection unit, the second storage unit, and the control unit are arranged on a substrate,
The power line for supplying the drive power of the programmable logic device to the programmable logic device is disposed in the inner layer without being exposed on the surface of the substrate. The unauthorized rewrite detection circuit according to claim 1. The programmable logic device, the first storage unit, the power supply unit, the terminal state detection unit, the second storage unit, the control unit, and the reset signal output unit are arranged on a substrate,
The unauthorized rewrite detection circuit according to claim 4, wherein a reset signal line for outputting the reset signal to the reset terminal is arranged in an inner layer without being exposed on the surface of the substrate. An unauthorized rewrite detection circuit according to any one of claims 1 to 6,
An image processing unit that performs image processing on image data representing an image of a document;
An image forming unit for forming the image data on recording paper;
With
The image processing unit is configured by the programmable logic device.

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