JP2011199141A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of a semiconductor device.SOLUTION: The device includes: a silicon carbide substrate 1; a transistor having a first conductivity type drift region 2 formed on the silicon carbide substrate 1, a second conductivity type well region 3 formed in the drift region 2 in contact with a principal plane of the drift region 2, a first conductivity type source region 4 formed in the well region 3 in contact with the principal plane of the drift region 2, a gate electrode 6 formed on the well region 3 sandwiched between the drift region 2 and the source region 4 via a gate insulating film 5, a source electrode 7 connected with the well region 3 and the source region 4, and a drain electrode 9 connected with the silicon carbide substrate 1; and a diode 12 having an anode constituted of a second conductivity type diffusion region 10 formed in the drift region 2, and a cathode constituted of a first conductivity type diffusion region 11 formed in the second conductivity type diffusion region 10. The cathode is configured by being connected with the gate electrode 6.

Description

  The present invention relates to a semiconductor device that controls operation based on a result of estimating a temperature of a semiconductor device.

  Conventionally, as this type of technology, for example, those described in the following documents are known (see Patent Document 1). In the technique described in this document, a polysilicon PN junction diode is formed in a semiconductor chip, and a forward voltage drop when a constant current is passed through the diode is provided separately from the semiconductor chip. Measure with The temperature of the semiconductor chip is estimated based on the measured value, and the gate drive circuit is controlled based on the estimated temperature.

Japanese Patent No. 3194353

  In the above prior art, in order to connect the temperature detection circuit and the diode on the semiconductor chip, it is necessary to provide an electrode junction portion having a certain area on the semiconductor chip. Since this electrode junction requires a predetermined area, the chip size is increased, which is an obstacle to the reduction of the chip size.

  Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device having a reduced configuration.

  In order to achieve the above object, the present invention is formed in an anode composed of a second conductivity type semiconductor region formed in a drift region on a semiconductor substrate on which a transistor is formed, and in the second conductivity type semiconductor region. In addition, a diode is constituted by a cathode made of the first conductivity type semiconductor region, and the cathode is constituted by being connected to a gate electrode of the transistor.

  According to the present invention, since the gate electrode of the transistor and the cathode of the diode are connected, the area of the junction required when connecting the diode and the temperature detecting circuit in the semiconductor device is eliminated. Thereby, a semiconductor device can be reduced in size.

It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the characteristic of the diode contained in the semiconductor device which concerns on Embodiment 1 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 1 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 1 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 1 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 1 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 1 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 4 of this invention. It is a figure which shows the characteristic of the diode contained in the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 5 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 5 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 5 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 5 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 5 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 5 of this invention. It is process sectional drawing which shows the manufacturing method of the apparatus which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 7 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 8 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 9 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 10 of this invention.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. In FIG. 1, this semiconductor device includes a MOSFET type transistor and a PN junction type diode on a silicon carbide substrate 1.

On one main surface of the N-type high concentration (N ⁺ -type) silicon carbide substrate 1, an N-type low concentration (N ⁻ -type) drift region 2 is formed. A P-type well region 3 is selectively formed on one main surface side of the N ⁻ -type drift region 2, and an N-type source region 4 is formed in the well region 3. A gate insulating film 5 is formed so as to be in contact with the main surface of the well region 3 serving as a channel of the transistor, and a polycrystalline silicon (polysilicon) gate electrode 6 is formed through the gate insulating film 5. A source electrode 7 is formed in the well region 3 and the source region 4 so as to be in ohmic contact with low resistance. The source electrode 7 and the gate electrode 6 are insulated by an interlayer insulating film 8. A drain electrode 9 is formed on the back surface of the silicon carbide substrate 1 in an ohmic connection with low electrical resistance. The transistor includes the drift region 2, the source region 4, and the gate electrode 6, and is configured as a so-called vertical MOSFET.

A P-type diffusion region 10 is selectively formed on one main surface side of the drift region 2. The P type diffusion region 10 is not electrically connected to the P type well region 3. An N-type diffusion region 11 is formed in the diffusion region 10. A gate electrode 6 is formed on the diffusion region 11, and the diffusion region 11 and the gate electrode 6 are electrically ohmically connected. As a result, a PN junction diode 12 having the P-type diffusion region 10 as an anode and the N-type diffusion region 11 as a cathode is configured. Furthermore, a diode 13 is configured with the P-type diffusion region 10 as an anode and the N ⁻ -type drift region 2 as a cathode.

  A portion denoted by reference numeral 101 corresponds to a so-called unit cell of the MOSFET, and in a portion outside the range shown in FIG. 1, the unit cell 101 is repeatedly arranged in the horizontal direction on the paper surface.

  Next, basic operation of the transistor having the structure shown in FIG. 1 will be described. The transistor functions as a transistor by controlling the potential of the gate electrode 6 with a predetermined positive potential applied to the drain electrode 9 with the potential of the source electrode 7 as a reference. That is, when the voltage between the gate electrode 6 and the source electrode 7 is set to a predetermined threshold voltage or more, an inversion layer is formed in the channel portion of the well region 3 under the gate electrode 6, so that the on state is established. Current flows to On the other hand, when the voltage between the gate electrode 6 and the source electrode 7 is set to a predetermined threshold voltage or less, the inversion layer disappears and is turned off, and the current is cut off.

In the on state, the power W represented by the following equation (1) is consumed in the transistor mainly by the source-drain voltage Vds and the drain current Id.
(Equation 1)
W = Vds × Id (1)
Due to this electric power W, the transistor generates heat, and the temperature of the silicon carbide substrate 1 rises.

  FIG. 2 shows the reverse current-voltage characteristics of the diode 12. When a reverse voltage is applied to the diode, a reverse current flows. This reverse current increases exponentially with increasing temperature. In FIG. 2, the reverse direction current voltage characteristic in the case of 25 degreeC, 75 degreeC, 125 degreeC, and 150 degreeC is shown typically. Here, the maximum allowable operating temperature of the transistor is 150 ° C. A voltage is applied to the gate electrode 6 of the transistor from a gate drive circuit (not shown). The gate drive circuit controls application of voltage and current for switching control of the transistor to the gate electrode 6. In order to charge the gate capacitance when the transistor shifts from the off state to the on state, the transistor has a predetermined upper limit on the current supply capability of the gate drive circuit.

As shown in FIG. 2, when the gate voltage of the transistor in the on state is VG1, this gate voltage is also applied to the cathode of the diode 12, and the reverse current of the diode 12 is sufficiently low at 25 ° C. When the transistor is kept on, the temperature of the transistor rises due to the power W. As a result, even if the temperature rises to 75 ° C., the reverse current of the diode 12 is still sufficiently low. When the temperature further rises to 125 ° C., the reverse current of the diode 12 matches the upper limit (gate upper limit current) of the current supply capability of the gate drive circuit. Even in this case, the transistor is on. When the temperature further rises and reaches the allowable maximum operating temperature of 150 ° C., the reverse current of the diode 12 at the gate voltage VG1 exceeds the upper limit of the current supply capability of the gate drive circuit. That is, the reverse current of the diode 12 when the allowable maximum operating temperature of the transistor is exceeded is set to be larger than the upper limit gate upper limit current that the gate drive circuit can supply to the gate electrode. As a result, the reverse current of the diode 12 decreases to the upper limit value of the current supply capability of the gate drive circuit at 150 ° C. as shown in FIG. 2, and the gate voltage decreases to VG2. By setting the gate voltage VG2 to be equal to or lower than the gate threshold voltage of the transistor, the transistor can be shifted from the on state to the off state. Thereby, generation of heat in the transistor can be stopped.

  The temperature dependence of the reverse current of the diode 12 can be easily adjusted by controlling the impurity concentration of the P-type diffusion region 10 and the N-type diffusion region 11 constituting the diode 12. For example, in a power MOSFET having a withstand voltage of about 600 V, setting the gate voltage VG1 to about 15 V and VG2 to about 5 V or less makes it possible to suppress the temperature of the transistor from exceeding the maximum operating temperature.

  Note that the leak current generated in the diode 12 flows to the drain electrode 9 through the diode 13. The forward voltage drop in the diode 13 is about 3V or less in the case of silicon carbide, and is smaller than the reverse voltage of the diode 12, so that the above operation is not affected. Even if the base material is silicon, the forward voltage drop of the diode 13 is about 0.6 V, and does not affect the above operation.

  Next, a method for manufacturing the semiconductor device having the configuration shown in FIG. 1 will be described with reference to FIGS.

First, in the step shown in FIG. 3A, a drift region 2 made of an N ⁻ type silicon carbide epitaxial layer is formed on an N ⁺ type silicon carbide substrate 1. There are several polytypes (crystal polymorphs) in silicon carbide, but here it will be described as representative 4H. Silicon carbide substrate 1 has a thickness of about several tens to several hundreds of μm. The drift region 2 has, for example, an impurity concentration of 10 ¹⁴ to
The film is formed with a thickness of 10 ¹⁸ cm ⁻³ and a thickness of several μm to several tens of μm.

  Next, in the process shown in FIG. 3B, the insulating film 14 is deposited on the drift region 2. A silicon oxide film can be used as the insulating film 14, and a thermal CVD method or a plasma CVD method can be used as a deposition method.

  Subsequently, a resist (not shown) formed on the insulating film 14 is patterned. As a patterning method, a general photolithography method can be used. The insulating film 14 is selectively removed by etching using the patterned resist as a mask. As an etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used.

  Subsequently, the resist is removed with oxygen plasma or sulfuric acid. Thereafter, the P-type impurity 15 is selectively ion-implanted using the insulating film 14 as a mask to form the well region 3 and the P-type diffusion region 10. As the P-type impurity 15, aluminum or boron can be used. At this time, by performing ion implantation while the substrate temperature is heated to about 600 ° C., it is possible to suppress the occurrence of crystal defects in the implanted region. In the first embodiment, the method of forming the well region 3 and the P-type diffusion region 10 by the same ion implantation has been described, but they may be formed by separate ion implantation. In particular, by adjusting the impurity concentration of the P type diffusion region 10, the reverse current voltage characteristic of the diode 12 shown in FIG. 2 can be set to a desired characteristic. After the ion implantation, the insulating film 14 is removed by etch etching using, for example, hydrofluoric acid.

  Next, in the step of FIG. 3C, the insulating film 14 is formed in the same manner as the step shown in FIG. N-type impurities 16 are ion-implanted using the insulating film 14 as a mask. Thereby, the source region 4 and the N type diffusion region 11 are formed. Nitrogen can be used as the N-type impurity 16. At this time, by performing ion implantation while the substrate temperature is heated to about 600 ° C., it is possible to suppress the occurrence of crystal defects in the implanted region. In the first embodiment, the method of forming the source region 4 and the N-type diffusion region 11 by the same ion implantation has been described, but they may be formed by separate ion implantation. In particular, by adjusting the impurity concentration of the N-type diffusion region 11, the reverse current-voltage characteristics of the diode 12 shown in FIG. 2 can be set to desired characteristics. After the ion implantation, the insulating film 14 is removed by etch etching using, for example, hydrofluoric acid.

  Thereafter, the impurity ion-implanted in the process shown in FIGS. 3-B and C is activated by heat treatment. A temperature of about 1700 ° C. can be used as the heat treatment temperature. Argon or nitrogen can be suitably used as the heat treatment atmosphere.

  Next, in the step shown in FIG. 3D, the gate insulating film 5 is deposited, for example, about 1000 mm. A silicon oxide film is preferably used as the gate insulating film 5, and a thermal oxidation method, a thermal CVD method, a plasma CVD method, a sputtering method, or the like is used as a deposition method. Subsequently, the gate insulating film 5 is patterned and selectively removed by wet etching or dry etching using a resist as a mask, and a contact hole is formed on the N-type diffusion region 11.

  Next, in the step shown in FIG. 3E, the gate electrode 6 is formed. As the gate electrode 6, polycrystalline silicon into which impurities are introduced can be suitably used, and a general low-pressure CVD method can be used as a deposition method. At this time, the gate electrode 6 is in ohmic contact with the diffusion region 11 by keeping the impurity concentration on the surface of the diffusion region 11 high. A resist pattern is formed on the polycrystalline silicon deposited and formed on the entire surface, and the polycrystalline silicon is patterned by using, for example, dry etching with this register pattern as a mask. As a result, the polycrystalline silicon is selectively removed, and the gate electrode 6 that also functions as the gate electrode 6 of the transistor and the cathode electrode of the diode 12 is formed.

  Finally, in the process of FIG. 3F, an interlayer insulating film 8 is deposited. A silicon oxide film is preferably used as the interlayer insulating film 8, and a thermal CVD method, a plasma CVD method, a sputtering method, or the like is used as a deposition method. A resist pattern is formed on the interlayer insulating film 8, and the interlayer insulating film 8 is selectively removed using the resist pattern as a mask to form a contact hole. A source electrode 7 is formed in the contact hole. As the source electrode 7, a metal electrode in which titanium and aluminum are laminated can be used. Thereafter, drain electrode 9 is formed on the back surface of silicon carbide substrate 1 to complete the semiconductor device shown in FIG.

  In FIG. 1, the P-type diffusion region 10 and the well region 3 are formed to the same depth, but the reverse current-voltage characteristics of the diode 12 shown in FIG. 2 are set to desired characteristics. Therefore, the junction depth and impurity concentration of the diffusion region 10 can be set independently of the well region 3.

  In FIG. 1, the N-type diffusion region 11 and the source region 4 are formed with the same depth, but the reverse current-voltage characteristic of the diode 12 shown in FIG. 2 is set to a desired characteristic. Therefore, the junction depth and impurity concentration of the diffusion region 11 can be adjusted independently of the source region 4.

  As described above, in the first embodiment, as the temperature of silicon carbide substrate 1 rises, the gate voltage is lowered by the function of diode 12 and the transistor is turned off. That is, the reverse current of the diode 12 when the allowable maximum operating temperature of the transistor is exceeded is set to be larger than the upper limit gate upper limit current that can be supplied to the gate electrode 6 by the gate drive circuit. Thereby, since the temperature of the transistor is lowered, the transistor can be controlled so as not to exceed a predetermined allowable maximum temperature.

  By adopting the configuration shown in FIG. 1, it is not necessary to connect the semiconductor chip and the temperature measurement circuit as compared with the conventional case, and a connection pad for connecting the semiconductor chip and the temperature measurement circuit on the semiconductor chip becomes unnecessary. Therefore, the area of the portion where the connection pad is formed can be reduced. As a result, the chip area can be reduced and the size of the semiconductor device can be reduced. Furthermore, a temperature measurement circuit is not required, and a low-cost semiconductor device can be provided.

(Embodiment 2)
FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 2 of the present invention.

  The second embodiment is different from the first embodiment in that the P-type diffusion region 10 is ohmically connected to the source electrode 7 through the well region 3 as shown in FIG. With this configuration, the reverse current generated in the diode 12 flows to the source electrode 7. Therefore, it is not necessary to consider the forward voltage drop of the diode 13 with respect to the reverse current voltage characteristic of the diode 12, and the chip temperature can be controlled more stably than in the first embodiment. Further, the voltage applied to the diode 12 substantially matches the gate-source voltage regardless of the drain potential. Therefore, the on / off state of the transistor can be directly controlled by the voltage applied to the diode 12, and the temperature can be controlled more stably.

  Since the basic operation in the configuration shown in FIG. 4 is the same as that of the first embodiment except that the reverse current of the diode 12 flows to the source electrode 7, the description thereof is omitted.

  The manufacturing method of the semiconductor device shown in FIG. 4 is substantially the same except that the mask pattern of the well region 3 and the P-type diffusion region 10 of the manufacturing method described in the first embodiment is changed. Omitted.

  In FIG. 4, the P-type diffusion region 10 and the well region 3 are formed to the same depth, but the reverse current-voltage characteristic of the diode 12 shown in FIG. 2 is set to a desired characteristic. Therefore, the junction depth and impurity concentration of the diffusion region 10 can be set independently of the well region 3.

  In FIG. 4, the N-type diffusion region 11 and the source region 4 are formed with the same depth, but the reverse current-voltage characteristic of the diode 12 shown in FIG. 2 is set to a desired characteristic. Therefore, the junction depth and impurity concentration of the diffusion region 11 can be adjusted independently of the source region 4.

  As described above, in the second embodiment, in addition to the effect obtained in the first embodiment, since the reverse current of the diode 12 flows to the source, the voltage applied to the diode 12 and the gate-source The voltages are almost the same. Thereby, the on / off state of the transistor can be directly controlled, and the temperature can be controlled more stably.

(Embodiment 3)
FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 3 of the present invention.

In this embodiment 3, the previous embodiment 2 differs from the silicon carbide substrate of the P ⁺ type instead of the silicon carbide substrate 1 a connected substrate to the drain electrode 9 of the N ⁺ -type, as shown in FIG. 5 18 This is a so-called IGBT (Insulated Gate Bipolar Transistor) structure. In the third embodiment, portions corresponding to the emitter and collector of the IGBT are referred to as a source and a drain, respectively.

  The basic operation in the configuration shown in FIG. 5 is the same as that in the second embodiment, and a description thereof will be omitted.

The semiconductor device manufacturing method shown in FIG. 5 is different from the manufacturing method described in the first embodiment in that N ⁺ type silicon carbide substrate 1 is changed to P ⁺ type silicon carbide substrate 18, well region 3 and diffusion. Since it is almost the same except that the mask pattern of the region 10 is changed, the description thereof is omitted.

  In FIG. 5, the P-type diffusion region 10 and the well region 3 are formed to the same depth, but the reverse current-voltage characteristics of the diode 12 shown in FIG. 2 are set to desired characteristics. Therefore, the junction depth and impurity concentration of the diffusion region 10 can be set independently of the well region 3.

  In FIG. 5, the N-type diffusion region 11 and the source region 4 are formed with the same depth, but the reverse current-voltage characteristic of the diode 12 shown in FIG. 2 is set to a desired characteristic. Therefore, the junction depth and impurity concentration of the diffusion region 11 can be adjusted independently of the source region 4.

In the third embodiment, the P ⁺ type silicon carbide substrate 18 has been described. However, an N type silicon carbide substrate is used and a P ⁺ type diffusion region is formed on the N type silicon carbide substrate. A similar structure can be obtained.

As described above, in the third embodiment, in addition to the effects obtained in the second embodiment, conduction is performed by holes injected from the P ⁺ type silicon carbide substrate 18 into the N ⁻ type drift region 2. Since the IGBT structure undergoes degree modulation, the resistance of the drift region 2 can be reduced. Thereby, a low-loss semiconductor device can be provided.

(Embodiment 4)
FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 4 of the present invention.

  In the fourth embodiment, the difference from the first embodiment is that the N-type diffusion region 11 is not formed in the P-type diffusion region 10 as shown in FIG. The gate electrode 6 is directly joined to the diffusion region 10. Thus, the diode 12 is formed of a Schottky diode in which the P-type diffusion region 10 and the gate electrode 6 are Schottky junctions.

  FIG. 7 shows the reverse current-voltage characteristics of the Schottky diode. In the current-voltage characteristics of the Schottky diode, the rate of change of the reverse voltage with respect to the reverse current is generally larger than that of the PN junction type diode shown in FIG. That is, in the PN diode, the reverse voltage of the diode changes abruptly even when the reverse current slightly rises due to the temperature rise. On the other hand, in the Schottky diode, the change in the reverse voltage is gradual with respect to the increase in the reverse current. Therefore, by setting the characteristics of the diode 12 for controlling on / off of the transistor to the characteristics shown in FIG. 7, the temperature can be controlled more stably than in the first embodiment.

  As the gate electrode 6, a single metal such as titanium, aluminum, or molybdenum, a silicide such as titanium silicide or nickel silicide, or a laminated structure metal such as upper layer aluminum with lower titanium can be used. The reverse current-voltage characteristics of the diode 12 are determined by the impurity concentration of the P-type diffusion region 10 and the type of metal bonded to the diffusion region 10. Therefore, a desired reverse current voltage characteristic as shown in FIG. 7 can be obtained by appropriately selecting the impurity concentration of the diffusion region 10 and the metal bonded to the diffusion region 10.

  The basic operation in the configuration shown in FIG. 6 is the same as that of the first embodiment except that the reverse current-voltage characteristics of the diode 12 are different from those of the first embodiment, and the description thereof is omitted.

  The semiconductor device manufacturing method shown in FIG. 6 is different from the manufacturing method described in the first embodiment so that the N-type diffusion region 11 is not formed by changing the mask pattern in the step shown in FIG. This is substantially the same except that the material of the gate electrode 6 is changed, and a description thereof will be omitted.

  In FIG. 6, the P-type diffusion region 10 and the well region 3 are formed to the same depth, but the reverse current-voltage characteristic of the diode 12 shown in FIG. 7 is set to a desired characteristic. Therefore, the junction depth and impurity concentration of the diffusion region 10 can be set independently of the well region 3.

  As described above, in the fourth embodiment, in addition to the effect obtained in the first embodiment, the diode 12 is a Schottky diode, so that the reverse voltage changes with respect to the increase in the reverse current. It can be relaxed. Thereby, the chip temperature can be controlled stably.

(Embodiment 5)
FIG. 8 is a cross-sectional view showing the configuration of the semiconductor device according to the fifth embodiment.

  The fifth embodiment is different from the fourth embodiment in that the cathode 17 of the Schottky diode 12 is formed of a different kind of material from the gate electrode 6 in the region where the channel of the transistor is formed. This is the point. The cathode 17 is joined to and electrically connected to the gate electrode 6. In the fifth embodiment, the gate electrode 6 is assumed to be polycrystalline silicon, and the cathode 17 of the diode 12 is assumed to be a metal.

  The cathode 17 of the diode 12 can be made of a single metal such as titanium, aluminum, or molybdenum, a silicide such as titanium silicide or nickel silicide, or a laminated metal such as a lower layer titanium such as upper layer aluminum. On the other hand, polycrystalline silicon is used for the gate electrode 6 where the inversion layer is formed in the channel portion of the transistor. Therefore, the fifth embodiment can provide a semiconductor device having a low on-resistance and a low loss without the possibility of carrier mobility deterioration due to the diffusion of metal atoms into the channel portion as compared with the fourth embodiment. .

  The characteristics of the diode 12 are the same as those in the fourth embodiment.

  In FIG. 8, as an example, a portion where the channel of the transistor is formed and the diode 12 are formed in the same section, but they may be formed in different sections in the depth direction.

  Next, a method for manufacturing the semiconductor device shown in FIG. 8 will be described with reference to FIGS.

First, in the step shown in FIG. 9A, a drift region 2 made of an N ⁻ type silicon carbide epitaxial layer is formed on an N ⁺ type silicon carbide substrate 1. There are several polytypes (crystal polymorphs) in silicon carbide, but here it will be described as representative 4H. Silicon carbide substrate 1 has a thickness of about several tens to several hundreds of μm. The drift region 2 has, for example, an impurity concentration of 10 ¹⁴ to
The film is formed with a thickness of 10 ¹⁸ cm ⁻³ and a thickness of several μm to several tens of μm.

  Next, in the step shown in FIG. 9B, the insulating film 14 is deposited on the drift region 2. A silicon oxide film can be used as the insulating film 14, and a thermal CVD method or a plasma CVD method can be used as a deposition method.

  Subsequently, a resist (not shown) formed on the insulating film 14 is patterned. As a patterning method, a general photolithography method can be used. The insulating film 14 is selectively removed by etching using the patterned resist as a mask. As an etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used.

  Subsequently, the resist is removed with oxygen plasma or sulfuric acid. Using the insulating film 14 as a mask, a P-type impurity 15 is selectively ion-implanted to form the well region 3 and the P-type diffusion region 10. As the P-type impurity 15, aluminum or boron can be used. At this time, by performing ion implantation while the substrate temperature is heated to about 600 ° C., it is possible to suppress the occurrence of crystal defects in the implanted region. In the fifth embodiment, the method of forming the well region 3 and the P-type diffusion region 10 by the same ion implantation has been described, but they may be formed by separate ion implantation. In particular, by adjusting the impurity concentration of the P-type diffusion region 10, the reverse current voltage characteristics of the diode 12 shown in FIG. 7 can be set to desired characteristics. After the ion implantation, the insulating film 14 is removed by etch etching using, for example, hydrofluoric acid.

  Next, in the process of FIG. 9C, the insulating film 14 is formed in the same manner as the process shown in FIG. 9B. Using this insulating film 14 as a mask, an N-type impurity 16 is ion-implanted to form the source region 4. Nitrogen can be used as the N-type impurity 16. At this time, by performing ion implantation while the substrate temperature is heated to about 600 ° C., it is possible to suppress the occurrence of crystal defects in the implanted region. After the ion implantation, the insulating film 14 is removed by etch etching using, for example, hydrofluoric acid.

  Thereafter, the impurities implanted in the step shown in FIGS. 9B and C are activated by heat treatment. A temperature of about 1700 ° C. can be used as the heat treatment temperature. Argon or nitrogen can be suitably used as the heat treatment atmosphere.

  Next, in the process shown in FIG. 9-D, the gate insulating film 5 is deposited, for example, about 1000 mm. A silicon oxide film is preferably used as the gate insulating film 5, and a thermal oxidation method, a thermal CVD method, a plasma CVD method, a sputtering method, or the like is used as a deposition method.

  Next, in the step shown in FIG. 9E, the gate electrode 6 is formed. As the gate electrode 6, polycrystalline silicon into which impurities are introduced can be suitably used, and a general low-pressure CVD method can be used as a deposition method. A resist pattern is formed on the polycrystalline silicon deposited and formed on the entire surface, and the polycrystalline silicon is patterned by using, for example, dry etching with this register pattern as a mask. Thereby, the polycrystalline silicon is selectively removed, and the gate electrode 6 of the transistor is formed.

  Finally, in the process of FIG. 9-F, an interlayer insulating film 8 is deposited. A silicon oxide film is preferably used as the interlayer insulating film 8, and a thermal CVD method, a plasma CVD method, a sputtering method, or the like is used as a deposition method. Thereafter, a resist pattern in which a region for forming the cathode 17 of the diode 12 is opened is formed on the interlayer insulating film 8. Using this resist pattern as a mask, interlayer insulating film 8, gate electrode 6 and gate insulating film 5 are selectively removed to form a contact hole reaching diffusion region 10.

  Subsequently, after forming a metal constituting the cathode 17 by a CVD method or the like, a resist pattern is formed thereon. Using this resist pattern as a mask, the metal is selectively removed to form a cathode 17 in the contact hole.

  Subsequently, a resist pattern is formed on the interlayer insulating film 8 and the cathode 17, and the interlayer insulating film 8 is selectively removed using the resist pattern as a mask to form a contact hole. A source electrode 7 is formed in the contact hole. As the source electrode 7, a metal electrode in which titanium and aluminum are laminated can be used. Thereafter, drain electrode 9 is formed on the back surface of silicon carbide substrate 1 to complete the semiconductor device shown in FIG.

  In FIG. 8, the P-type diffusion region 10 and the well region 3 are formed to the same depth, but the reverse current-voltage characteristic of the diode 12 shown in FIG. 7 is set to a desired characteristic. Therefore, the junction depth and impurity concentration of the diffusion region 10 can be set independently of the well region 3.

  As described above, in the fifth embodiment, in addition to the effect obtained in the fourth embodiment, since polycrystalline silicon is used for the gate electrode 6 of the transistor, the diffusion of metal atoms into the channel portion is performed. There is no risk of carrier mobility degradation. Thereby, a low on-resistance and low-loss semiconductor device can be provided.

(Embodiment 6)
FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 6 of the present invention.

  The sixth embodiment is different from the fourth embodiment in that the P-type diffusion region 10 is ohmically connected to the source electrode 7 through the well region 3 as shown in FIG. With this configuration, the reverse current generated in the diode 12 flows to the source electrode 7. Therefore, it is not necessary to consider the forward voltage drop of the diode 13 shown in the previous embodiment 4 with respect to the reverse current voltage characteristics of the diode 12, and the chip temperature can be controlled more stably than in the previous embodiment 4. can do. Further, the voltage applied to the diode 12 substantially matches the gate-source voltage regardless of the drain potential. Therefore, the on / off state of the transistor can be directly controlled by the voltage applied to the diode 12, and the temperature can be controlled more stably.

  Since the basic operation in the configuration shown in FIG. 10 is the same as that of the fourth embodiment except that the reverse current of the diode 12 flows to the source electrode 7, the description thereof is omitted.

  The semiconductor device manufacturing method shown in FIG. 10 is substantially the same except that the mask pattern of the well region 3 and the P-type diffusion region 10 of the manufacturing method described in the fourth embodiment is changed. Omitted.

  In FIG. 10, the P-type diffusion region 10 and the well region 3 are formed to the same depth, but the reverse current-voltage characteristics of the diode 12 shown in FIG. 7 are set to desired characteristics. Therefore, the junction depth and impurity concentration of the diffusion region 10 can be set independently of the well region 3.

  As described above, in the sixth embodiment, in addition to the effect obtained in the fourth embodiment, since the reverse current of the diode 12 flows to the source, the voltage applied to the diode 12 and the gate-source The voltages are almost the same. Thereby, the on / off state of the transistor can be directly controlled, and the temperature can be controlled more stably.

(Embodiment 7)
FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 7 of the present invention.

In this embodiment 7, the previous embodiment 6 differs from the silicon carbide substrate of P ⁺ -type instead the connected substrate to the drain electrode 9 in the silicon carbide substrate 1 of the N ⁺ -type, as shown in FIG. 11 18 This is a so-called IGBT structure. In the seventh embodiment, portions corresponding to the emitter and collector of the IGBT are called a source and a drain, respectively.

  Since the basic operation in the configuration shown in FIG. 11 is the same as that of the previous embodiment 6, the description thereof is omitted.

The semiconductor device manufacturing method shown in FIG. 11 is different from the manufacturing method described in the fourth embodiment in that N ⁺ type silicon carbide substrate 1 is changed to P ⁺ type silicon carbide substrate 18, well region 3 and diffusion. Since it is almost the same except that the mask pattern of the region 10 is changed, the description thereof is omitted.

  In FIG. 11, the P-type diffusion region 10 and the well region 3 are formed to the same depth, but the reverse current-voltage characteristics of the diode 12 shown in FIG. 7 are set to desired characteristics. Therefore, the junction depth and impurity concentration of the diffusion region 10 can be set independently of the well region 3.

In the seventh embodiment, the P ⁺ type silicon carbide substrate 18 has been described. However, an N type silicon carbide substrate is used, and a P ⁺ type diffusion region is formed on the back surface of the N type silicon carbide substrate. A similar structure can be obtained by the method.

As described above, in the seventh embodiment, in addition to the effects obtained in the sixth embodiment, conduction is performed by holes injected from the P ⁺ type silicon carbide substrate 18 into the N ⁻ type drift region 2. Since the IGBT structure undergoes degree modulation, the resistance of the drift region 2 can be reduced. Thereby, a low-loss semiconductor device can be provided.

(Embodiment 8)
FIG. 12 is a cross-sectional view showing a configuration of the semiconductor device according to the present embodiment.

  This embodiment 8 is different from the previous embodiment 4 in that the gate electrode 6 is made of polycrystalline silicon instead of metal. As a result, the diode 12 is formed by heterojunction of the P-type diffusion region 10 and the polycrystalline silicon gate electrode 6. The characteristics of the diode 12 are similar to the current-voltage characteristics shown in FIG.

  The basic operation in the configuration shown in FIG. 12 is the same as that of the first embodiment except that the reverse current-voltage characteristics of the diode 12 are different from those of the first embodiment.

  In FIG. 12, the P-type diffusion region 10 and the well region 3 are formed at the same depth, but the characteristics close to the reverse current voltage characteristics of the diode 12 shown in FIG. 7 are set as desired characteristics. Therefore, the junction depth and impurity concentration of the diffusion region 10 can be set independently of the well region 3.

  The semiconductor device manufacturing method shown in FIG. 12 is different from the manufacturing method described in the first embodiment so that the N-type diffusion region 11 is not formed by changing the mask pattern in the step shown in FIG. This is substantially the same except that the material of the gate electrode 6 is changed, and a description thereof will be omitted.

  As described above, in the eighth embodiment, in addition to the effects obtained in the fourth embodiment, metal atoms are diffused from the gate electrode 6 made of metal as compared with the configuration of the fourth embodiment, so that adjacent channels are formed. There is no possibility of deteriorating the carrier mobility of the part, and a low-loss semiconductor device can be provided. Compared to the configuration of the fifth embodiment, it is not necessary to separately form a contact hole for joining the cathode 17 made of metal to the P-type diffusion region 10. As a result, the number of manufacturing steps can be reduced, and a cheaper semiconductor device can be provided.

  It has been experimentally confirmed that the forward voltage drop and the reverse current voltage characteristic of the diode 12 can be easily adjusted by adjusting the impurity type and concentration of the gate electrode 6 made of polycrystalline silicon. Therefore, the reverse current voltage characteristic of the diode 12 can be set to a desired characteristic. For example, when joining with the P-type diffusion region 10, the forward voltage drop of the diode 12 is smaller when the polysilicon is made P-type than when the polysilicon is made P-type or N-type. The reverse leakage current increases.

  By changing the impurity concentration of the gate electrode 6 on the channel region and the impurity concentration of the gate electrode 6 at the heterojunction part forming the diode 12, the characteristics of the transistor and the diode 12 are set to desired characteristics independently of each other. be able to.

(Embodiment 9)
FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 9 of the present invention.

  This embodiment 9 is different from the previous embodiment 8 in that the P type diffusion region 10 is ohmically connected to the source electrode 7 through the well region 3 as shown in FIG. With this configuration, the reverse current generated in the diode 12 flows to the source electrode 7. Therefore, there is no need to consider the forward voltage drop of the diode 13 shown in the previous embodiment 4 with respect to the reverse current voltage characteristics of the diode 12, and the chip temperature can be controlled more stably than in the previous embodiment 8. can do. Further, the voltage applied to the diode 12 substantially matches the gate-source voltage regardless of the drain potential. Therefore, the on / off state of the transistor can be directly controlled by the voltage applied to the diode 12, and the temperature can be controlled more stably.

  The basic operation in the configuration shown in FIG. 13 is the same as that of the previous embodiment 8 except that the reverse current of the diode 12 flows to the source electrode 7, and the description thereof is omitted.

  The manufacturing method of the semiconductor device shown in FIG. 13 is substantially the same except that the mask pattern of the well region 3 and the P type diffusion region 10 of the manufacturing method described in the previous embodiment 8 is changed. Omitted.

  In FIG. 13, the P-type diffusion region 10 and the well region 3 are formed to the same depth, but the reverse current-voltage characteristics of the diode 12 shown in FIG. 7 are set to desired characteristics. Therefore, the junction depth and impurity concentration of the diffusion region 10 can be set independently of the well region 3.

  As described above, in the ninth embodiment, in addition to the effects obtained in the previous eighth embodiment, the reverse current of the diode 12 flows to the source, so the voltage applied to the diode 12 and the gate-source The voltages are almost the same. Thereby, the on / off state of the transistor can be directly controlled, and the temperature can be controlled more stably.

(Embodiment 10)
FIG. 14 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 10 of the present invention.

In this embodiment 10, the previous embodiment 9 differs, silicon carbide substrate P ⁺ type instead the connected substrate to the drain electrode 9 in the silicon carbide substrate 1 of the N ⁺ -type, as shown in FIG. 14 18 This is a so-called IGBT structure. In the tenth embodiment, portions corresponding to the emitter and collector of the IGBT are called a source and a drain, respectively.

  Since the basic operation in the configuration shown in FIG. 14 is the same as that of the ninth embodiment, the description thereof is omitted.

The semiconductor device manufacturing method shown in FIG. 14 differs from the manufacturing method described in the eighth embodiment in that N ⁺ type silicon carbide substrate 1 is changed to P ⁺ type silicon carbide substrate 18, well region 3 and diffusion. Since it is almost the same except that the mask pattern of the region 10 is changed, the description thereof is omitted.

  In FIG. 14, the P-type diffusion region 10 and the well region 3 are formed to the same depth, but the characteristics close to the reverse current voltage characteristics of the diode 12 shown in FIG. Therefore, the junction depth and impurity concentration of the diffusion region 10 can be set independently of the well region 3.

In the tenth embodiment, the P ⁺ type silicon carbide substrate 18 has been described. However, an N type silicon carbide substrate is used and a P ⁺ type diffusion region is formed on the N type silicon carbide substrate. A similar structure can be obtained.

As described above, in the tenth embodiment, in addition to the effects obtained in the previous ninth embodiment, conduction is performed by holes injected from the P ⁺ type silicon carbide substrate 18 into the N ⁻ type drift region 2. Since the IGBT structure undergoes degree modulation, the resistance of the drift region 2 can be reduced. Thereby, a low-loss semiconductor device can be provided.

  Next, the arrangement in the plane direction of the silicon carbide substrate of the diode 12 described in the first to tenth embodiments will be described. When the silicon carbide substrate is mounted on a metal substrate or the like via solder, heat is diffused laterally in the outer peripheral portion of the silicon carbide substrate plane as compared with the central portion. As a result, the central portion of the silicon carbide substrate plane tends to be the highest temperature. Therefore, by disposing diode 12 at least in the center of the plane of the silicon carbide substrate, it is possible to detect the maximum temperature in the silicon carbide substrate and control to lower the temperature.

  In addition, variations in temperature may occur in the plane of the silicon carbide substrate due to the bias of the drain current. Therefore, by forming a plurality of diodes 12 on the plane of the silicon carbide substrate, the temperature can be controlled to be lowered with respect to the maximum temperature at various locations on the substrate.

  Regarding the cross-sectional structure in the basic structure of the first to tenth embodiments, a termination structure (not shown) such as a guard ring is employed in the outermost peripheral portion of the semiconductor chip in which a plurality of unit cells 101 are connected in parallel. This guard ring is a termination structure that realizes a high breakdown voltage by relaxing electric field concentration in the periphery when the transistor is off, but a general termination structure used in the field of power devices can be applied.

  In the first to tenth embodiments, a so-called vertical MOSFET structure or IGBT structure in which one main surface (front surface) of the substrate is a source (emitter) and the other main surface (back surface) is a drain (collector) has been described. However, a so-called lateral MOSFET structure or IGBT structure in which the drain (collector) is formed on the surface of the substrate may be used.

  In the first to tenth embodiments described above, the semiconductor substrate has been described as silicon carbide. However, other semiconductor substrates such as silicon, gallium arsenide, gallium nitride, and diamond may be used.

DESCRIPTION OF SYMBOLS 1,18 ... Silicon carbide base | substrate 2 ... Drift region 3 ... Well region 4 ... Source region 5 ... Gate insulating film 6 ... Gate electrode 7 ... Source electrode 8 ... Interlayer insulating film 9 ... Drain electrode 10, 11 ... Diffusion region 12, 13 ... Diode 14 ... Insulating film 15, 16 ... Impurity 17 ... Cathode 101 ... Unit cell

Claims (11)

A semiconductor substrate;
A first conductivity type drift region formed on the semiconductor substrate;
A second conductivity type well region formed in the drift region so as to be in contact with the main surface of the drift region;
A first conductivity type source region formed in the well region so as to be in contact with the main surface of the drift region;
A gate electrode formed on the well region sandwiched between the drift region and the source region via a gate insulating film;
A source electrode connected to the well region and the source region;
A transistor comprising a drain electrode connected to the semiconductor substrate;
An anode formed of a semiconductor region of a second conductivity type formed in the drift region;
A cathode composed of a first conductivity type semiconductor region formed in the second conductivity type semiconductor region;
The cathode is configured to be connected to the gate electrode; and
A semiconductor device comprising: A semiconductor substrate;
A first conductivity type drift region formed on the semiconductor substrate;
A second conductivity type well region formed in the drift region so as to be in contact with the main surface of the drift region;
A first conductivity type source region formed in the well region so as to be in contact with the main surface of the drift region;
A gate electrode formed on the well region sandwiched between the drift region and the source region via a gate insulating film;
A source electrode connected to the well region and the source region;
A transistor comprising a drain electrode connected to the semiconductor substrate;
An anode formed of a semiconductor region of a second conductivity type formed in the drift region;
A cathode formed in contact with the semiconductor region of the second conductivity type,
The cathode is a diode formed integrally with the gate electrode;
A semiconductor device comprising: A semiconductor substrate;
A first conductivity type drift region formed on the semiconductor substrate;
A second conductivity type well region formed in the drift region so as to be in contact with the main surface of the drift region;
A first conductivity type source region formed in the well region so as to be in contact with the main surface of the drift region;
A gate electrode formed on the well region sandwiched between the drift region and the source region via a gate insulating film;
A source electrode connected to the well region and the source region;
A transistor comprising a drain electrode connected to the semiconductor substrate;
An anode formed of a semiconductor region of a second conductivity type formed in the drift region;
A cathode formed in contact with the semiconductor region of the second conductivity type,
The cathode is formed of a heterogeneous body with the gate electrode and connected to the gate electrode; and
A semiconductor device comprising: The gate electrode or cathode is made of metal;
The semiconductor device according to claim 2, wherein the diode constitutes a Schottky diode. The gate electrode is formed of polycrystalline silicon;
The semiconductor device according to claim 2, wherein the diode constitutes a heterojunction diode. The semiconductor device according to claim 1, wherein an anode made of a second conductivity type semiconductor region formed in the drift region is ohmically connected to the source electrode. The semiconductor device according to claim 6, wherein the transistor has an IGBT structure. The semiconductor device according to claim 1, wherein at least one of the diodes is formed at a central portion of the semiconductor substrate plane. The semiconductor device according to claim 1, wherein a plurality of the diodes are formed on the semiconductor substrate. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide. The semiconductor device according to any one of claims 1 to 10,
A gate driving circuit for controlling application of a voltage for switching control of the transistor to the gate electrode;
The reverse current of the diode when the maximum allowable operating temperature of the transistor is exceeded is set to be larger than the upper limit gate upper limit current that the gate driving circuit can supply to the gate electrode. Semiconductor device.

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