JP6008145B2 - Power semiconductor device - Google Patents

Description

  The present invention relates to a power semiconductor device such as a silicon carbide semiconductor device.

  A power semiconductor device including a power vertical metal-oxide-semiconductor field-effect transistor (MOSFET) and a diode described in Patent Document 1 are shown in FIGS. 1 and 2 of the same document. As shown in FIG. 2, diodes are arranged in at least one row in the peripheral portion of the cell region of the MOSFET, that is, in the region adjacent to the gate pad portion. Each of these diodes is injected during forward bias into the N-type semiconductor layer on the drain side from the P well and P base shown in FIG. 2 when the MOSFET switches from the on state to the off state. Absorbs holes. For this reason, the above-mentioned structure of the same document can prevent the parasitic transistor shown in FIG. 3 of the same document from being turned on when the MOSFET is switched from the forward bias to the reverse bias.

  Here, in the structure of the same document, as shown in FIG. 2, the P base, which is the P well of the MOSFET, is electrically connected to the source electrode through the back gate.

JP-A-5-198816 (FIGS. 1 to 3)

  The problem to be solved by the present invention will be described below with reference to FIG.

When the MOSFET of the power semiconductor device described in Patent Document 1 is switched from the on state to the off state, the drain voltage of the MOSFET, that is, the voltage of the drain electrode rises rapidly, and in some cases reaches about several hundred volts. May reach. Due to the rise of the drain voltage, displacement currents are generated on the drain electrode side and the source electrode side via the depletion layer capacitance formed between the P well and the N ⁻ drain layer in the off state. This displacement current is generated not only in the P well of the MOSFET but also in the diode if the P-type region is provided in the N ⁻ drain layer like the P well or the P well.

  The displacement current generated in this way flows to the drain electrode as it is generated on the drain electrode side, but the displacement current generated on the source electrode side flows to the source electrode via the P-well or P-type region. .

  In the case of a power semiconductor device as shown in Patent Document 1, the source electrode and the field plate are electrically connected as described in the description of the conventional example. In the cross section shown, the displacement current that has flowed into the P well under the gate pad flows in the P well under the gate pad from the MOSFET cell direction toward the contact hole connected to the field plate, and passes through the field plate. Flows into the source electrode.

  Here, the area of the P well under the gate pad is very large with respect to the area of the P well of the MOSFET cell and the P well of the diode cell. Since the well itself and the contact hole have a resistance with a certain large resistance value, a voltage of a value that cannot be ignored is generated in the P well. As a result, at a position in the P well where the distance in the plane direction is large from a place (contact hole) where the P well is electrically connected to the source electrode (usually connected to the ground potential) via the field plate. A large potential will be generated.

  This potential increases as the displacement current increases, and increases as the fluctuation dV / dt of the drain voltage V with respect to time t increases.

  In a power semiconductor device including such a MOSFET, the voltage of the gate electrode is changed immediately after switching the MOSFET from the on state to the off state at a location where the gate insulating film of the MOSFET is sandwiched between the P well and the gate electrode. When the voltage is close to 0 V, a high voltage is generated in the P-well as described above, and the gate insulating film may be destroyed by a high electric field due to the high voltage.

  The present invention was made to solve such a problem, and in a power semiconductor device including a MOSFET that switches at high speed, the occurrence of dielectric breakdown between the gate electrode and the source electrode during switching can be suppressed. An object of the present invention is to provide a highly reliable power semiconductor device and a method for manufacturing the same.

A power semiconductor device of the present invention includes a silicon carbide semiconductor substrate, a drift layer formed on a first main surface of the silicon carbide semiconductor substrate, using a silicon carbide material of a first conductivity type, and a surface layer of the drift layer. A plurality of first conductivity type first well regions formed in part, a first conductivity type source region formed in a part of each surface layer of the plurality of first well regions, and a surface layer of the drift layer, The second conductivity type second well region formed in a region different from the first well region, the plurality of first well regions, the source region, and the first well region side on the second well region. Formed on the side opposite to the first well region side above the second well region, and formed on the field insulating film and the gate insulating film. Formed on the gate electrode and the first well region The source contact hole, the source pad that electrically connects the first well region and the second well region via the well contact hole formed on the second well region, and the gate electrode are electrically connected And a drain electrode provided on the second main surface of the silicon carbide semiconductor substrate, and the closest distance from the position (P) where the distance to the inner well contact hole of the second well region is the longest and distance x _P to the position of the well contact hole (Q), the distance from the position of the well contact hole on a straight line PQ (Q) to the boundary (R) of the gate insulating film and the field insulating film as x _R, d _ox the thickness of the gate insulating film, the time for switching the t from the oN state to the oFF state, the sheet resistance of the R _SH second well region, the epsilon ₀ of the vacuum dielectric constant, the epsilon _S The dielectric constant of the lift layer, q the elementary charge, the effective first conductivity type impurity concentration of the drift of the _{N D layer,} the voltage of the drain electrode of _{V OFF} OFF _state, Ri _{E max} is 10 MV / cm der, the drain time derivative of 10V / nsec and to Rutoki voltage _{V OFF} of the electrodes, characterized by satisfying the predetermined formula relationships.

A power semiconductor device according to the present invention includes a silicon carbide semiconductor substrate, a drift layer formed on the first main surface of the silicon carbide semiconductor substrate, using a silicon carbide material of the first conductivity type, and a drift layer. A plurality of first conductivity type first well regions formed in a part of the surface layer, a first conductivity type source region formed in a part of each surface layer of the plurality of first well regions, and a surface layer of the drift layer The second conductivity type second well region formed in a region different from the first well region, the plurality of first well regions, the source region, and the first well region side on the second well region A gate insulating film formed; a field insulating film formed on a side opposite to the first well region side above the second well region; and having a thickness greater than the gate insulating film; and on the field insulating film and the gate insulating film The formed gate electrode and the first well region The source contact hole formed, the source pad that electrically connects the first well region and the second well region via the well contact hole formed on the second well region, and the gate electrode electrically A connected gate pad and a drain electrode provided on the second main surface of the silicon carbide semiconductor substrate, the second farthest region of the second well region below the field insulating film being the farthest from the first well region. on a straight line connecting the 'position of the well contact hole closest (Q each position of the outer periphery of the second well region (P)'), 'the distance between x _P' P'Q as, well contact hole position ( Q ′) is the distance from the gate insulating film to the boundary (R ′) between the gate insulating film and the field insulating film, x _{R ′} , d _ox is the thickness of the gate insulating film, t is the time for switching from the on state to the off state, R _SH The The sheet resistance of the second well region, epsilon ₀ the dielectric constant of vacuum, epsilon dielectric constant of the _S drift layer, q the elementary charge, the effective first conductivity type impurity concentration of the drift layer N _D, V _OFF to the OFF state the voltage of the drain _{electrode, E max} is 10 MV / cm der is, the voltage _{V OFF} of the drain electrode time derivative of 10V / nsec and to Rutoki, characterized by satisfying the predetermined formula relationships.

A power semiconductor device according to the present invention includes a silicon carbide semiconductor substrate, a drift layer formed on the first main surface of the silicon carbide semiconductor substrate, using a silicon carbide material of the first conductivity type, and a drift layer. A plurality of first conductivity type first well regions formed in a part of the surface layer, a first conductivity type source region formed in a part of each surface layer of the plurality of first well regions, and a surface layer of the drift layer The second conductivity type second well region formed in a region different from the first well region, the plurality of first well regions, the source region, and the first well region side on the second well region A gate insulating film formed; a field insulating film formed on a side opposite to the first well region side above the second well region; and having a thickness greater than the gate insulating film; and on the field insulating film and the gate insulating film The formed gate electrode and the first well region The source contact hole formed, the source pad that electrically connects the first well region and the second well region via the well contact hole formed on the second well region, and the gate electrode electrically A connected gate pad and a drain electrode provided on the second main surface of the silicon carbide semiconductor substrate, the closest from the position (P) where the distance to the inner well contact hole in the second well region is the largest the position of the well contact hole the distance to (Q) as x _P, the position where there is a gate electrode farthest from the position of the well contact hole on the field insulating film on a straight line PQ (Q) (S) and the well the distance between the position of the contact hole (Q) as x _S, the thickness of the field insulating film d _FL, switching time from the oN state to the oFF state to t, The sheet resistance of the _SH second well region, epsilon ₀ the dielectric constant of vacuum, the relative dielectric constant of the drift layer epsilon _S, q the elementary charge, the effective first conductivity type impurity concentration of the drift layer N _D, a V _OFF the drain voltage in the off _{state, E max} is 10 MV / cm der is, the voltage _{V oFF} of the drain electrode time derivative of 10V / nsec and to Rutoki, characterized by satisfying the predetermined formula relationships.

A power semiconductor device according to the present invention includes a silicon carbide semiconductor substrate, a drift layer formed on the first main surface of the silicon carbide semiconductor substrate, using a silicon carbide material of the first conductivity type, and a drift layer. A plurality of first conductivity type first well regions formed in a part of the surface layer, a first conductivity type source region formed in a part of each surface layer of the plurality of first well regions, and a surface layer of the drift layer The second conductivity type second well region formed in a region different from the first well region, the plurality of first well regions, the source region, and the first well region side on the second well region A gate insulating film formed; a field insulating film formed on a side opposite to the first well region side above the second well region; and having a thickness greater than the gate insulating film; and on the field insulating film and the gate insulating film The formed gate electrode and the first well region The source contact hole formed, the source pad that electrically connects the first well region and the second well region via the well contact hole formed on the second well region, and the gate electrode electrically A connected gate pad and a drain electrode provided on the second main surface of the silicon carbide semiconductor substrate, the second farthest region of the second well region below the field insulating film being the farthest from the first well region. The distance between P′Q ′ on the straight line connecting each position (P ′) on the outer periphery of the 2-well region to the position (Q ′) of the nearest well contact hole is x _{P ′,} and the well is formed on the field insulating film. The distance from the contact hole position (Q ′) to the position (S ′) where the gate electrode is located farthest is x _{S ′} , d _FL is the thickness of the field insulating film, and t is turned from the on state to the off state. Switching Time, R _SH is the sheet resistance of the second well region, ε ₀ is the vacuum dielectric constant, ε _S is the relative permittivity of the drift layer, q is the elementary charge, N _D is the effective first conductivity type impurity concentration of the drift layer the _{V oFF} and the drain voltage in the off _{state, E} Ri _max is 10 MV / cm der, the voltage _{V oFF} of the drain electrode time derivative of 10V / nsec and to Rutoki, and satisfy the predetermined formula relationships To do.

  According to the power semiconductor device of the present invention, even when the power semiconductor device is driven at a high speed, the gate insulating film is not applied to the gate insulating film or the field insulating film on the second well region without applying a high strength electric field. A breakdown of the film or the field insulating film can be suppressed, and a more reliable power semiconductor device can be provided.

1 is a plan view schematically showing a power semiconductor device according to a first embodiment of the present invention. 1 is a plan view schematically showing a power semiconductor device according to a first embodiment of the present invention. It is sectional drawing which represents typically the one part cross section of the semiconductor device for electric power in Embodiment 1 of this invention. It is sectional drawing which represents typically the one part cross section of the semiconductor device for electric power in Embodiment 1 of this invention. It is sectional drawing which represents typically a part of power semiconductor device for demonstrating the manufacturing process of the power semiconductor device in Embodiment 1 of this invention. It is sectional drawing which represents typically a part of power semiconductor device for demonstrating the manufacturing process of the power semiconductor device in Embodiment 1 of this invention. It is sectional drawing which represents typically the one part cross section of the semiconductor device for electric power in Embodiment 1 of this invention. 1 is a plan view schematically showing a power semiconductor device according to a first embodiment of the present invention. It is sectional drawing which represents typically the one part cross section of the semiconductor device for electric power in Embodiment 1 of this invention. It is a top view which represents typically the electric power semiconductor device in Embodiment 2 of this invention. It is a top view which represents typically the electric power semiconductor device in Embodiment 2 of this invention. It is sectional drawing which represents typically the one part cross section of the semiconductor device for electric power in Embodiment 2 of this invention.

Embodiment 1 FIG.
In the first embodiment of the present invention, description will be made using a vertical n-type channel silicon carbide MOSFET as a main example of a power semiconductor device. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, the semiconductor conductivity type may be reversed.

  1 is a plan view of a power semiconductor device mainly including a silicon carbide MOSFET, which is a power semiconductor device according to a first embodiment of the present invention, as viewed from above. In FIG. 1, a source pad 10 is provided at the center of the upper surface of the power semiconductor device. A gate pad 11 is provided on one side of the source pad 10 as viewed from above. A gate wiring 12 is provided so as to extend from the gate pad 11 and surround the source pad 10.

  The source pad 10 is electrically connected to the source electrode of the unit cell of the MOSFET provided in a plurality under the source pad 10, and the gate pad 11 and the gate wiring 12 are electrically connected to the gate electrode of the unit cell. And a gate voltage supplied from an external control circuit is applied to the gate electrode.

  FIG. 2 is a plan view of layers below the layers such as the source pad 10 and the gate pad 11 of the power semiconductor device according to the present embodiment shown in FIG. In FIG. 2, a well contact hole 62 is formed in the lower part around the source pad 10 shown in FIG. 1 through an interlayer insulating film (not shown) and a gate insulating film (not shown) thereunder. Has been. A p-type silicon carbide second well region 42 is formed in a layer made of silicon carbide below well contact hole 62. An n-type silicon carbide field stopper region 81 is formed outside the second well region 42 at a predetermined interval.

  In the plan view of FIG. 2, a cell region in which a large number of the unit cells are provided is provided on the inner side surrounded by the well contact hole 62 and the second well region 42. In the cell region, a plurality of source contact holes 61 formed in the interlayer insulating film and a first well region 41 of p-type silicon carbide below each are formed.

  Further, a gate electrode (not shown) is formed on a part of the upper portion of the second well region 42 via a gate insulating film or a field insulating film, and the gate pad 11, the gate wiring 12, the gate electrode, A gate contact hole 64, which is a hole for electrically connecting the two, is formed through the interlayer insulating film.

  3 and 4 are schematic cross-sectional views of the power semiconductor device according to the present embodiment, schematically showing the cross-section of the AA portion and the cross-section of the BB portion of the plan view of FIG.

  3 and 4, drift layer 21 made of n-type silicon carbide is formed on the surface of semiconductor substrate 20 made of n-type and low-resistance silicon carbide. A second well region 42 made of p-type silicon carbide is provided in the surface layer portion of the drift layer 21 at a position substantially corresponding to the region where the gate pad 11 and the gate wiring 12 described in FIG. 2 are provided. ing.

  The second well region is located on both sides of the second well region 42 in FIG. 3 and on the surface layer portion of the drift layer 21 on the right side of the second well region 42 in FIG. 4 (inner side surrounded by the second well region 42 in FIG. 2). A plurality of first well regions 41 made of p-type silicon carbide are provided at least at a predetermined interval from 42. The region where the first well region 41 and the like are formed corresponds to the cell region described with reference to FIG.

  In each surface layer portion of the first well region 41, a source region 80 made of n-type silicon carbide is formed at a position inside the first well region 41 from the outer periphery by a predetermined distance. A low resistance p-type well contact region 46 made of silicon carbide is provided in the inner surface layer portion surrounded by the source region 80 of the first well region 41. A low resistance p-type well contact region 47 made of silicon carbide is provided below the well contact hole 62 in the surface layer portion of the second well region 42.

  An n-type field stopper region 81 made of silicon carbide is formed at a predetermined interval on the surface layer portion of the drift layer 21 on the left side (outside of FIG. 2) of the second well region 42 in FIG. ing.

  A gate insulating film made of silicon dioxide in contact with the drift layer 21 in which the first well region 41, the second well region 42, the source region 80, the well contact regions 46 and 47, and the field stopper region 81 are formed. A field insulating film 31 made of 30 or silicon dioxide is formed. The gate insulating film 30 is formed on the first well region 41 that is a cell region and the upper part of the periphery of the first well region 41 and the upper part of the second well region 42, and the field insulating film 31 is formed on the side of the first well region 41. The upper side of the second well region 42 is formed on the side opposite to the first well region 41 side (inner side of FIG. 3, left side of FIG. 4, outer side of FIG. 2). In the power semiconductor device of the present embodiment, the gate insulating film field insulating film boundary 33, which is the boundary between the gate insulating film 30 and the field insulating film 31, is formed above the second well region 42.

  A gate electrode 50 is formed on part of the gate insulating film 30 and the field insulating film 31 in contact with the gate insulating film 30 and the field insulating film 31. The gate electrode 50 is provided on the gate insulating film 30 on the outer periphery of the first well region 41 and is electrically connected from a portion on the gate insulating film 30 to a portion on the field insulating film 31. The gate electrode 50 is connected to the gate pad 11 or the gate wiring 12 by a gate contact hole 64 formed on the field insulating film 31 through the interlayer insulating film 32 formed on the field insulating film 31. Yes.

  A source contact hole 61 provided through the interlayer insulating film 32 and the gate insulating film 30 is provided above the source region 80 and the well contact region 46 in the first well region 41. In addition, a well contact hole 62 provided through the insulating film including the interlayer insulating film 32 is provided above the well contact region 47 of the second well region 42. The well contact hole 62 is provided through the interlayer insulating film 32 and the gate insulating film 30.

  The first well region 41 and the second well region 42 are electrically connected to each other by the source pad 10 in the source contact hole 61 and the well contact hole 62 with the ohmic electrode 71 interposed therebetween.

  A drain electrode 13 is formed on the back surface side of the semiconductor substrate 20 via a back surface ohmic electrode 72.

  The characteristic dimensions of the power semiconductor device of this embodiment will be described in detail later.

  Next, a method for manufacturing the power semiconductor device of the present embodiment will be described with reference to FIGS. 5 and 6 are cross-sectional views schematically showing a part of the power semiconductor device for explaining the manufacturing process of the power semiconductor device of the present embodiment. , (A) corresponds to the AA cross section of FIG. 2, and (b) corresponds to the cross section of the BB cross section of FIG.

Hereinafter, the manufacturing method of the power semiconductor device of this embodiment will be described in order.
First, 1 × 10 ¹³ cm ⁻³ to 1 × 10 on the surface (first main surface) of the n-type low-resistance silicon carbide semiconductor substrate 20 by chemical vapor deposition (CVD). ^A drift layer 21 made of silicon carbide having an n-type impurity concentration of ¹⁸ cm ⁻³ and a thickness of 4 to 200 μm is epitaxially grown. As the semiconductor substrate 20 of silicon carbide, a substrate whose first principal plane has a (0001) plane and has a 4H polytype and is tilted to 8 ° or less with respect to the c-axis direction is used. The plane orientation, polytype, and inclination angle may be sufficient, or may not be inclined.

  Subsequently, as shown in FIG. 5, a p-type first well region 41, a p-type second well region 42, and an n-type source region 80 are formed at predetermined positions on the surface layer of the drift layer 21 by ion implantation. The n-type field stopper region 81 and the p-type well contact regions 46 and 47 are formed. Al (aluminum) or B (boron) is preferable as the p-type impurity to be ion-implanted, and N (nitrogen) or P (phosphorus) is preferable as the n-type impurity to be ion-implanted. Further, the semiconductor substrate 20 may not be positively heated at the time of ion implantation, or may be heated at 200 to 800 ° C.

It is necessary to set the depth of each of the first well region 41 and the second well region 42 so as not to be deeper than the bottom surface of the drift layer 21 that is an epitaxial growth layer, for example, a value in the range of 0.3 to 2 μm. To do. In addition, the p-type impurity concentration of each of the first well region 41 and the second well region 42 is higher than the impurity concentration of the drift layer 21 and is in the range of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . Set in.

The depth of the source region 80 is set so that its bottom surface does not exceed the bottom surface of the first well region 41, its n-type impurity concentration is higher than the p-type impurity concentration of the first well region 41, and 1 It is set within the range of × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . The field stopper region 81 may be formed under the same conditions as the source region 80.

  However, only in the vicinity of the outermost surface of the drift layer 21, the p-type impurity concentration of each of the first well region 41 and the second well region 42 is set to n of the drift layer 21 in order to increase the conductivity in the channel region of the MOSFET. It may be lower than the type impurity concentration.

  The well contact regions 46 and 47 are provided to obtain good electrical contact between the first well region 41 and the second well region 42 and the source pad 10 with the ohmic electrode 71 interposed therebetween. It is desirable to set the impurity concentration higher than the p-type impurity concentration of the first well region 41 and the second well region 42. Further, when ion-implanting these high-concentration impurities, it is desirable to ion-implant by heating the semiconductor substrate 20 to 150 ° C. or higher in order to reduce the resistance of the well contact regions 46 and 47.

  Subsequently, annealing is performed in an inert gas atmosphere such as argon (Ar) gas or nitrogen gas, or in vacuum, in a temperature range of 1500 to 2200 ° C. and for a time in a range of 0.5 to 60 minutes, and ion implantation is performed. The activated impurities are electrically activated. When performing this annealing, the semiconductor substrate 20 and the film formed thereon may be annealed while being covered with a carbon film. By covering and annealing with the carbon film, it is possible to prevent the occurrence of surface roughness of the silicon carbide caused by residual moisture or residual oxygen in the apparatus during annealing.

  Next, a thermal oxide film is formed by sacrificing the surface of the drift layer 21 ion-implanted as described above, and the thermal oxide film is removed with hydrofluoric acid to thereby form the ion-implanted drift layer 21. The surface alteration layer is removed to expose a clean surface. Subsequently, a silicon dioxide film called a field insulating film 31 having a thickness of about 0.5 to 2 μm is formed in a region other than the position substantially corresponding to the above-described cell region by using a CVD method, a photolithography technique, or the like. At this time, for example, after the field insulating film 31 is formed on the entire surface, the field insulating film 31 at a position substantially corresponding to the cell region may be removed by photolithography, etching, or the like.

  Subsequently, a silicon dioxide film having a thickness smaller than that of the field insulating film 31, for example, about 1/10 of the thickness of the field insulating film 31, using a thermal oxidation method or a deposition method in a region centered on the cell region A gate insulating film 30 is formed.

  The thickness of the gate insulating film 30 may be 30 nm or more and 300 nm or less, and more preferably 50 nm or more and 150 nm or less.

  Subsequently, as shown in a cross-sectional view of FIG. 6, a gate electrode 50 made of a polycrystalline silicon material is formed on the gate insulating film 30 and the field insulating film 31 at a predetermined position by using a CVD method, a photolithography technique, or the like. Form. The polycrystalline silicon used for the gate electrode 50 preferably contains P and B and has a low resistance. P and B may be introduced during the film formation of the polycrystalline silicon, or may be introduced by an ion implantation method after the film formation. The gate electrode 50 may be a multilayer film of polycrystalline silicon and metal or a multilayer film of polycrystalline silicon and metal silicide.

  The outermost end surface of the gate electrode 50 may be disposed on the field insulating film 31. By doing so, it is possible to prevent the quality deterioration of the gate insulating film 30 exposed at the end face due to the over-etching of the end face by the dry etching process.

  Next, an interlayer insulating film 32 composed of a silicon dioxide film is formed on the gate electrode 50 and the like by a deposition method such as a CVD method. Subsequently, the interlayer insulating film 32 is removed from the portion that becomes the source contact hole 61 and the well contact hole 62 by using a photolithography technique and a dry etching technique.

  Subsequently, heat treatment at a temperature of 600 to 1100 ° C. is performed following the formation of a metal film containing Ni as a main component by sputtering or the like, and the metal film containing Ni as a main component reacts with the silicon carbide layer to carbonize. Silicide is formed between the silicon layer and the metal film. Next, the metal film remaining on the interlayer insulating film 32 other than the silicide formed by the reaction is removed by wet etching using one of sulfuric acid, nitric acid, hydrochloric acid, or a mixed solution of these and hydrogen peroxide. .

  The silicide formed in the source contact hole 61 and the well contact hole 62 in this way becomes the ohmic electrode 71 shown in FIGS. 3 and 4, and the n-type silicon carbide region such as the source region 80 and the first well. Ohmic connection is made to both p-type silicon carbide regions such as region 41.

  Further, the interlayer insulating film 32 at a location to become the gate contact hole 64 is removed by using a photolithography technique and a dry etching technique. Subsequently, a back surface ohmic electrode 72 is formed on the back side of the semiconductor substrate 20 by forming a metal mainly composed of Ni on the back surface (second main surface) of the semiconductor substrate 20 and performing a heat treatment.

  Thereafter, a wiring metal such as Al is formed on the surface of the semiconductor substrate 20 that has been processed so far by sputtering or vapor deposition, and processed into a predetermined shape by photolithography, whereby the source pad 10, the gate pad 11 and the gate are formed. The wiring 12 is formed. Further, the drain electrode 13 is formed by forming a metal film on the surface of the back ohmic electrode 72 on the back surface of the substrate, and the power semiconductor device whose cross-sectional views are shown in FIGS. 3 and 4 is completed.

Next, the operation of the power semiconductor device of the present embodiment will be described.
First, the configuration of the power semiconductor device of the present embodiment as viewed from an electric circuit will be described. In the power semiconductor device according to the present embodiment, the second conductivity type (p-type in this embodiment) second well region 42 connected to the source pad 10 by the well contact hole 62, the semiconductor substrate 20, and the back surface ohmic. A diode is formed between the first conductivity type (n-type in this embodiment) drift layer 21 connected to the drain electrode 13 via the electrode 72. In addition, the region (channel region) in contact with the gate insulating film 30 in the second conductivity type first well region 41 between the first conductivity type source region 80 and the first conductivity type drift layer 21 is electrically connected. It can be controlled by the voltage of the gate electrode 50 on the gate insulating film 30, and these constitute a vertical MOSFET. In the power semiconductor device of the present embodiment, the source and gate of a MOSFET (n-type MOSFET in this embodiment) are the second conductivity type electrodes of the pn diode, and the drain of the MOSFET is the pn diode first. Each of the electrodes is integrated with one conductivity type electrode, and a diode is connected in parallel between the source and drain of the MOSFET.

  Next, the operation will be described with reference to FIG. FIGS. 7A and 7B are schematic cross-sectional views of the power semiconductor device according to the present embodiment corresponding to FIGS. 3 and 4, respectively, and arrows in the drawing indicate current flows.

  In the power semiconductor device of this embodiment, when the voltage applied to the gate of the MOSFET (the gate pad 11 in this embodiment) is changed so that the MOSFET switches from the on state to the off state, The voltage of the drain (in this embodiment, the drain electrode 13) rises rapidly and changes from approximately 0V to several hundred volts. Then, as shown in FIG. 7, the displacement current is p-type via the parasitic capacitance generated between the p-type first well region 41, the second well region 42, and the n-type drift layer 21. It flows in both n-type regions. In the p-type region, as schematically shown by the solid line arrows in FIG. 7, a displacement current flows from the p-type first well region 41 and the second well region 42 to the source pad 10 through the ohmic electrode 71. Flowing. In the n-type region, a displacement current flows from the n-type drift layer 21 to the drain electrode 13 through the semiconductor substrate 20 and the back surface ohmic electrode 72 as schematically shown by the broken-line arrows in FIG.

  These displacement currents generate a voltage determined by the resistance value of the region where the displacement current flows and the value of the displacement current. However, since the area of the first well region 41 is not large, the resistance value of the region is not large. The generated voltage remains at a certain value. On the other hand, since the second well region 42 has a large area, a large current corresponding to the area flows. Thus, when a displacement current having a large current value flows from the second well region 42 to the source pad 10 via the ohmic electrode 71 of the well contact region 48 and the well contact hole 62, the contact resistance in the vicinity of the contact hole is reduced. Since the resistance value of the current path including it is relatively large, the voltage generated in the current path becomes a large value. The voltage generated in this current path increases as the fluctuation dV / dt of the drain voltage V with respect to time t increases.

  When the gate electrode 50 is formed on the portion (well region) where such a large voltage is generated via the gate insulating film 30 and the field insulating film 31, the MOSFET is turned off and the voltage becomes approximately 0V. In some cases, a high electric field is applied to the insulating film between the gate electrode 50 and a portion (well region) where a large voltage is generated, causing the insulating film to break down.

  In the power semiconductor device according to the present embodiment of the present invention, by controlling the voltage generated at a location (well region) facing the gate electrode 50 within a predetermined value, the dielectric breakdown of the insulating film is suppressed. it can.

  Hereinafter, a voltage generated at a location (well region) facing the gate electrode 50 and an electric field applied to the gate insulating film 30 and the field insulating film 31 based on the voltage are obtained.

In the pn junction formed between the n-type drift layer 21 and the p-type second well region 42 of the power semiconductor device of the present embodiment of the present invention, there is a gap between the source pad 10 and the drain electrode 13. In some cases, a depletion layer is formed by this voltage, and the charge density of this depletion layer is determined by the potential difference between the source pad 10 and the drain electrode 13. Since the voltage of the source pad 10 is usually 0 V, the voltage of the drain electrode 13 (drain voltage V _D ) becomes the potential difference between the source pad 10 and the drain electrode 13 as it is.

When a positive voltage is applied to the drain electrode 13 with respect to the source pad 10 to form a depletion layer at the pn junction between the drift layer 21 and the second well region 42, the n-type drift layer 21 and the p-type drift layer 21 are formed. absolute value Q _D of the depletion charge density generated respectively in the second well region 42 is given by the following equation.

Here, epsilon ₀ is the vacuum dielectric constant, .epsilon.s dielectric constant of the drift layer 21, q is the elementary charge, N _D is when the effective first conductivity type impurity concentration (drift layer 21 of the drift layer 21 is n-type the amount obtained by subtracting the acceptor concentration from the donor concentration), [Phi _bi is the diffusion potential of the pn junction, the impurity concentration N _a of the second well region 42 is made sufficiently higher than the impurity concentration N _D of the drift layer 21.

When the MOSFET which is the power semiconductor device of the present embodiment is switched from the on state to the off state, the voltage of the drain electrode 13 (drain voltage V _D ) changes from the drain voltage V _{ON in the} on state to the drain voltage V _OFF in the off state. increase also increases the depletion charge density Q _D accordingly. Assuming that the time during which the power semiconductor device is switched from the on state to the off state is t, the time change rate dQ _D / dt of the depletion charge density during the switching from the on state to the off state is expressed by the following equation.

Here, while the [Phi _bi and _{V ON} is at most a few _V, since _{V OFF} is several hundreds V or _more, V _OFF >> V _ON, holds the relationship of _{V OFF} »Fai _bi, number 2 the following It can be approximated with high accuracy like

  In order to compensate for the change in the depletion charge density, holes having the same charge density are generated in the second well region 42, and the displacement current is transferred to the source pad 10 via the ohmic electrode 71 closest to the generated position. Flowing. In this current path, holes are generated in the second well region 42 as shown in FIG. 7, and move toward the same ohmic electrode 71 (well contact hole 62).

Here, in the second well region 42, the position in the wafer plane where the distance to the ohmic electrode 71 (well contact hole 62) is the largest is P, and the ohmic electrode 71 (well contact hole 62) closest to the position P. Let Q be the position in the wafer plane, and determine the current and potential generated between the straight lines PQ. To be precise, the point Q is a position where the distance to the position P is the shortest in the ohmic electrode 71 (well contact hole 62) formed with a size of about several μm on the wafer plane. Also, the position Q x = 0, defines the parallel x-axis position P in a current path to x = _{x P.}

The current magnitude I _H (x ₁ ) at the position x ₁ on the straight line PQ (where 0 ≦ x ₁ ≦ x _P ) is the amount of holes generated per hour in the range of x ₁ ≦ x ≦ x _P. Since they are equal, they can be expressed by the following equation.

The potential difference between the position of the coordinate x = 0 and the position of the coordinate x = x ₁ is the current magnitude I _H (x ₁ ) and the sheet resistance R _SH of the second well region 42 in the range of 0 ≦ x ≦ x _1. It can be obtained by integrating the product of. Since the ohmic electrode 71 (well contact hole 62) at the position Q is connected to the source pad 10, the voltage at the coordinate x = 0 is 0V.
Therefore, the potential V _H (x ₂ ) at the coordinate x = x ₂ can be expressed by the following equation.

Here, since x ₂ is an arbitrary value satisfying 0 ≦ x ₂ ≦ x _P , the voltage V _H (x) at a position away from the position Q by the distance x on the straight line PQ is expressed by the following formula 6. be able to.

While the MOSFET changes from the on state to the off state, and the voltage V _D of the drain electrode 21 changes from V _on (approximately 0 V) to V _off during time t, the point on the straight line PQ of the second well region 42 Then, the voltage given by Equation 6 is generated. Here, when the gate electrode 50 is present on the second well region 42, a voltage given by V _H (x) is applied to the gate insulating film 30 and the field insulating film 31 sandwiched therebetween. This voltage increases as x increases, that is, as the distance from the position Q increases.

  Next, the electric field applied to the gate insulating film 30 and the electric field applied to the field insulating film 31 are calculated.

  First, the electric field applied to the gate insulating film 30 is calculated.

On the straight line PQ, the region where the gate electrode 50 is located through the field insulating film 31 whose film thickness is d _FL when viewed from the position Q is the region where the gate electrode 50 is located via the gate insulating film 30 whose film thickness is d _OX. Since the field insulating film 31 is farther away, a higher voltage than the gate insulating film 30 is applied to the field insulating film 31, but the field insulating film 31 can be designed to be thicker than the gate insulating film 30. The applied electric field strength can be reduced. On the other hand, since it is difficult to increase the thickness of the gate insulating film 30 for the purpose of reducing the on-resistance, a high electric field is likely to be generated. That is, the position where the electric field having the highest electric field strength is generated in the gate insulating film 30 on the straight line connecting the position P and the position Q is the position of the gate insulating film field insulating film boundary 33. Maximum electric field strength E _H2max occurring at this position, on the straight line PQ, when the distance of the gate insulating film field insulating film boundary 33 from the position Q to x _R, the thickness of the gate insulating film and d _ox, the following formula It is represented by

したがって、ゲート絶縁膜に印加する電界強度をＥ_ｍａｘ以下にするためには、下記数８の不等式を満たす必要がある。

Therefore, in order to the intensity of the electric field applied to the gate insulating film below E _max it is required to satisfy the following inequality number 8.

Solving the range of the _{x R} to satisfy the inequality of Equation 8 in the range of _x R _{<x p,}

It becomes.
As described above, the position (position P) in the wafer plane where the distance to the ohmic electrode 71 (well contact hole 62) is the largest in the second well region 42 and the distance to the position P are the shortest. 71 on the straight line PQ connecting the position of the (well contact hole 62) (position Q), by a distance x _R of the gate insulating film field insulating film boundary 33 from the position Q is set so as to satisfy the equation (9), a gate insulating film The electric field applied to 30 can be set to a predetermined value or less. For example, when Emax is 10 MV / cm, the electric field applied to the gate insulating film 30 can be 10 MV / cm or less, and a highly reliable power semiconductor device can be obtained. Further, when Emax is 3 MV / cm, a more reliable power semiconductor device can be obtained.

  Next, the electric field applied to the field insulating film 31 is calculated.

On the straight line PQ, the region where the gate electrode 50 is located through the field insulating film 31 whose film thickness is d _FL when viewed from the position Q is the region where the gate electrode 50 is located via the gate insulating film 30 whose film thickness is d _OX. Since it is further away, a voltage higher than that of the gate insulating film 30 is applied to the field insulating film 31.

  Here, the position where the electric field having the greatest electric field strength is applied to the field insulating film 31 is the position farthest from the position Q among the positions where the gate electrode 50 exists on the straight line PQ. This position is defined as position S. A position S on the straight line PQ is shown in FIG. FIG. 9 is a schematic cross-sectional view of the power semiconductor device of the present embodiment.

When the distance from the position Q to the gate insulating film field insulating film boundary 33 is x _R , the distance from the position Q to the position S is x _S , and the film thickness of the field insulating film 31 is d _FL on the straight line PQ, x ≧ x field is applied to the field insulation film 31 of the position of _{R E} F (x) can be expressed by the following Expression 10.

Since the electric field E _H (x) takes the maximum value when x = x _S , the maximum value of the electric field E _F can be expressed by the following equation.

Therefore, in order to suppress the electric field strength applied to the field insulating film 31 to E _max or less, E _max ≧ E _F (x _S ),

And it is sufficient.
As described above, the position (position P) in the wafer plane where the distance to the ohmic electrode 71 (well contact hole 62) is the largest in the second well region 42 and the distance to the position P are the shortest. 71 on the straight line PQ connecting the position of the (well contact hole 62) (position Q), so that the distance x _S from the distance x _p and position Q from the position Q to the position P to the position S satisfies the relation of Equation 12 By setting to, the electric field applied to the field insulating film 31 can be made a predetermined value or less. For example, when E _max is 3 MV / cm, the electric field applied to the field insulating film 31 can be 3 MV / cm or less, and a highly reliable power semiconductor device can be obtained.

Note that silicon dioxide is generally used for the gate insulating film 30 and the field insulating film 31, and the breakdown electric field strength thereof is 10 MV / cm. When the _E max = 10MV / cm in the number 9 and number 12, by choosing the _{x R} range satisfying Equation 9, it is possible to prevent the breakdown of the gate insulating film _30, and the E max = 10MV / cm Occasionally, by choosing the thickness d _FL of the field insulating film 31 in the range satisfying Equation 12, it is possible to prevent the destruction of the field insulating film 31. Even when the gate insulating film 30 and the field insulating film 31 are silicon dioxide, it is more desirable that the gate insulating film 30 and the field insulating film 31 are lower than 10 MV / cm, and it is more preferable that E _max = 3 MV / cm. Thus, a more reliable power semiconductor device can be obtained.

Next, the influence of the film thickness of the interlayer insulating film 32 formed by the CVD method will be examined.
The interlayer insulating film 32 formed by the CVD method is also deposited on the side surface of the field insulating film 31 by a film thickness approximately equal to the film thickness deposited on the field insulating film 31. Therefore, the film thickness of the interlayer insulating film 32 in the vertical direction of the wafer increases in the range of a distance equal to the film thickness of the interlayer insulating film 32 from the gate insulating film field insulating film boundary 33 to the gate insulating film 30 side.

  The well contact hole 62 is formed so as to penetrate the interlayer insulating film 32, but in the range where the distance between the well contact hole 62 and the gate insulating film field insulating film boundary 33 is larger than the film thickness of the interlayer insulating film 31, the well contact hole 62 is formed. When the contact hole 62 is formed, the thickness of the interlayer insulating film 32 to be etched is uniform within the well contact hole 62, so that under-etching and over-etching are unlikely to occur and the process is facilitated.

In the power semiconductor device of the present embodiment, “the position where the distance from the well contact hole 62 connected to the second well region 42 in the second well region 42 is farthest” is as shown in FIG. in the outermost circumference of the second well region 42, a position P ₁ as a position closest to the center of the second well region 42, the well contact hole 62 closest to the position P ₁ is the position Q ₁ shown in FIG.

Up to this point, only the position on the straight line PQ has been described. However, for the entire power semiconductor device, each position on the outermost periphery of the second well region 42 (the second well region far from the first well region). The distance between P′Q ′ and the position Q ′ of the nearest well contact hole 62 on the straight line connecting _{P ′} and the position Q ′ of the nearest well contact hole 62 is xP ′, and the gate from the position (Q ′) of the well contact hole The distance to the insulating film field insulating film boundary 33 (R ′) is x _{R ′} , and the distance to the position (S ′) where the gate electrode 50 is located farthest from the position (Q ′) of the well contact hole 62 is x. _{As S ′} , the relationship of Equations 9 and 12 may be satisfied.

In the power semiconductor device of the present embodiment, E _{max is set} to 10 MV / cm, and the distance x _P from the point where the distance to the inner well contact hole in the second well region is the largest to the position of the well contact hole is set to several 9 Therefore, the electric field applied to the gate insulating film 30 can be 10 MV / cm or less, and a highly reliable power semiconductor device in which the gate insulating film 30 is not broken can be obtained.

Further, E _max is 10 MV / cm, the distance x _P from the point where the distance to the inner well contact hole 62 in the second well region 42 is the largest to the position of the well contact hole 62, the well contact hole on the field insulating film 31. Since the distance x _S between the position where the gate electrode 50 is farthest from 62 and the well contact hole 62 is set to a value defined by Equation 12, the electric field applied to the field insulating film 31 is 10 MV / cm or less. Thus, a highly reliable power semiconductor device in which the field insulating film 31 is not broken can be obtained.

  Here, a description will be given of driving a MOSFET using a wide band gap semiconductor material such as silicon carbide at a high speed, that is, driving at a high dV / dt.

  A conventional Si-MOSFET that is a unipolar element using Si (silicon) is operated at a relatively high speed of 20 V / nsec or more as an operation speed, but when operated at a high voltage of about 1 kV or higher. Since the conduction loss becomes very large, the operating voltage is limited to several tens to several hundreds volts. For this reason, an Si-IGBT (Insulated Gate Bipolar Transistor) has been used exclusively in a high voltage region of about 1 kV or higher. However, since the IGBT is a bipolar element, it is difficult to obtain high-speed switching characteristics like a unipolar element due to the influence of minority carriers. That is, since switching loss cannot be greatly reduced even if dV / dt is increased, it is not necessary to drive at high dV / dt, and it is used at an operating speed of about several V / nsec at most.

  On the other hand, a MOSFET using a wide band gap semiconductor material such as silicon carbide can obtain a low conduction loss even in a high voltage region of 1 kV or higher, and can operate at high speed because it is a unipolar element. Since switching loss can be reduced by high-speed switching, loss during inverter operation can be further reduced.

  In such an operating environment that is not possible with a conventional Si element, such as high-speed switching of 10 V / nsec or more in an operation in a high voltage region of 1 kV or higher, P is caused by the displacement current during switching as described in the example of Patent Document 1. The voltage generated in the well becomes more prominent.

  Further, when such a MOSFET is formed using a silicon carbide semiconductor material, an element having a sufficiently shallow p-type impurity level does not exist in the band gap of silicon carbide. Type silicon carbide cannot be obtained, and the contact resistance between the p type silicon carbide and the metal also increases. Therefore, when a MOSFET power semiconductor device is configured using silicon carbide, the value of the contact resistance between the P-well composed of p-type silicon carbide and this metal is increased, and the voltage generated by the displacement current is also increased. Become.

  For this reason, when a MOSFET power semiconductor device using a wide band gap semiconductor material, particularly silicon carbide, is driven at a high dV / dt, the voltage generated by the displacement current at the time of switching becomes particularly large.

  On the other hand, according to the power semiconductor device of the present embodiment formed of a wide band gap semiconductor material, silicon dioxide that is the gate insulating film 30 even when operated under a high dV / dt condition such as 10 V / nsec. The electric field applied to the film can be reduced, and a highly reliable power semiconductor device can be obtained.

  In the power semiconductor device of the present embodiment, well contact regions 46 and 47 are provided to reduce the contact resistance between the ohmic electrode 71 and the first well region 41 and the second well region 42, respectively. However, the well contact regions 46 and 47 are not essential and may be omitted. That is, if the contact resistance having a sufficiently low contact resistance is obtained by changing the metal forming the ohmic electrode 71 to one suitable for p-type silicon carbide, the well contact regions 46 and 47 need not be formed. . Further, a p-type junction termination structure (JTE) region which is a breakdown voltage structure may be provided in a part of the outside of the second well region 42. The field stopper region 81 is not essential and may be omitted.

  Furthermore, in the description of the method for manufacturing the power semiconductor device according to the present embodiment, the formation of the source contact hole 61 and the well contact hole 62 and the formation of the gate contact hole 64 are performed separately. The well contact hole 62 and the gate contact hole 64 may be formed at the same time. By simultaneously forming the source contact hole 61 and the well contact hole 62 and the gate contact hole 64, the number of steps can be reduced and the manufacturing cost can be reduced. At this time, silicide may be formed on the surface of the gate electrode 50 on the bottom surface of the gate contact hole 64 depending on the selection of the material of each component.

  Further, in the power semiconductor device, the temperature sensor electrode and the current sensor electrode may be formed in a part of the power semiconductor device, but these electrodes are included in the power semiconductor device in the present embodiment. May be formed. The presence / absence of the temperature sensor electrode and the current sensor electrode does not affect the effect of the power semiconductor device of the present embodiment.

  Although not shown and described, a silicon nitride film or polyimide is left, leaving openings for connecting the source pad 10, gate pad 11, and gate wiring 12 on the upper surface of the power semiconductor device to an external control circuit. It may be covered with a protective film.

  Further, in the power semiconductor device of the present embodiment, an example in which doped polycrystalline silicon is used as the material of the gate electrode 50 has been described. However, since the resistance of the doped polycrystalline silicon is not sufficiently low, the gate pad In some cases, the potential of the gate electrode 50 at a location distant from the connection position with the gate 11 may be temporally shifted from the potential of the gate pad 11 and the gate wiring 12. This time shift is determined by a time constant determined by a resistance component such as the resistance of the gate electrode 50 and a parasitic capacitance formed between the source pad 10 and the like. In the present embodiment, the low-resistance gate wiring 12 is provided in parallel with the gate electrode 50 in the outer peripheral portion, so that the occurrence of the time shift as described above is suppressed.

  In the power semiconductor device of the present embodiment, the first well region 41 and the second well region 42 have been described and illustrated as having the same p-type impurity concentration and depth. The impurity concentration and the depth of each need not be the same, and may be different values.

  In the power semiconductor device of the present embodiment, the well contact regions 46 and 47 have been described as being individually located below the contact holes. However, the well contact regions 46 and 47 are continuous with the cross-sectional depth method. May be formed.

Embodiment 2. FIG.
FIG. 10 is a plan view of a power semiconductor device mainly including a silicon carbide MOSFET, which is a power semiconductor device according to the second embodiment of the present invention, as viewed from above. In FIG. 10, a source pad 10 is provided at the center of the upper surface of the power semiconductor device. A gate pad 11 is formed inside the source pad 10 as viewed from above, and one or more gate wirings 12 having a line width narrower than the gate pad 11 are formed extending from the gate pad 11.

FIG. 11 is a plan view of the layers below the layers such as the source pad 10 and the gate pad 11 shown in FIG. Further, FIG. 12 shows the position _{S 2} on the straight line _P 2 _{Q 2} in FIG. 11. FIG. 12 is a schematic cross-sectional view of the power semiconductor device of the present embodiment. In the arrangement of the source pad 10 and the gate pad 11 on the plane shown in FIG. 11, the arrangement of the second well region 42 is also different from that in the first embodiment (FIG. 2). In this case, "in the second well region 42, farthest distance from the well contact hole 62 connected to the second well region 42 ', as shown with P ₂ in FIG. 11, the second well region 42 Even in this case, even in this case, “the position where the distance from the well contact hole 62 connected to the second well region 42 is the farthest in the second well region 42” (P ₂ ) and the nearest well contact. Also between the hole 62 (ohmic contact 71) (Q _{2 in} FIG. 11), the distance from the nearest well contact hole 62 (ohmic electrode 71) to the gate insulating film field insulating film boundary 33, and the field insulating film 31 the film thickness on the number 9 range described in the _{embodiments, E max} of 10 MV / cm, more preferably, to a 3 MV / cm It is to prevent dielectric breakdown of the gate insulating film 30 and the field insulating film 31, a highly reliable device is obtained. Expression 12 is the same as that in the first embodiment.

  As described above, the position and number of the gate pads 11, the shape of the source pad 10, and the like can be in a wide variety of cases, but they do not affect the effect of the power semiconductor device of the present invention.

  In the first and second embodiments, the case where the semiconductor element formed in the cell region is a vertical MOSFET is disclosed. For example, the semiconductor substrate 20 of FIG. 3 and the back surface ohmic electrode 72 on the back surface side are disclosed. Even if a semiconductor element having an IGBT cell region is formed by providing a collector layer of the second conductivity type in between, the above-described effects of the present invention can be similarly achieved for a semiconductor element having an IGBT cell region. The Therefore, the scope of the present invention is a semiconductor element as a switching element having a MOS structure such as MOSFET or IGBT. When the semiconductor element is an IGBT, the drain (electrode) of the MOSFET corresponds to the collector (electrode), and the source (electrode) of the MOSFET corresponds to the emitter (electrode).

Also, in the trench type MOSFET in which the channel region is formed perpendicular to the surface of the semiconductor substrate 20, E _{max is set} to 10 MV / cm, more preferably 3 MV / cm, so that the relations of Equations 9 and 12 are satisfied. Thus, even when the switch-off is performed at high speed, the electric field applied to the gate insulating film 30 and the field insulating film can be suppressed to a predetermined value or less, and a highly reliable power semiconductor device can be obtained.

  Furthermore, if the structure of the power semiconductor device shown in the first and second embodiments is provided, the effect of the present invention does not depend on the manufacturing method, and other than the manufacturing method described in the first and second embodiments. Also in the power semiconductor device structure manufactured by using this manufacturing method, a highly reliable power semiconductor device structure can be obtained.

  In the first and second embodiments, examples of power semiconductor devices mainly composed of silicon carbide materials have been described. However, the present invention is not limited to power semiconductor devices composed of silicon carbide. A power semiconductor device composed of a wide band gap semiconductor material such as gallium nitride, another semiconductor material such as a gallium arsenide material, or a Si material has the same effect. The effect of the present invention is remarkable when the semiconductor material is a wide gap semiconductor. For example, the present invention is applied to a semiconductor device used for semiconductor materials such as silicon carbide, gallium nitride, aluminum nitride, and diamond. This is particularly effective when

  In addition, the gate insulating film 30 of the power semiconductor device described as the vertical MOSFET in the first and second embodiments does not necessarily need to be an oxide film such as silicon dioxide as the name of the MOS. An insulating film such as an aluminum film may be used.

  Furthermore, in the present invention, in addition to defining the semiconductor element itself having the MOSFET structure described in the first and second embodiments as a “semiconductor device” in a narrow sense, for example, a semiconductor element having this MOSFET structure, A semiconductor element such as a freewheel diode connected in antiparallel to the semiconductor element and an inverter module mounted on a lead frame and sealed together with a control circuit for generating and applying a gate voltage of the semiconductor element. The incorporated power module itself can also be defined as a “semiconductor device” in a broad sense.

  10 source pad, 11 gate pad, 12 gate wiring, 13 drain electrode, 20 semiconductor substrate, 21 drift layer, 30 gate insulating film, 31 field insulating film, 32 interlayer insulating film, 33 gate insulating film field insulating film boundary, 41 1 well region, 42 second well region, 46, 47 well contact region, 50 gate electrode, 61 source contact hole, 62 well contact hole, 64 gate contact hole, 71 ohmic electrode, 72 back ohmic electrode, 80 source region, 81 Field stopper area.

Claims (8)

A silicon carbide semiconductor substrate;
A drift layer using a silicon carbide material of a first conductivity type formed on the first main surface of the silicon carbide semiconductor substrate;
A plurality of second well-conducting type first well regions formed in part of the surface layer of the drift layer;
A first conductivity type source region formed in a part of a surface layer of each of the plurality of first well regions; and a second layer formed in a region different from the first well region of the surface layer of the drift layer. A second well region of conductivity type;
A plurality of first well regions, a gate insulating film formed on the source region and on the second well region on the first well region side;
A field insulating film formed on the side opposite to the first well region side above the second well region and having a thickness greater than that of the gate insulating film;
A gate electrode formed on the field insulating film and the gate insulating film;
The first well region and the second well region are electrically connected through a source contact hole formed on the first well region and a well contact hole formed on the second well region. A source pad,
A gate pad electrically connected to the gate electrode;
A drain electrode provided on the second main surface of the silicon carbide semiconductor substrate;
With
The distance from the distance is the largest position to an inner said well contact hole of said second well region (P) to the position of the well contact hole closest (Q) and x _P, said well contact hole on a straight line PQ the distance from the position of (Q) to the boundary (R) of said field insulating film and the gate insulating film as x _R, the thickness of the gate insulating film d _ox, time switched from the oN state to the oFF state t , R _SH is the sheet resistance of the second well region, ε ₀ is the vacuum dielectric constant, ε _S is the relative dielectric constant of the drift layer, q is the elementary charge, and N _D is the effective first conductivity type impurity of the drift layer _{concentration,} and the voltage of the drain electrode of the off state _{V oFF, E} Ri _max is 10 MV / cm der, the voltage _{V oFF} of the drain electrode time derivative of 10V / nsec and to Rutoki, where Satisfy the equation relationship,
The power semiconductor device, wherein the predetermined mathematical formula is Formula 1.

A silicon carbide semiconductor substrate;
A drift layer using a silicon carbide material of a first conductivity type formed on the first main surface of the silicon carbide semiconductor substrate;
A plurality of second well-conducting type first well regions formed in part of the surface layer of the drift layer;
A first conductivity type source region formed in a part of a surface layer of each of the plurality of first well regions; and a second layer formed in a region different from the first well region of the surface layer of the drift layer. A second well region of conductivity type;
A plurality of first well regions, a gate insulating film formed on the source region and on the second well region on the first well region side;
A field insulating film formed on the side opposite to the first well region side above the second well region and having a thickness greater than that of the gate insulating film;
A gate electrode formed on the field insulating film and the gate insulating film;
The first well region and the second well region are electrically connected through a source contact hole formed on the first well region and a well contact hole formed on the second well region. A source pad,
A gate pad electrically connected to the gate electrode;
A drain electrode provided on the second main surface of the silicon carbide semiconductor substrate;
With
The position of the well contact hole nearest to the position (P ′) of the outer periphery of the second well region farthest from the first well region among the second well regions below the field insulating film (Q 'on a straight line connecting the), P'Q' the distance between _'the position of the well contact hole (Q' x _P from) to the boundary (R ') with the field insulating film and the gate insulating film The distance is _{xR ′} , d _ox is the thickness of the gate insulating film, t is the time for switching from the on state to the off state, R _SH is the sheet resistance of the second well region, ε ₀ is the vacuum dielectric constant, ε the dielectric constant of the _S the drift layer, q the elementary charge, the effective first conductivity type impurity concentration of the _{N D} the drift _layer, the voltage of the drain electrode of the off state _{V oFF, E max} is at 10 MV / cm Oh it is, of the drain electrode The time derivative of the pressure _{V OFF} 10V / nsec and to Rutoki, satisfy a predetermined formula relationships,
2. The power semiconductor device according to claim 2, wherein the predetermined mathematical formula is Formula 2.

A silicon carbide semiconductor substrate;
A drift layer using a silicon carbide material of a first conductivity type formed on the first main surface of the silicon carbide semiconductor substrate;
A plurality of second well-conducting type first well regions formed in part of the surface layer of the drift layer;
A first conductivity type source region formed in a part of a surface layer of each of the plurality of first well regions; and a second layer formed in a region different from the first well region of the surface layer of the drift layer. A second well region of conductivity type;
A plurality of first well regions, a gate insulating film formed on the source region and on the second well region on the first well region side;
A field insulating film formed on the side opposite to the first well region side above the second well region and having a thickness greater than that of the gate insulating film;
A gate electrode formed on the field insulating film and the gate insulating film;
The first well region and the second well region are electrically connected through a source contact hole formed on the first well region and a well contact hole formed on the second well region. A source pad,
A gate pad electrically connected to the gate electrode;
A drain electrode provided on the second main surface of the silicon carbide semiconductor substrate;
With
The distance from the distance is the largest position to an inner said well contact hole of said second well region (P) to the position of the well contact hole closest (Q) and x _P, said field insulating films on the straight line PQ the distance between the position of the well contact hole position (S) and the farthest from the location of the well contact hole above (Q) is the gate electrode (Q) as x _S, wherein the field insulating the d _FL The thickness of the film, the time for switching t from the on state to the off state, R _SH is the sheet resistance of the second well region, ε ₀ is the dielectric constant of vacuum, ε _S is the relative dielectric constant of the drift layer, and q is the prime charge, the effective first conductivity type impurity concentration of the _{N D} the drift _layer, a _{V oFF} and the drain voltage in the off _{state, E max} Ri is 10 MV / cm der, the voltage of the drain electrode V The time derivative of the _OFF 10V / nsec and be Rutoki, satisfies a predetermined formula relationships,
The power semiconductor device, wherein the predetermined mathematical formula is Formula 3.

A silicon carbide semiconductor substrate;
A drift layer using a silicon carbide material of a first conductivity type formed on the first main surface of the silicon carbide semiconductor substrate;
A plurality of second well-conducting type first well regions formed in part of the surface layer of the drift layer;
A first conductivity type source region formed in a part of a surface layer of each of the plurality of first well regions; and a second layer formed in a region different from the first well region of the surface layer of the drift layer. A second well region of conductivity type;
A plurality of first well regions, a gate insulating film formed on the source region and on the second well region on the first well region side;
A field insulating film formed on the side opposite to the first well region side above the second well region and having a thickness greater than that of the gate insulating film;
A gate electrode formed on the field insulating film and the gate insulating film;
The first well region and the second well region are electrically connected through a source contact hole formed on the first well region and a well contact hole formed on the second well region. A source pad,
A gate pad electrically connected to the gate electrode;
A drain electrode provided on the second main surface of the silicon carbide semiconductor substrate;
With
The position of the well contact hole nearest to the position (P ′) of the outer periphery of the second well region farthest from the first well region among the second well regions below the field insulating film (Q The distance between P′Q ′ is xP ′ on the straight line connecting “) _”, and the position where the gate electrode is located farthest from the position (Q ′) of the well contact hole on the field insulating film ( X _{FL '} is the distance to S ′), d _FL is the thickness of the field insulating film, t is the time for switching from the on state to the off state, R _SH is the sheet resistance of the second well region, and ε ₀ is the vacuum the dielectric constant, and ε the dielectric constant of the _S the drift layer, q the elementary charge, the effective first conductivity type impurity concentration of the _{N D} the drift _layer, a _{V oFF} and the drain voltage in the off _{state, E max} is 10 MV / cm der is, the drain The time derivative of the voltage _{V OFF} of emission electrodes 10V / nsec and to Rutoki, satisfy a predetermined formula relationships,
The power semiconductor device, wherein the predetermined mathematical formula is Formula 4.

5. The power semiconductor device according to claim 1, wherein when the E _max is 3 MV / cm, the predetermined mathematical relationship is satisfied. An interlayer insulating film is provided on the gate insulating film and the field insulating film, and x _P , x _{P ′} , x _R , x _{R ′,} x _S or x _{S ′} is larger than the film thickness of the interlayer insulating film. The power semiconductor device according to claim 1, wherein the power semiconductor device is a power semiconductor device. The power semiconductor device according to any one of claims 1 to 6, wherein the field insulating film and having a thickness of 2μm or more 0.5 [mu] m. The power semiconductor device according to any one of claims 1 to 7 , wherein the power semiconductor device is a trench type.

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