JP2020036045A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device which has excellent pressure resistance and can be manufactured with high yield.SOLUTION: A semiconductor device 1 is manufactured, which includes: p- type body regions 17 formed at a distance from each other in a surface layer portion of an SiC epitaxial layer 14; n+ type source regions 19 formed on surface layer portions of the respective p- type body regions 17 at an interval from the periphery of the p- type body regions 17; a gate electrode 10 formed across the p- type body region 17, and facing a channel region 22 between the periphery of the p- type body regions 17 and the n+ type source region 19 with a gate insulating film 21 interposed therebetween, and selectively separated by a cavity 25 in a JFET region 18 between the adjacent p- type body regions 17, and an intermediate insulating film 30 formed in the cavity 25 and thicker than the gate insulating film 21.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device.

Patent Literature 1 discloses an n ⁺ -type SiC substrate, an n ⁻ -type SiC epi layer formed on the SiC substrate, and a plurality of p-type bases formed at intervals on a surface portion of the n ⁻ -type SiC epi layer. Disclosed is a semiconductor device including a region and an N ⁺ type source region formed in a surface layer of each base region. A gate insulating film in the semiconductor device is formed to extend between adjacent base regions, and a gate electrode is formed on the gate insulating film. The gate electrode faces each body region with the gate insulating film interposed therebetween. A source electrode is electrically connected to the source region. On the other hand, the drain electrode is formed on the back side of the SiC substrate. Thus, a power device having a vertical structure in which the source electrode and the drain electrode are arranged in a vertical direction perpendicular to the main surface of the SiC substrate is configured.

  When a voltage equal to or higher than the threshold is applied to the gate electrode in a state where a voltage is applied between the source electrode and the drain electrode (between the source and the drain), an electric field from the gate electrode causes a contact with the gate insulating film in the body region. A channel is formed near the interface. Accordingly, a current flows between the source electrode and the drain electrode, and the power device is turned on.

JP 2003-347548 A

In the semiconductor device as disclosed in Patent Document 1, when the semiconductor device is off (that is, the gate voltage is 0 V), the source region and the SiC substrate functioning as the drain have a voltage at which the SiC substrate is on the (+) side. Is applied, equipotential surfaces having a higher potential are distributed between the body regions adjacent to each other with reference to the gate electrode (0 V).
Since this equipotential surface has a smaller interval than the equipotential surfaces in other regions, a large electric field is applied to the gate insulating film interposed between the gate electrode and the SiC substrate. Therefore, if a voltage as high as the device withstand voltage is continuously applied between the source and the drain, the gate insulating film cannot withstand the electric field concentration and may cause dielectric breakdown.

Such a problem also causes a decrease in yield in a high temperature reverse bias (HTRB) test for inspecting a device breakdown voltage under a high temperature environment.
One embodiment of the present invention provides a semiconductor device having excellent withstand voltage.

  In one embodiment of the present invention, a plurality of semiconductor layers having a main surface and having a first conductivity type including a wide band gap semiconductor and a surface layer portion of the main surface of the semiconductor layer are formed at intervals from each other. A second conductivity type body region, a first conductivity type source region (or emitter region) formed in a surface layer of the body region, and a gate insulating film formed on the main surface of the semiconductor layer. A gate electrode formed on the gate insulating film and having ends above the source region (or the emitter region) and above an intermediate region between the adjacent body regions of the second conductivity type. A semiconductor device, wherein the thickness of the gate insulating film is greater at the end of the gate electrode than at a channel region below the gate electrode.

FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is an enlarged view showing an arrangement of gate electrodes and unit cells of the semiconductor device shown in FIG. FIG. 3A is a sectional view taken along the section line IIIa-IIIa in FIG. 2, and FIG. 3B is a sectional view taken along the section line IIIb-IIIb in FIG. FIG. 4 is a table showing the relationship between the electric field strength at the time of dielectric breakdown of SiO ₂ , SiC and Si. FIG. 5 is a schematic view of the SiC substrate and the SiC epitaxial layer in a wafer state. FIG. 6 is a schematic diagram illustrating a unit cell having a 4H—SiC crystal structure. FIG. 7 is a diagram of the unit cell of FIG. 6 as viewed from directly above the (0001) plane. FIG. 8 is a flowchart illustrating an example of a manufacturing process of the semiconductor device shown in FIG. FIG. 9 is a schematic sectional view of a semiconductor device according to the second embodiment of the present invention. FIG. 10 is a schematic sectional view of a semiconductor device according to the third embodiment of the present invention. FIG. 11 is a schematic enlarged plan view of a semiconductor device according to a modification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of a semiconductor device 1 according to the first embodiment of the present invention.
The semiconductor device 1 employs SiC as an example of a wide bandgap semiconductor, and includes, for example, a planar gate type VDMISFET (Vertical double diffused Metal Insulator Field effect Transistor) 2 having a breakdown voltage of 600 V to 10000 V.

The semiconductor device 1 is formed in a substantially rectangular shape including a pair of long sides 1a and a pair of short sides 1b in plan view of FIG. At one end in the longitudinal direction along the long side 1 a of the semiconductor device 1, a gate pad 3 having a substantially rectangular shape in plan view is formed, and an active region 4 including the VDMISFET 2 is formed so as to surround the gate pad 3. ing.
Gate pad 3 includes a pair of long sides 3 a formed along short side 1 b of semiconductor device 1 and a pair of short sides 3 b formed along long side 1 a of semiconductor device 1. A plurality of contacts 5 are formed on the gate pad 3 along the periphery of the gate pad 3 at intervals. The contacts 5 are formed at both longitudinal ends of each long side 3a of the gate pad 3 and at the longitudinal center of each short side 3b. The gate wiring 6 is electrically connected to each contact 5. .

  The gate wiring 6 includes a first wiring 7 connected to each contact 5 on each long side 3a of the gate pad 3, and a second wiring 8 connected to each contact 5 on each short side 3b of the gate pad 3. . The first wirings 7 are formed so as to run in parallel with each other in a direction perpendicular to the short side 1 b of the semiconductor device 1 from each contact 5. On the other hand, each second wiring 8 is formed along each short side 3 b of the gate pad 3. A plurality of gate electrodes 10 are formed on the first wiring 7 and the second wiring 8 so as to be integrally connected.

  The plurality of gate electrodes 10 are formed in a direction orthogonal to the gate wiring 6, and are arranged in stripes at intervals. Hereinafter, the direction in which the gate electrodes 10 are arranged is referred to as the “stripe direction of the gate electrode 10”. The VDMISFET 2 formed along the stripe direction of the gate electrode 10 is electrically connected to the gate electrode 10. That is, in the present embodiment, the striped VDMISFET 2 is formed. Hereinafter, the structure of the VDMISFET 2 will be described more specifically with reference to FIGS.

FIG. 2 is an enlarged view showing an arrangement of the gate electrodes 10 and the unit cells 11 of the semiconductor device 1 according to FIG. FIG. 3A is a sectional view taken along the section line IIIa-IIIa in FIG. 2, and FIG. 3B is a sectional view taken along the section line IIIb-IIIb in FIG. In FIG. 2, the gate wiring 6 and the gate electrode 10 are indicated by hatching for convenience of explanation.
As shown in FIG. 3, the semiconductor device 1 has a SiC semiconductor layer 12 containing SiC as an example of a wide band gap semiconductor. SiC semiconductor layer 12 includes an ^{n +} -type SiC substrate 13, is stacked on ^{the n +} -type SiC substrate 13, than ^{the n +} -type SiC substrate 13 and the low concentration of the SiC epitaxial layer 14. The SiC epitaxial layer 14 is formed by epitaxially growing SiC on the surface of the n ⁺ -type SiC substrate 13 and functions as a drift layer (drain layer) of the semiconductor device 1.

The impurity concentration of n ⁺ type SiC substrate 13 is, for example, 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , and the impurity concentration of SiC epitaxial layer 14 is, for example, 1 × 10 ¹⁴ cm ⁻³ to 1 ×. 10 ¹⁷ cm ⁻³ . As the n-type impurity, for example, N (nitrogen), P (phosphorus), As (arsenic) and the like can be used (the same applies hereinafter). In the surface portion of SiC epitaxial layer 14, p ⁻ type body connection region 16 and p ⁻ type body region 17 are integrally formed.

The p ⁻ type body connection region 16 is formed along the gate line 6 as shown in FIGS. 2 and 3A. The p ⁻ type body connection region 16 is formed wider than the gate line 6 and is formed to cover the gate line 6 from below.
On the other hand, as shown in FIGS. 2 and 3B, a plurality of p ⁻ type body regions 17 are formed at intervals from one another along the stripe direction of the gate electrode 10. One end and / or the other end in the longitudinal direction of each p ⁻ type body region 17 is formed so as to be integrally connected to p ⁻ type body connection region 16 as shown in FIG. The SiC epitaxial layer 14 between the adjacent p ⁻ -type body regions 17 is a JFET (Junction Field Effect Transistor) region 18 as an intermediate region.

  The width WJ of the JFET region 18 is preferably, for example, 0.1 μm to 50 μm (2.6 μm in the present embodiment). As the JFET region 18 becomes wider, when the gate electrode 10 is in the off state, a high potential equipotential surface tends to be distributed in the JFET region 18. On the other hand, if the JFET region 18 is too narrow, the resistance value of the JFET region 18 will increase. Therefore, within this numerical range, a good resistance value can be realized while suppressing the distribution of the high-potential equipotential surface in the JFET region 18.

The depths of the p ⁻ -type body connection region 16 and the p ⁻ -type body region 17 (the depths from the surface of the SiC epitaxial layer 14 in the thickness direction; the same applies hereinafter) are, for example, 0.1 μm to 10 μm. It is. Further, the impurity concentration of p ⁻ -type body connection region 16 and p ⁻ -type body region 17 is, for example, 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . As the p-type impurity, for example, B (boron), Al (aluminum), or the like can be used (the same applies hereinafter). An n ⁺ -type source region 19 and a p ⁺ -type body contact region 20 are formed in the surface layer of the p ⁻ -type body region 17.

The n ⁺ type source region 19 is formed along the stripe direction of the gate electrode 10 as shown in FIGS. 2 and 3B, and is spaced apart from the periphery of the p ⁻ type body region 17 in plan view. It is formed in a rectangular ring shape. N ⁺ type source region 19 is formed shallower than p ⁻ type body region 17, and has a depth of, for example, 0.05 μm to 5 μm. Further, the impurity concentration of n ⁺ type source region 19 is, for example, 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

p ⁺ -type body contact region 20, as shown in FIGS. 2 and 3 (b), are formed along the stripe direction of the gate electrode 10, the inner portion surrounded by the n ⁺ -type source region 19 ( The p ^- type body region 17 is formed in a substantially rectangular shape in plan view (at the center of the surface layer). The p ⁺ type body contact region 20 is formed shallower than the p ⁻ type body region 17 and deeper than the n ⁺ type source region 19. The depth of p ⁺ type body contact region 20 is, for example, 0.06 μm to 6 μm. Further, the impurity concentration of p ⁺ -type body contact region 20 is, for example, 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . A unit cell 11 extending in the stripe direction of the gate electrode 10 is defined by a boundary line passing through the center of the p ⁺ type body contact region 20. A gate insulating film 21 is formed on the surface of SiC epitaxial layer 14 along p ⁻ type body connection region 16 and each unit cell 11.

In the present embodiment, the gate insulating film 21 is a silicon oxide film made of SiO ₂ (silicon oxide). The gate insulating film 21 formed on the p ⁻ type body connection region 16 is formed wider than the gate wiring 6 as shown in FIG. That is, the entire gate wiring 6 faces the p ⁻ type body connection region 16 with the gate insulating film 21 interposed therebetween. On the other hand, as shown in FIG. 3B, the gate insulating film 21 formed on each unit cell 11 is formed so as to straddle the p ⁻ type body region 17 adjacent to each other. More specifically, the gate insulating film 21, each of the p ^- is formed so as to cover the outer peripheral portion of the n ⁺ -type source part surrounding the region 19 and the n ⁺ -type source region 19, in the mold body region 17. Gate insulating film 21 is formed to have a uniform thickness, and the film thickness is preferably, for example, 1 μm or less.

The gate electrode 10 faces the channel region 22 with the gate insulating film 21 interposed therebetween. More specifically, gate electrode 10 has a region extending across SiC epitaxial layer 14, p ⁻ -type body region 17 and n ⁺ -type source region 19 outside p ⁻ -type body region 17 with gate insulating film 21 interposed therebetween. Facing. In a plan view, the gate electrode 10 includes an overlap portion protruding from the boundary between the n ⁺ type source region 19 and the p ⁻ type body region 17 toward the n ⁺ type source region 19. In the direction orthogonal to the stripe direction, the width of the overlap portion of the gate electrode 10 is, for example, 0.05 μm to 1 μm.

Gate electrode 10 (and gate wiring 6) has a thickness of, for example, 2 μm or less. Further, the gate electrode 10 (and the gate wiring 6) is formed of an electrode material made of polysilicon or a metal material. When polysilicon is used for the gate electrode 10, the polysilicon preferably contains B (boron) ions. Thus, the threshold voltage (V _{GS (th)} ) of the gate voltage required for forming a channel can be reduced.

On the other hand, when a metal material is used for the gate electrode 10, the metal material is preferably made of Al (aluminum), Cu (copper), or AlCu (aluminum copper). According to these metal materials, the resistance value of the gate electrode 10 can be reduced as compared with the case where polysilicon is adopted as the electrode material. Therefore, the thickness of the gate electrode 10 can be further reduced (for example, 0.1 μm to 1 μm). A cavity 25 is formed in each gate electrode 10 on the region (JFET region 18) between the adjacent p ⁻ -type body regions 17.

The cavity 25 is a region where the electrode material of the gate electrode 10 is removed and the gate electrode 10 does not face the JFET region 18 with the gate insulating film 21 interposed therebetween. Each cavity 25 is formed in a substantially rectangular shape along the stripe direction of the gate electrode 10, as shown in FIG. Further, each cavity 25 is formed at a position crossing a boundary passing through the center between the p ⁻ -type body regions 17 in a direction perpendicular to the stripe direction. More specifically, each cavity 25 is formed to fit inside JFET region 18 at a distance from the boundary between each p ⁻ -type body region 17 and JFET region 18. Each cavity 25 is preferably formed on the center of adjacent p ⁻ -type body regions 17. One end and / or the other end of each cavity 25 in the stripe direction is formed so as to reach the gate wiring 6.

As shown in FIG. 3B, each cavity 25 is formed to have a width smaller than the width WJ (= 2.6 μm) of the JFET region 18, and the width WD is, for example, 0.1 μm to 2.0 μm. It is 4 μm (in this embodiment, 1.6 μm). Due to the hollow portion 25, the gate electrode 10 is configured to further include an overlap portion that protrudes from the boundary between the p ⁻ -type body region 17 and the JFET region 18 toward the JFET region 18 in plan view. Thereby, the gate electrode 10 can be reliably opposed to the p ⁻ type body region 17 between the n ⁺ type source region 19 and the JFET region 18, so that the channel in the p ⁻ type body region 17 can be formed. Can be controlled reliably. That is, when the gate electrode 10 is turned on, a current can flow through the JFET region 18 in each unit cell 11. More specifically, the current can flow from SiC epitaxial layer 14 to n ⁺ -type source region 19 via channel region 22 in p ⁻ -type body region 17. The channel length L of the channel region 22 is defined by the width of the p ⁻ type body region 17 immediately below the gate electrode 10 and is, for example, 0.05 μm to 2 μm (0.65 μm in the present embodiment).

On the SiC epitaxial layer 14, an interlayer insulating film 26 is formed so as to cover the gate electrode 10 by burying the cavity 25 from above the gate insulating film 21. The interlayer insulating film 26 formed on the gate insulating film 21 in the cavity 25 has substantially the same thickness as the interlayer insulating film 26 formed so as to cover the gate electrode 10. As the insulating material of the interlayer insulating film 26, SiO ₂ or an insulating material having a higher dielectric constant than SiO ₂ , for example, Al ₂ O ₃ or SiN can be adopted. In FIG. 3, the thickness of the interlayer insulating film 26 on the gate insulating film 21 is increased in order to more clearly show the configuration of the cavity 25 (the intermediate insulating film 30).

The intermediate insulating film 30 as an example of the intermediate insulating film of the present invention is defined by the laminated structure of the gate insulating film 21 in the cavity 25 and the interlayer insulating film 26 buried in the cavity 25.
When SiO ₂ is used as the insulating material of the interlayer insulating film 26, the interlayer insulating film 26 is preferably a PSG (Phosphorus Silicon Glass) film in which P (phosphorus) ions are contained in the SiO ₂ . According to the PSG film, the interlayer insulating film 26 having a flat surface can be formed. In addition, the PSG film melts well during reflow (for example, about 1000 ° C.). Therefore, the PSG film can be satisfactorily buried in the cavity 25. Further, the interlayer insulating film 26 is more preferably a BPSG (Boron Phosphorus Silicon Glass) film in which the SiO ₂ contains B (boron) ions in addition to P (phosphorus) ions. The BPSG film melts at a lower temperature (for example, about 800 ° C.) than the PSG film. Therefore, the BPSG film can be more satisfactorily embedded in the cavity 25, and the interlayer insulating film 26 having a more flat surface can be formed.

On the other hand, when Al ₂ O ₃ or SiN is used as the insulating material of the interlayer insulating film 26, the intermediate insulating film 30 has a multilayer structure in which Al ₂ O ₃ or SiN is stacked on the gate insulating film 21 (SiO ₂ ). including. According to this configuration, since the portion (connection interface) where the SiC epitaxial layer 14 and the intermediate insulating film 30 are in contact with each other is formed by the gate insulating film 21, the channel mobility of carriers flowing through the channel region 22 can be improved. On the other hand, since the interlayer insulating film 26 having a higher dielectric constant than SiO ₂ is formed on the gate insulating film 21, the dielectric constant of the intermediate insulating film 30 can be increased by the interlayer insulating film 26.

The intermediate insulating film 30 thus formed has a thickness of at least twice (more specifically, at least 2 to 25 times) the thickness of the gate insulating film 21, and the A portion of the insulating film 21 where an electric field is easily applied (that is, a central portion between the adjacent p ⁻ -type body regions 17) is formed thicker than other portions.
FIG. 4 is a table showing the relationship between the electric field strength at the time of dielectric breakdown of SiO ₂ , SiC and Si.

Referring to the table of FIG. 4, the electric field of SiO ₂ (= 6.4 MV / cm) at the time of semiconductor breakdown of SiC is different from the electric field (= 0.77 MV / cm) of SiO ₂ at the time of semiconductor breakdown of Si. In comparison, the value is close to the electric field (= 8 MV / cm to 11 MV / cm) at the time of dielectric breakdown of SiO ₂ . This indicates that the gate insulating film (SiO ₂ ) is more easily broken in the case of the SiC semiconductor device than in the case of the Si semiconductor device. Therefore, as in the present embodiment, by forming the intermediate insulating film 30 thicker than the gate insulating film 21 while forming the cavity 25 on the central portion of the JFET region 18 where the electric field tends to be highest, the gate insulating It can be seen that the destruction of the film 21 (SiO ₂ ) can be effectively suppressed. Further, it can be seen that such an intermediate insulating film 30 is particularly effective in a SiC semiconductor device.

The electric field of SiO ₂ at the time of semiconductor breakdown of SiC (or Si) is calculated by (dielectric constant of SiC / relative permittivity of SiO ₂ ) × dielectric breakdown voltage of SiC (or Si).
Referring again to FIG. 3A and FIG. 3B, a contact hole 33 is formed in the interlayer insulating film 26. In the contact hole 33, the entire p ⁺ type body contact region 20 and the inner peripheral portion of the n ⁺ type source region 19 are exposed.

On the interlayer insulating film 26, a source electrode 34 is formed. The source electrode 34 is collectively connected to the p ⁺ -type body contact regions 20 and the n ⁺ -type source regions 19 of all the unit cells 11 via the respective contact holes 33. That is, the source electrode 34 is a common wiring for all the unit cells 11. The source electrode 34 may have a structure in which a Ti / TiN layer 35 and an Al layer are sequentially stacked from the contact side with the SiC epitaxial layer 14. The Ti / TiN layer 35 is a laminated film having a Ti layer as an adhesion layer on the SiC epitaxial layer 14 side, and a TiN layer as a barrier layer laminated on this Ti layer. The barrier layer prevents the constituent atoms (Al atoms) of the Al layer from diffusing to the SiC epitaxial layer 14 side. A passivation film (not shown) is partially formed on the source electrode 34, and a portion without the passivation film is a source pad (not shown).

On the back surface of the n ⁺ -type SiC substrate 13, a drain electrode 36 is formed so as to cover the whole area. The drain electrode 36 is a common wiring for all the unit cells 11. As the drain electrode 36, for example, a laminated structure (Ti / Ni / Au / Ag) in which Ti, Ni, Au and Ag are laminated in order from the n ⁺ -type SiC substrate 13 can be adopted.
Next, the relationship between the off direction of the n ⁺ -type SiC substrate 13 and the direction in which the unit cells 11 are formed will be described with reference to FIGS. FIG. 5 is a schematic diagram of the n ⁺ -type SiC substrate 13 and the SiC epitaxial layer 14 in a wafer state.

The SiC crystal forming the n ⁺ -type SiC substrate 13 and the SiC epitaxial layer 14 of the semiconductor device 1 is a material showing a polymorphism (polytype) having the same composition and various laminated structures, and several hundreds or more There are polytypes. As the polytype, for example, there are 4H-SiC, 3CSiC, 6H-SiC, 15R-SiC and the like. Among them, 4H-SiC is preferable. In the following description, it is assumed that a 4H-SiC wafer is used as the n ⁺ -type SiC substrate 13.

The thickness t1 of the n ⁺ type SiC substrate 13 is, for example, 200 μm to 500 μm, and the thickness t2 of the SiC epitaxial layer 14 is smaller than that of the n ⁺ type SiC substrate 13, for example, 5 μm to 100 μm (for example, about 10 μm). ).
In this embodiment, the n ⁺ type SiC substrate 13 has an off angle θ of 2 ° to 8 ° (preferably, about 4 °). For example, the surface of n ⁺ type SiC substrate 13 is a surface inclined at an off angle θ in the <11-20> direction (off direction) with respect to the (0001) plane. Expressions such as (0001) and <11-20> are so-called Miller indices, and are used when describing the lattice plane and lattice direction of the SiC crystal. The Miller index can be described with reference to FIGS.

FIG. 6 is a schematic diagram illustrating a unit cell having a 4H—SiC crystal structure. FIG. 7 is a diagram of the unit cell of FIG. 6 as viewed from directly above the (0001) plane. In the perspective view of the SiC crystal structure shown in the lower part of FIG. 6, only two layers out of the four layers of the SiC stacked structure shown on the side are extracted and shown.
As shown in FIG. 6, the crystal structure of 4H—SiC can be approximated in a hexagonal system, and four carbon atoms are bonded to one silicon atom. The four carbon atoms are located at the four vertices of a regular tetrahedron with the silicon atom located in the center. Of these four carbon atoms, one silicon atom is located in the <0001> direction with respect to the carbon atom, and the other three carbon atoms are located on the <000-1> side with respect to the silicon atom.

<0001> and <000-1> are along the axial direction of the hexagonal prism, and a surface (the top surface of the hexagonal prism) having the <0001> as a normal line is a (0001) surface (Si surface). On the other hand, the plane (the lower surface of the hexagonal prism) with <000-1> as the normal line is the (000-1) plane (C plane).
In addition, directions perpendicular to <0001> and passing through non-adjacent vertices of a hexagonal note when viewed from directly above the (0001) plane are a1 axis <2-1-10> and a2 axis <−12−10> and a3-axis <−1−120>.

As shown in FIG. 7, the direction passing through the vertex between the a1 axis and the a2 axis is <11-20>, the direction passing through the vertex between the a2 axis and the a3 axis is <−2110>, The direction passing through the vertex between the a3 axis and the a1 axis is <1-210>.
Between each of the six axes passing through the vertices of the hexagonal note, the axis that is inclined at an angle of 30 ° with respect to each of the axes on both sides of the hexagonal note is a1 From <10-10>, <1-100>, <0-110>, <-1010>, <-1100> and <01-10> in the clockwise order from between the axis and <11-20>. is there. Each plane (the side surface of the hexagonal prism) having these axes as normals is a crystal plane perpendicular to the (0001) plane and the (000-1) plane.

Here, in the n ⁺ -type SiC substrate 13 (4H-SiC wafer), basal plane dislocation may exist on the (0001) plane (Si plane) which is a plane perpendicular to the <0001> axis direction. . The basal plane dislocation is a dislocation on the (0001) plane and is a complete dislocation having a Burgers vector in the <11-20> axis direction. As described above, the n ⁺ -type SiC substrate 13 has a predetermined off-angle from the viewpoint of favorably growing the SiC epitaxial layer 14. Accordingly, the basal plane dislocations in the ^{n +} -type SiC substrate 13, the basal plane dislocation structurally converted into threading edge dislocation near the interface between the SiC epitaxial layer 14 and the ^{n +} -type SiC substrate 13, as SiC epitaxial layer 14 are taken over according to the step flow direction (ie, the <11-20> axis direction) which is the growth direction.

  Such a basal plane dislocation causes a planar stacking fault along the <11-20> axis direction during a forward operation (that is, in an ON state), particularly in a device including a pn junction, thereby causing a forward direction dislocation. There is a possibility that the characteristics may be deteriorated (forward-direction energization deterioration). When a current flows in a direction perpendicular to the planar stacking fault, the stacking fault impedes the flow of a forward current. As a result, the electric resistance at the time of the ON operation of the device increases, and the power consumption increases. Therefore, it is necessary to reduce such defects in order to improve the reliability of the semiconductor device.

  The VDMISFET 2 in the semiconductor device 1 has a body diode (parasitic diode) between the source electrode 34 and the drain electrode 36 (between the source and the drain). For example, when the unit cell 11 is formed along the <0001> axis direction, when a forward current flows through the body diode, a stacking fault occurs due to basal plane dislocation, and the stack current causes the forward current flow. Be inhibited. As a result, the characteristics of the body diode fluctuate, leading to a decrease in reliability.

  Therefore, the unit cell 11 is preferably formed along the <11-20> axis direction (the step flow direction which is the growth direction of the SiC epitaxial layer 14). According to this configuration, occurrence of stacking faults due to basal plane dislocation can be suppressed. Further, even if a stacking fault occurs, a forward current can flow in a direction along the stacking fault (that is, the <11-20> axis direction), so that deterioration of the body diode can be suppressed. Thus, a semiconductor device exhibiting good forward characteristics can be provided.

As described above, according to the semiconductor device 1, the n ⁺ type source region 19 and the SiC epitaxial layer 14 have the vertical structure in which the p ⁻ type body region 17 is interposed in the vertical direction. . Further, the gate electrode 10 in the semiconductor device 1 is divided by the cavity 25, and an intermediate insulating film 30 thicker than the gate insulating film 21 is formed in the cavity 25.
Therefore, when the semiconductor device 1 is off (that is, the gate electrode 10 is at 0 V), a voltage (for example, 1200 V) at which the n ⁺ type source region 19 and the SiC epitaxial layer 14 are on the (+) side is applied. Even if the gate electrode 10 and the JFET region 18 do not face each other with the gate insulating film 21 interposed therebetween, the cavity 25 does not become a reference position on the equipotential surface. Therefore, distribution of a relatively high potential equipotential surface in the JFET region 18 immediately below the cavity 25 can be effectively suppressed. In particular, since the equipotential surface of this potential is likely to be distributed such that the central portion of the JFET region 18 becomes the highest, the cavity portion 25 (the intermediate insulating film 30) is formed on the central portion of the JFET region 18 as in the semiconductor device 1. ) Can effectively reduce the application of a high electric field to the JFET region 18.

Further, since the intermediate insulating film 30 thicker than the gate insulating film 21 is formed on the region where the electric field can be reduced, the dielectric breakdown in the JFET region 18 can be effectively suppressed. As a result, it is possible to provide the semiconductor device 1 which has excellent withstand voltage and can be manufactured with high yield.
Further, according to this configuration, since the gate electrode 10 is formed on the channel region 22, there is no hindrance to the ON operation of the VDCMISFET 2. Further, the area of the gate electrode 10 (more specifically, the facing area where the surface of the gate electrode 10 faces the surface of the SiC epitaxial layer 14) can be reduced by the cavity 25. Thereby, the capacitance between the gate electrode 10 and the SiC epitaxial layer 14 can be reduced.

Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIG. FIG. 8 is a flowchart for explaining an example of the manufacturing process of the semiconductor device 1 shown in FIG.
To manufacture the semiconductor device 1, first, an n ⁺ -type SiC substrate 13 is prepared. The n ⁺ type SiC substrate 13 is a 4H-SiC wafer provided with a predetermined off angle. Next, the surface (Si surface) of the n ⁺ -type SiC substrate 13 is formed by an epitaxial growth method such as a CVD (Chemical Vapor Deposition) method or an LPE (Liquid Phase Epitaxy) method. A SiC crystal is grown while introducing an n-type impurity (for example, N (nitrogen)) (step S1). Thus, an n ⁻ -type SiC epitaxial layer 14 is formed on the n ⁺ -type SiC substrate 13.

Next, using a mask having an opening in a portion where p ⁻ type body region 17 (p ⁻ type body connection region 16) is to be formed, p type impurities (for example, Al (aluminum)) are deposited on the surface of SiC epitaxial layer 14. (Step S2). Thus, p ⁻ type body region 17 (p ⁻ type body connection region 16) is formed in the surface layer portion of SiC epitaxial layer 14. In the base layer of the SiC epitaxial layer 14, a drift region that maintains a state after epitaxial growth is formed.

Next, an n-type impurity (for example, P (phosphorus)) is implanted into the p ⁻ -type body region 17 using a mask having an opening in a region where the n ⁺ -type source region 19 is to be formed (step S3). As a result, an n ⁺ type source region 19 is formed in the surface layer of the p ⁻ type body region 17. Next, p-type impurities (for example, Al) are implanted into p ⁻ -type body region 17 using a mask having an opening in a region where p ⁺ -type body contact region 20 is to be formed (step S4). Thereby, p ⁺ type body contact region 20 is formed.

  Next, for example, the SiC epitaxial layer 14 is annealed (heat treated) at 1400 ° C. to 2000 ° C. for 2 to 10 minutes (step S5). As a result, the ions of the n-type impurity and the p-type impurity implanted into the surface portion of the SiC epitaxial layer 14 are activated. The annealing of the SiC epitaxial layer 14 can be performed, for example, by controlling the resistance heating furnace and the high-frequency induction heating furnace at appropriate temperatures.

  Next, the surface of SiC epitaxial layer 14 is thermally oxidized to form gate insulating film 21 covering the entire surface of SiC epitaxial layer 14 (step S6). Next, a polysilicon material is deposited on the SiC epitaxial layer 14 by introducing a p-type impurity (for example, B (boron)) by a CVD method (step S7). Of course, introduction of impurities into the polysilicon material may be performed by ion implantation. Next, unnecessary portions of the deposited polysilicon material are removed by dry etching (step S8). Thereby, the gate electrode 10 having the cavity 25 is formed.

Then, for example, depositing a SiO ₂ containing SiO ₂ or P (phosphorus) ions and B (boron) ions, including P (phosphorus) ions on the SiC epitaxial layer 14 (step S9). Next, SiO ₂ is melted by reflow (for example, 800 ° C. to 1000 ° C.) (Step S10) to fill back the cavity 25 of the gate electrode 10 and to cover the surface of the gate electrode 10 with the interlayer insulating film 26 (PSG). Film or BPSG film) is formed.

  Next, a contact hole 33 is formed by continuously patterning the interlayer insulating film 26 and the gate insulating film 21 (Step S11). Next, for example, Ti, TiN, and Al are sequentially sputtered on interlayer insulating film 26 to form source electrode 34 (step S12). Further, Ti, Ni, Au and Ag are sequentially sputtered on the back surface of the SiC substrate to form a drain electrode 36. Thereafter, the semiconductor device 1 shown in FIG. 1 is obtained by forming the gate pads 3 and the like.

FIG. 9 is a schematic sectional view of a semiconductor device 51 according to the second embodiment of the present invention.
The semiconductor device 51 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that an n ⁺ type source region 59 is formed instead of the n ⁺ type source region 19. The point is that an n ⁺ -type impurity region 52 is formed between adjacent p ⁻ -type body regions 17, and that a gate insulating film 50 is formed instead of the gate insulating film 21. Other configurations are the same as the configuration of the semiconductor device 1 according to the above-described first embodiment. In FIG. 9, portions corresponding to the respective portions shown in FIGS. 1 to 8 are denoted by the same reference numerals, and description thereof will be omitted.

The n ⁺ type source region 59 according to the second embodiment is formed in the same shape and the same depth as the n ⁺ type source region 19 according to the first embodiment. The n ⁺ -type source region 59 has an n-type impurity concentration of, for example, 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²² cm ⁻³ , more preferably 1 × 10 ²⁰ cm ⁻³ to 1 × 10 ²² cm ⁻³ . is there.
The n ⁺ type impurity region 52 is formed in the surface layer of the JFET region 18. More specifically, n ⁺ -type impurity region 52 is formed in a substantially rectangular shape along the stripe direction of gate electrode 10 at the center of JFET region 18. N ⁺ -type impurity region 52 is formed at a position spaced from the boundary between p ⁻ -type body region 17 and JFET region 18. N ⁺ type impurity region 52 is formed at the same depth and concentration as n ⁺ type source region 59.

The gate insulating film 50 according to the second embodiment includes a first region 53 covering the entire region of the JFET region 18, a portion surrounding the n ⁺ -type source region 59 in each of the p ⁻ -type body regions 17, and the n ⁺ -type source region 59. A second region 54 that covers the outer peripheral portion. Each of the first and second regions 53 and 54 of the gate insulating film 50 is selectively formed thicker on a region into which a high concentration impurity is implanted. That is, gate insulating film 50 includes a first portion 50 a in contact with n ⁺ -type impurity region 52, a second portion 50 b in contact with p ⁻ -type body region 17, and a third portion 50 c in contact with n ⁺ -type source region 59.

The lower interface of the first portion 50a (the interface with the n ⁺ -type impurity region 52) and the lower interface of the third portion 50c (the interface with the n ⁺ -type source region 59) are both below the second portion 50b. It is located below the interface (the interface with the p ⁻ -type body region 17) (n ⁺ -type SiC substrate 13 side; a position deeper from the surface of the SiC epitaxial layer 14). The upper interface (interface with the interlayer insulating film 26) of the first portion 50a and the upper interface (interface with the gate electrode 10) of the third portion 50c are both the upper interface (interface with the gate electrode 10) of the second portion 50b. (The gate electrode 10 side; a position farther from the surface of the SiC epitaxial layer 14).

  Thus, the thickness T1 of the first portion 50a and the thickness T3 of the third portion 50c in the gate insulating film 50 are both larger than the thickness T2 of the second portion 50b. More specifically, the thickness T2 of the second portion 50b is, for example, 30 nm or more (for example, about 40 nm). On the other hand, the thicknesses T1 and T3 of the first portion 50a and the third portion 50c are preferably, for example, not less than 2.03 times the thickness T2 of the second portion 50b, for example, about 90 nm. . In this embodiment, the gate insulating film 50 is formed of an oxide film containing nitrogen, for example, a silicon nitride oxide film formed by thermal oxidation using a gas containing nitrogen and oxygen.

Bird's beaks are formed at both ends of the first portion 50a and ends of the third portion 50c on the JFET region 18 side in a direction orthogonal to the stripe direction of the gate electrode 10. On the other hand, no bird's beak is formed at the end of the third portion 50c opposite to the JFET region 18 side in the direction perpendicular to the stripe direction, and the thick portion is flush with the side surface of the interlayer insulating film 26. And is exposed from the contact hole 33. The portion where the interlayer insulating film 26 is in contact with the third portion 50c faces the n ⁺ -type source region 59.

Such a gate insulating film 50 may be obtained by changing the step S3 as follows. That is, the mask having an opening in the region where the n ⁺ type source region 19 is to be formed is changed to a mask having an opening in the region where the n ⁺ type source region 59 and the n ⁺ type impurity region 52 are to be formed. Next, when an n-type impurity (for example, P (phosphorus)) is injected into SiC epitaxial layer 14, the temperature of SiC epitaxial layer 14 is kept at 150 ° C. or lower (for example, room temperature). The temperature of the SiC epitaxial layer 14 is kept at 150 ° C. or lower during the ion implantation in order to prevent the n ⁺ -type source region 59 and the n ⁺ -type impurity region 52 from being crystallized. Thus, a thick gate insulating film 50 can be formed on n ⁺ -type source region 59 and n ⁺ -type impurity region 52 during the thermal oxidation process in step S6.

That is, in the thermal oxidation step of step S6, the gate insulating film 50 made of a silicon nitride oxide (SiN) film is formed by thermal oxidation in an atmosphere containing nitrogen and oxygen (for example, at about 1200 ° C. for half a day to two days). It is formed. As described above, n-type impurity ions are implanted into the n ⁺ -type source region 59 and the n ⁺ -type impurity region 52 so as to have a concentration of 1 × 10 ¹⁹ cm ⁻³ or more. , N ⁺ -type source region 59 and n ⁺ -type impurity region 52 at a low temperature (150 ° C. or lower) at which crystallization does not occur. Therefore, when the gate insulating film 50 is formed by the thermal oxidation process, the thicknesses T1 and T3 of the first portion 50a and the third portion 50c that are in contact with the n ⁺ -type source region 59 and the n ⁺ -type impurity region 52 are locally increased. . As a result, the thicknesses T1 and T3 of the first portion 50a and the third portion 50c are larger than the thickness T2 of the second portion 50b in contact with the p ⁻ -type body region 17.

As described above, in the semiconductor device 51, the thicknesses T1 and T3 of the first portion 50a in contact with the n ⁺ -type impurity region 52 and the third portion 50c in contact with the n ⁺ -type source region 59 in the gate insulating film 50 are p ^- greater than the thickness T2 of the second portion 50b in contact with the mold body region 17. As a result, the thickness of the intermediate insulating film 30 can be further increased, so that dielectric breakdown in the JFET region 18 can be further suppressed.

Further, in the semiconductor device 51, when an electric field is applied to the gate insulating film 50, the electric field in the third portion 50c in contact with the n ⁺ -type source region 59 can be reduced, so that the leak current in the third portion 50c can be suppressed. Therefore, dielectric breakdown at the third portion 50c in contact with the n ⁺ -type source region 59 can be suppressed, so that long-term reliability of the entire gate insulating film 50 can be easily secured. Thereby, the reliability of the whole semiconductor device can be easily secured.

Further, according to the semiconductor device 51, the gate insulating film 50 includes SiN having a higher dielectric constant than SiO ₂ . Therefore, the intermediate insulating film 30 containing Al ₂ O ₃ or SiN can be formed. According to this configuration, the dielectric constant is higher than when the intermediate insulating film 30 includes SiO ₂ , so that the application of a high electric field to the gate insulating film 21 can be further reduced.
Further, since such a gate insulating film 50 can be formed only by devising the layout of the mask, the manufacturing process does not become complicated.

FIG. 10 is a schematic sectional view of a semiconductor device 61 according to the third embodiment of the present invention.
The semiconductor device 61 according to the third embodiment is different from the semiconductor device 1 according to the above-described first embodiment in that a gate electrode 60 is used instead of the gate electrode 10. Other configurations are the same as the configuration of the semiconductor device 1 according to the above-described first embodiment. 10, the same reference numerals are given to the portions corresponding to the respective portions shown in FIGS. 1 to 9 described above, and the description will be omitted.

The gate electrode 60 according to the third embodiment has a chamfer at the upper end and a taper angle of 5 degrees or more. Such a taper angle can be formed only by changing the etching method in step S8. Thereby, in step S9, the interlayer insulating film 26 can be more buried in the cavity 25 of the gate electrode 60.
As described above, the embodiments of the present invention have been described, but the present invention can be embodied in other forms.

  For example, in each of the above-described embodiments, the example in which the cavity 25 is formed in the gate electrodes 10 and 60 along the stripe direction of the gate electrodes 10 and 60 has been described. May be formed at intervals in the stripe direction. Alternatively, a plurality of stripe-shaped cavities 25 may be formed along the stripe direction at intervals.

Further, in each of the above-described embodiments, an example in which the gate electrodes 10 and 60 are formed in a stripe shape has been described. However, the gate electrodes 10 and 60 are arranged in a lattice shape (ladder shape) as shown in FIG. May be.
FIG. 11 is a schematic enlarged plan view of a semiconductor device 81 according to a modification.
The semiconductor device 81 according to the modification differs from the semiconductor device 1 according to the above-described first embodiment in that a matrix-shaped (lattice-shaped) VDCMISFET 72 is formed instead of the striped VDCMISFET 2, and that a stripe is formed. Is that a gate electrode 70 in a lattice shape (ladder shape) is formed instead of the gate electrode 10 in a lattice shape.

Since semiconductor device 81 has a cross-sectional structure equivalent to the cross-sectional structure shown in FIG. 3, only the arrangement of gate electrode 70 and p ⁻ -type body region 77 forming VDMISFET 72 is shown in FIG. The illustration and description of other components are omitted.
As shown in FIG. 11, a plurality of p ⁻ -type body regions 77 are formed in the surface layer portion of SiC epitaxial layer 14. The plurality of p ⁻ -type body regions 77 are arranged in a square matrix at equal intervals in the row and column directions.

Gate electrode 70 is formed so as to straddle the boundary between each p ⁻ -type body region 77 and SiC epitaxial layer 14. A first cavity 75 that divides the gate electrode 70 in the column direction is formed in the gate electrode 70 between the p ⁻ -type body regions 77 adjacent to each other in the row direction. On the other hand, in the gate electrode 70 between the p ⁻ -type body regions 77 adjacent to each other in the column direction, a second cavity portion 76 for dividing the gate electrode 70 in the row direction is selectively formed. Thus, the gate electrode 70 has a configuration formed in a substantially rectangular ring shape in plan view. The gate electrodes 70 adjacent to each other in the column direction are electrically connected to each other via a gate electrode connecting portion 70a.

  The gate electrode connecting portion 70a is formed integrally with each gate electrode 70 adjacent in the column direction at positions at both ends in the longitudinal direction where the second hollow portion 76 extends in the row direction. Thus, a ladder-shaped gate electrode 70 is formed along the column direction. One end and / or the other end in the longitudinal direction of the gate electrode 70 is connected to the gate wiring 6 (see FIG. 1), as in the first embodiment. In the first and second hollow portions 75 and 76, an intermediate insulating film 30 is formed in the same configuration as in the first embodiment.

  In this modification, the example in which the gate electrode connecting portions 70a are formed at both ends in the longitudinal direction of the second hollow portion 76 is shown. However, the second hollow portion 76 is not formed, and The adjacent gate electrodes 70 may be directly connected to each other. Further, in the present modification, an example is shown in which the first cavity 75 that divides the gate electrode 70 in the column direction is formed, but the first cavity 75 is formed in the same manner as the configuration of the second cavity 76. The gate electrode 70 having a lattice shape may be formed by using the structure.

Here, when the first and second cavities 75 and 76 are formed so as to extend over the entire area in the row and column directions without forming the gate electrode connecting portion 70a, the closed annular gate electrode 70 is formed. Therefore, as a result of the gate electrode 70 and the gate wiring 6 being electrically separated, the VDIMSET 72 cannot operate. On the other hand, according to the semiconductor device 81 of the present modification, each annular gate electrode 70 is electrically connected to the gate wiring 6 via the gate electrode connecting portion 70a. Therefore, unlike the case of the first embodiment described above, it is possible to reduce the electric field in the entire region between the p ⁻ type body regions 77 adjacent to each other in the row direction and the column direction (that is, the JFET region 18 (see FIG. 3)). Although not possible, the electric field can be reduced in the JFET region 18 in the entire region in the column direction and a part in the row direction. That is, in a mode in which the gate electrode 70 and the gate wiring 6 are electrically connected, if the first and second cavities 75 and 76 (the intermediate insulating film 30) are formed in the JFET region 18 where an electric field is easily applied. In addition, dielectric breakdown in the JFET region 18 can be suppressed.

Further, in the first and third embodiments described above, the example in which the gate insulating film 21 made of the silicon oxide film (SiO ₂ ) is formed, but the gate insulating film 21 is replaced with Al ₂ O instead of SiO _{2. 3} or SiN. When the gate insulating film 21 is made of Al ₂ O ₃ or SiN, the intermediate insulating film 30 can be formed of Al ₂ O ₃ or SiN. According to this configuration, since the dielectric constant is higher than when the intermediate insulating film 30 is made of SiO ₂ , the electric field in the JFET region 18 can be reduced more effectively.

In the first and third embodiments, the intermediate insulating film 30 may be formed separately from the gate insulating film 21. That is, while the gate insulating film 21 in the region outside the cavity 25 of the gate electrode 10 is formed of SiO ₂ , the connection portion of the intermediate insulating film 30 with the JFET region 18 is formed of Al ₂ O ₃ or SiN. Good.
Further, in the first and third embodiments described above, while the connection portion between the intermediate insulating film 30 and the JFET region 18 is formed by the gate insulating film 21, the cavity 25 of the gate electrode 10 is formed by SiO ₂ , Al ₂ O ₃ or after backfilling with SiN, an interlayer insulating film 26 may be further formed.

Further, in each of the above-described embodiments, an example in which the interlayer insulating film 26 including only one layer is formed has been described, but the interlayer insulating film 26 may of course include a plurality of insulating material films (SiO ₂ , Al ₂ O ₃ , Alternatively, it may have a laminated structure in which SiN) is laminated over a plurality of cycles.
In each of the above-described embodiments, the interlayer insulating film 26 formed on the gate insulating film 21 in the cavity 25 has a thickness substantially equal to that of the interlayer insulating film 26 formed so as to cover the gate electrode 10. Although the example described above has been described, they may be formed with different thicknesses.

Further, in each of the above-described embodiments, the conductivity type of each semiconductor portion of the semiconductor device 1 can be inverted to form a p-type VDCMISFET. That is, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.
Further, in each of the embodiments described above, the example in which the VDCMISFET 2 is formed in the active region 4 has been described. However, instead of the n ⁺ -type SiC substrate 13 (drain region), a p ⁺ -type SiC substrate (p ⁺ -type collector region) is used. By adopting it, an IGBT (Insulated Gate Bipolar Transistor) may be formed. In this case, the source electrode 34 of the VDMISFET 2 corresponds to the emitter electrode of the IGBT.

  The semiconductor devices 1, 51, 61, and 81 of the present invention constitute a drive circuit for driving an electric motor used as a power source of, for example, an electric vehicle (including a hybrid vehicle), a train, and an industrial robot. It can be incorporated in a power module used for an inverter circuit. Further, the present invention can be incorporated in a power module used for an inverter circuit that converts power generated by a solar cell, a wind power generator, or another power generation device (particularly, a private power generation device) so as to match power of a commercial power supply.

Hereinafter, examples of features extracted from the specification and the drawings will be described.
[Item 1] An SiC semiconductor layer of a first conductivity type, a plurality of body regions of a second conductivity type formed at intervals in a surface layer portion of the SiC semiconductor layer, and a surface layer portion of each of the body regions. A first conductivity type source region formed at an interval from the periphery of the body region; and a gate formed at a channel region formed over the plurality of body regions and between the periphery of each body region and the source region. A gate electrode opposing the insulating film and selectively separated by a cavity in an intermediate region between the adjacent body regions; and an intermediate insulating film formed in the cavity and having a thickness greater than the gate insulating film. And a semiconductor device.

According to this semiconductor device, the source region and the region that can function as the drain in the SiC semiconductor layer have a vertical structure in which the body region is interposed in the vertical direction. Further, the gate electrode is divided by a cavity, and an intermediate insulating film thicker than the gate insulating film is formed in the cavity.
Therefore, even when a voltage (for example, 1200 V) that causes the source region and the SiC semiconductor layer to be on the (+) side is applied in a state where the semiconductor device is off (that is, a state where the gate electrode is at 0 V), the cavity portion is Since there is no gate electrode, the cavity does not become a reference position on the equipotential surface.

  Thereby, the distribution of the equipotential surface of the potential in the intermediate region can be changed. As a result, the application of a high electric field to the intermediate region can be reduced. Further, since the thick intermediate insulating film is formed in the region where the electric field can be reduced, dielectric breakdown in the intermediate region can be effectively suppressed. As a result, it is possible to provide a semiconductor device which has excellent withstand voltage and can be manufactured with high yield.

  Further, according to this semiconductor device, since the gate electrode is formed on the channel region, the ON operation of the MISFET (Metal Insulator Field Effect Transistor) is not hindered. Furthermore, the area of the gate electrode (more specifically, the facing area where the surface of the gate electrode faces the surface of the SiC semiconductor layer) can be reduced by the cavity. Thereby, the capacitance between the SiC semiconductor layer and the gate electrode can be reduced.

[Item 2] The semiconductor device according to item 1, wherein the cavity of the gate electrode is formed on a central portion of the intermediate region.
According to this semiconductor device, the intermediate insulating film is formed on the central portion of the intermediate region. The equipotential surface of the potential tends to be highest at the center of the intermediate region. Therefore, by forming the intermediate insulating film on the central portion of the intermediate region where the electric field is most likely to be highest, dielectric breakdown in the intermediate region can be effectively suppressed.

[Claim 3] The plurality of body regions are formed in a stripe shape having one end and the other end, and the gate electrode is connected to the adjacent body region at the one end and / or the other end of the body region. 3. The semiconductor device according to item 1 or 2, which straddles.
According to this semiconductor device, the intermediate insulating film is formed along the stripe direction of the body region (intermediate region). Therefore, the distribution of the equipotential surface of the potential in the intermediate region can be changed along the stripe direction of the intermediate region. This can reduce the application of an electric field over a wide range along the stripe direction in the intermediate region. As a result, dielectric breakdown in the intermediate region can be further suppressed.

[Item 4] The method according to any one of Items 1 to 3, wherein the cavity of the gate electrode is formed so as to fit inside the intermediate region at an interval from a boundary between each of the body regions and the intermediate region. The semiconductor device according to claim 1.
According to this semiconductor device, the gate electrode can reliably face the source region, the body region, and the SiC semiconductor layer. Therefore, the gate electrode and the channel region can be surely opposed to each other, and the ON operation of the MISFET can be further improved.

[Item 5] The semiconductor device according to any one of Items 1 to 4, wherein the intermediate region has a width of 0.1 μm to 50 μm.
According to this semiconductor device, it is possible to realize a good resistance value while suppressing distribution of a high potential equipotential surface in the intermediate region. As the width of the intermediate region increases, equipotential surfaces having a higher potential tend to be distributed in the intermediate region. On the other hand, if the intermediate region is too narrow, the resistance value of the intermediate region increases. Therefore, by forming the intermediate region having a width of 0.1 μm to 50 μm, a good resistance value can be realized while suppressing the distribution of the high potential equipotential surface in the intermediate region.

[Item 6] The semiconductor device according to any one of Items 1 to 5, wherein the intermediate insulating film has a thickness twice or more the thickness of the gate insulating film. According to this semiconductor device, dielectric breakdown in the intermediate region can be further suppressed.
[Item 7] The semiconductor device according to any one of Items 1 to 6, wherein the intermediate insulating film includes a SiO ₂ film. According to this semiconductor device, since the SiO ₂ film is excellently melted during reflowing, it is possible to embed the SiO ₂ film better in the cavity.

[Item 8] The semiconductor device according to item 7, wherein the SiO ₂ film contains P (phosphorus) ions. According to this semiconductor device, the intermediate insulating film includes a PSG (Phosphorus Silicon Glass) film. The PSG film melts well at the time of reflow (for example, about 1000 ° C.). Therefore, the PSG film can be satisfactorily embedded in the cavity.
[Item 9] The semiconductor device according to item 8, wherein the SiO ₂ film further contains B (boron) ions. According to this semiconductor device, the intermediate insulating film includes a BPSG (Boron Phosphorus Silicon Glass) film. The BPSG film melts at a lower temperature (for example, about 800 ° C.) than the PSG film. Therefore, the BPSG film can be more buried in the cavity.

[Claim 10] The intermediate insulating film includes a high dielectric material film dielectric constant than SiO _2, the semiconductor device according to any one of claims 1 to 6. According to this semiconductor device, dielectric breakdown in the intermediate region can be further suppressed.
[Item 11] The semiconductor device according to item 10, wherein the insulating material film is made of Al ₂ O ₃ or SiN.

[Item 12] The semiconductor device according to any one of Items 1 to 6, wherein the insulating material film includes a stacked structure in which a SiO ₂ film and an Al ₂ O ₃ film are stacked in this order.
According to this configuration, since the portion (connection interface) where the SiC semiconductor layer and the intermediate insulating film are in contact with each other is formed of the SiO ₂ film, the channel mobility of carriers flowing through the channel region can be improved. Meanwhile, since the on the SiO ₂ film _{an Al} 2 _{O 3} film having a dielectric constant higher than that of the SiO ₂ film is formed, a high dielectric constant can be secured in the _{the Al} 2 _{O 3} film. Thereby, dielectric breakdown in the intermediate region can be further suppressed. Note that the SiO ₂ film and the Al ₂ O ₃ film may be stacked over a plurality of cycles.

[Item 13] The semiconductor device according to any one of Items 1 to 6, wherein the intermediate insulating film has a stacked structure in which a SiO ₂ film and a SiN film are stacked in this order.
According to this configuration, since the portion (connection interface) where the SiC semiconductor layer and the intermediate insulating film are in contact with each other is formed of the SiO ₂ film, the channel mobility of carriers flowing through the channel region can be improved. Meanwhile, since the on SiO ₂ film are formed SiN film having a dielectric constant higher than that of the SiO ₂ film can ensure a high dielectric constant in the SiN film. Thereby, dielectric breakdown in the intermediate region can be further suppressed. Note that the SiO ₂ film and the SiN film may be stacked over a plurality of cycles.

[Item 14] The semiconductor device according to any one of Items 1 to 13, wherein the gate electrode is made of polysilicon.
[Item 15] The semiconductor device according to item 14, wherein the polysilicon contains B (boron) ions. According to this semiconductor device, the threshold voltage (V _{GS (th)} ) of the gate voltage required for forming a channel can be reduced.

[Item 16] The semiconductor device according to any one of Items 1 to 13, wherein the gate electrode is made of a metal material. According to this semiconductor device, the resistance value of the gate electrode can be made smaller than when the gate electrode is formed using polysilicon. As a result, the thickness of the gate electrode can be further reduced, so that the intermediate insulating film can be satisfactorily embedded in the cavity.
[Item 17] The semiconductor device according to item 16, wherein the metal material is made of Al, Cu, or AlCu.

[Item 18] The semiconductor device according to any one of Items 1 to 17, wherein the gate electrode has a thickness of 2 μm or less. According to this semiconductor device, the intermediate insulating film can be satisfactorily embedded in the cavity.
[Item 19] The semiconductor device according to any one of Items 1 to 18, wherein each of the body regions is formed along the <11-20> axis direction.

[Item 20] The gate insulating film has a first thickness on the channel region, and has a second thickness on the source region larger than the first thickness. 20. The semiconductor device according to any one of claims 19 to 19.
According to this semiconductor device, when an electric field is applied to the gate insulating film, the electric field in the gate insulating film in contact with the source region can be effectively reduced. Thereby, dielectric breakdown of the gate insulating film on the source region can be effectively suppressed.

[Item 21] The semiconductor device according to item 20, wherein the second thickness of the gate insulating film is at least 2.03 times the first thickness.
According to this semiconductor device, long-term reliability of the gate insulating film in contact with the source region can be improved. Thus, the long-term reliability of the entire gate insulating film can be further improved by the long-term reliability of the gate insulating film in contact with the source region.

[Item 22] The semiconductor device according to any one of Items 1 to 21, wherein the gate insulating film has a thickness of 1 μm or less on the channel region.
[Item 23] The semiconductor device further includes an interlayer insulating film formed on the SiC semiconductor layer so as to cover the gate electrode and buried in the cavity, and the intermediate insulating film uses a buried portion of the interlayer insulating film. 23. The semiconductor device according to any one of Items 1 to 22, which is formed by:

According to this semiconductor device, the intermediate insulating film can be formed using the step of forming the interlayer insulating film. Therefore, a semiconductor device that can be easily manufactured can be provided.
[Item 24] The semiconductor device according to item 23, wherein a filling amount of the interlayer insulating film in the cavity is substantially equal to a thickness of a portion of the interlayer insulating film on the gate electrode.
[Item 25] The semiconductor device according to any one of Items 1 to 24, wherein a taper angle of 5 degrees or more is formed at an upper end portion of the gate electrode. According to this semiconductor device, the insulating film can be satisfactorily embedded in the cavity.

  In addition, various design changes can be made within the scope of the matters described in the claims.

REFERENCE SIGNS LIST 1 semiconductor device 10 gate electrode 12 SiC semiconductor layer 17 p ⁻ type body region 18 JFET region 19 n ⁺ source type region 21 gate insulating film 22 channel region 25 cavity 26 interlayer insulating film 30 intermediate insulating film 50 gate insulating film 51 semiconductor Device 59 n ⁺ type source type region 60 Gate electrode 61 Semiconductor device 70 Gate electrode 75 First cavity 76 Second cavity 77 p ⁻ Body region 81 Semiconductor device L Channel length T1 Film thickness T2 Film thickness T3 Film thickness WD Width WJ width θ Off angle

Claims (10)

A first conductivity type semiconductor layer having a main surface and including a wide band gap semiconductor;
A plurality of second conductivity type body regions formed at intervals on the surface layer portion of the main surface of the semiconductor layer;
A first conductivity type source region (or emitter region) formed in a surface layer of the body region;
A gate insulating film formed on the main surface of the semiconductor layer;
A gate electrode formed on the gate insulating film and having an end above the source region (or the emitter region) and above an intermediate region between the body regions of the second conductivity type adjacent to each other; ,
The semiconductor device, wherein the gate insulating film has a greater thickness at the end of the gate electrode than at a channel region below the gate electrode.   2. The semiconductor device according to claim 1, wherein the gate insulating film has a portion where the thickness of the gate insulating film gradually becomes larger than a thickness of a channel region formed by the gate electrode as approaching the end of the gate electrode. 3.   3. The semiconductor device according to claim 1, wherein the gate insulating film is thicker on the semiconductor layer side in an intermediate region. 4.   4. The semiconductor device according to claim 1, wherein the gate insulating film has a thickness in the channel region of 30 nm or more, and a thickness of the end portion is 2.03 times or more. 5.   The JFET (Junction Field Effect Transistor) region serving as the intermediate region between the body regions of the second conductivity type adjacent to each other is located at a position spaced from a boundary between the body region and the JFET region in a surface layer portion of the JFET region. The semiconductor device according to claim 1, further comprising a first conductivity type impurity region formed at the same depth and concentration as the one conductivity type source region (or emitter region).   The gate insulating film includes a first region covering an entire region of the JFET region, a portion surrounding the source region and a second region covering an outer peripheral portion of the source region, and is in contact with the first conductivity type impurity region. The thickness of the third portion in contact with the first portion and the source region (or the emitter region) of the first conductivity type is greater than the thickness of the second portion in contact with the body region of the second conductivity type. The semiconductor device according to claim 5.   7. The gate electrode according to claim 1, wherein the gate electrode has an overlap portion extending from a region facing the body region to a region facing the source region (or the emitter region). 8. Semiconductor device.   The semiconductor device according to claim 7, wherein the overlap portion has a width of 0.05 μm to 1 μm.   The gate electrode includes a first gate wiring (6, 7) connected to a plurality of contacts (5) formed on the periphery of the long side and the short side (5a, 5b) of the gate pad (3). The semiconductor device according to claim 1, wherein the semiconductor device is connected through two gate wirings (6, 8).   The semiconductor device according to claim 1, wherein the semiconductor layer is a SiC semiconductor layer.

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