JP2011166003A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of forming a MOSFET element to be operated normally by compensating a B (boron) sucking out phenomenon and a P (phosphorus) pile-up phenomenon while ensuring reliability of a gate oxide film. <P>SOLUTION: A p-type diffusion layer 10 is formed on the surface layer of an n-type diffusion layer 9. The B (boron) sucking out phenomenon and the P (phosphorus) pile-up phenomenon generated by formation of a gate oxide film 11 thereafter are compensated by carrying out a heat treatment of 900°C or higher. The p-type diffusion layer 10 surface that has become the n-type is returned to the p-type. Thereby, a method for manufacturing a semiconductor device having a MOSFET element to be operated normally while ensuring the reliability of the gate oxide film 11 is provided. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having a MOSFET element or the like.

  In recent years, not only low withstand voltage elements of about several tens of volts, but also high-voltage elements of a few hundred hundred V class are built in and integrated, and semiconductor devices having MOSFET elements with high functionality have been widely used. ing.

  FIG. 18 is a cross-sectional view of a main part of a conventional n-channel MOSFET device. A deep n-type diffusion layer 2 is formed on the p-type silicon substrate 1, and a p-type diffusion layer 3 shallower than the n-type diffusion layer 2 is formed on the n-type diffusion layer 2. A gate oxide film 4 is formed on the p-type diffusion layer 3 and the n-type diffusion layer 2, and a gate electrode 5 is formed thereon.

  Since the n-type diffusion layer 2 is sandwiched between the p-type silicon substrate 1 and the p-type diffusion layer 3, the p-type silicon substrate 1 and the p-type diffusion layer 3 are joined and separated from each other by the n-type diffusion layer 2, Electrically isolated.

  Here, the p-type impurity forming the p-type diffusion layer 3 is B (boron) or BF2 (boron difluoride), and the n-type impurity forming the n-type diffusion layer 2 is P (phosphorus) or As. (Arsenic) is generally used, and the deep n-type diffusion layer 2 is a diffusion layer called a well. The thickness of the gate oxide film 4 is typically about several tens of nanometers, and the material of the gate electrode 5 is generally polysilicon doped with high-concentration n-type impurities.

In addition, the n ⁺ source layer 6 and the n ⁺ drain layer 7 are formed using the gate electrode 5 as a mask, and the source electrode and the drain electrode are formed as an extraction electrode (not shown), for example, of an aluminum alloy material. .

Further, Patent Document 1 describes that in order to prevent boron from being sucked into the gate oxide film, the gate oxide film is nitrided, boron is ion-implanted through the gate insulating film, and heat treatment is performed by lamp annealing. Yes.
Patent Document 2 describes forming a p-type layer at a location where phosphorus is piled up.

JP-A-8-51205 JP 2002-222869 A

  Normally, in a semiconductor device incorporating a low breakdown voltage element and a high breakdown voltage element, the structure of the MOSFET element is improved so that the low breakdown voltage and the high breakdown voltage element are formed in the same chip. For the purpose of reducing the size, a high voltage is often applied directly to the gate electrode of the high breakdown voltage element or the gate electrode of the MOSFET element constituting the control circuit, and the gate insulating film under the gate electrode is formed thick.

  The gate insulating film of a MOSFET element is typically a gate oxide film formed by thermal oxidation of a silicon substrate from the viewpoint of ease of assembly of the manufacturing process, withstand voltage, quality, and reliability. The following problems occur when the thickness is increased.

  In the region of the silicon substrate in which the MOSFET element is formed, a diffusion layer (for example, the p-type diffusion layer 3 in FIG. 9) into which n-type and p-type impurities are mixed is usually formed. When a gate oxide film is formed on this diffusion layer by thermal oxidation, n-type impurities represented by P (phosphorus), As (arsenic), etc., are piled up (segregated) to cause an interface between the gate oxide film and the silicon substrate. The p-type impurities typified by B (boron), BF2 (boron difluoride), and the like are locally absorbed at the silicon substrate side interface, and the gate oxide film and the silicon substrate are absorbed by suction. A phenomenon occurs in which the concentration is lowered at the interface on the silicon substrate side of the interface.

  This tendency becomes more prominent as the thickness of the gate oxide film increases. In particular, a thick gate oxide film is formed using a pyro-oxidation method or a steam oxidation method in which oxygen gas and hydrogen gas are burned to perform thermal oxidation. The case becomes noticeable. In the case of dry oxidation in which the gate oxide film is relatively thin and thermal oxidation is performed in an atmosphere containing hydrogen-free oxygen gas or oxygen gas mixed with an inert gas such as nitrogen, the same phenomenon occurs. Although it occurs, the degree is known to be minor.

FIG. 19 is a cross-sectional view of the main part manufacturing process when a thick gate oxide film 4a is formed on the p-type diffusion layer 3 formed on the surface layer of the n-type diffusion layer 2.
In the case of forming the thick gate oxide film 4a, pyro-oxidation that provides a high oxidation rate is used from the viewpoint of throughput. In this case, both the thickening of the gate oxide film 4a and the application of the pyro-oxidation method are used. Since the phenomenon works in a direction in which the phenomenon becomes significant, control of these impurities is important when manufacturing a MOSFET element using the thick gate oxide film 4a.

  20 and 21 are diagrams in which the distribution of impurities immediately below the gate oxide film 4a is investigated by SIMS (Secondary Ion Mass Spectrometry) analysis, and FIG. 20 shows the diffusion depth on the Y1-Y1 line. FIG. 21 is an enlarged view of the vicinity of the surface of FIG.

  Immediately below the gate oxide film 4a, P (phosphorus) forming the n-type diffusion layer 2 locally piles up on the silicon substrate side near the interface between the gate oxide film 4a and the silicon substrate (p-type diffusion layer 3). The P (phosphorus) concentration rises steeply on the surface. On the other hand, B (boron) forming the p-type diffusion layer 3 is gradually reduced in concentration immediately below the gate oxide film 4a due to the sucking phenomenon.

As shown in FIG. 21, the p-type diffusion layer 3 in the vicinity of the vicinity of the interface under the gate oxide film 4a, P by pile-up phenomenon (phosphorus), n-type to n ⁺ layer (n-type channel) is formed The n ⁺ source layer 6 and the n ⁺ drain layer 7 are connected by the n ⁺ layer. Therefore, the n ⁺ source layer 6 and the n ⁺ drain layer 7 are always short-circuited, and even if a gate signal is given to the gate electrode 5, the MOSFET element remains on and the switch function of the MOSFET element disappears.

  As a method for preventing this, the amount of P (phosphorus) introduced is decreased in anticipation of the concentration increase due to the pile-up phenomenon of P (phosphorus) and the concentration decrease due to the suction phenomenon of B (boron), or B ( There is a method for increasing the amount of boron introduced.

  FIG. 22 is a diagram showing the concentration difference between the gate oxide film formation temperature of P (phosphorus), which is an n-type impurity, and B (boron), which is a p-type impurity, generated in the process of forming the gate oxide film 4a. The concentration difference is P (phosphorus) concentration / B (boron) concentration. As an initial condition, P (phosphorus) and B (boron) before forming the gate oxide film 4a are introduced into the silicon substrate with the same dose.

  From FIG. 22, when the formation temperature of the gate oxide film 4a is 900 ° C., the concentration difference near the surface is 25 times, at 1100 ° C. the concentration difference is 10 times, and further at 1200 ° C., the concentration difference is 5 times. That is, it can be seen that the concentration difference decreases as the formation temperature of the gate oxide film 4a increases. In the range of the formation temperature from 900 ° C. to 1200 ° C., the vicinity of the surface of the silicon substrate is n-type.

Therefore, if the p-type impurity is introduced more than 25 times the n-type impurity, the n-type near the surface can be eliminated even when the formation temperature of the gate oxide film 4a is as low as 900 ° C. However, a high introduction amount of B (boron) is more than 25 times larger than the appropriate introduction amount of P (phosphorus) in the n-type diffusion layer 2 (for example, the dose amount is 2 × 10 ¹³ cm ⁻² ). When the p-type diffusion layer 3 is formed, the profile of the p-type diffusion layer becomes steep at the pn junction between the p-type diffusion layer 3 and the n-type diffusion layer 2, and the breakdown voltage decreases. Further, if B (boron) is introduced excessively, the gate threshold value is increased, and further, the channel resistance is increased, so that the device characteristics are deteriorated and the concentration of the p-type diffusion layer 3 cannot be significantly increased. Therefore, the degree of freedom in device design (diffusion profile design, etc.) is reduced.

On the other hand, the introduction amount of P (phosphorus) in the n-type diffusion layer 2 is 1 with respect to the appropriate introduction amount of B (boron) in the p-type diffusion layer 3 (for example, the dose amount is 4 × 10 ¹³ cm ⁻² ). / 25 or less, the impurity concentration of the n-type diffusion layer 2 becomes too low, and the n-type diffusion layer 2 sandwiched between the p-type silicon substrate 1 and the p-type diffusion layer 3 is likely to punch through and the breakdown voltage is reduced. .

  Another method is to introduce B (boron) by ion implantation through the gate oxide film 4a after forming the gate oxide film 4a for concentration compensation. However, in this case, since the gate oxide film 4a is damaged in the process of introducing B (boron), the quality and reliability of the gate oxide film 4a of the MOSFET element may be lowered.

  These problems are prominent when the diffusion layer forming the n-channel MOSFET element contains n-type impurities and p-type impurities having different conductivity types, and the concentration difference between them is small. Further, when the thick gate oxide film 4a is formed, the above-described sucking phenomenon and pile-up phenomenon are further accelerated, which becomes remarkable.

In Patent Document 1 and Patent Document 2 described above, there is no description about redistribution of impurities by performing heat treatment after forming the gate oxide film.
In the case of a p-channel MOSFET element, the surface concentration of the n-type diffusion layer that is the channel layer becomes too high due to the pile-up phenomenon, and the gate threshold voltage is abnormally increased, thereby causing normal operation. It becomes impossible.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and compensate for the B (boron) sucking phenomenon and the P (phosphorus) pileup phenomenon while ensuring the reliability of the gate oxide film, and operating normally. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can form the above.

  In order to achieve the above object, according to the first aspect of the present invention, in the method of manufacturing a semiconductor device having a MOS gate structure, the surface layer of the first diffusion layer of the first conductivity type is formed. Forming a second diffusion layer of the second conductivity type; forming a gate oxide film on the second diffusion layer at a first processing temperature; and a second processing temperature higher than the first processing temperature. And a step of forming a gate electrode on the gate oxide film after the heat treatment step, and the amount of the second conductivity type impurity introduced into the second diffusion layer is the first diffusion layer of the first diffusion layer. A manufacturing method of a semiconductor device higher than the introduction amount of the conductive impurities is provided.

  According to the second aspect of the present invention, in the method of manufacturing a semiconductor device having a MOS gate structure, a step of forming a p-type diffusion layer on the surface layer of the n-type diffusion layer, and the p Forming a gate oxide film on the mold diffusion layer at a first processing temperature; performing a heat treatment at a second processing temperature higher than the first processing temperature; and forming the gate oxide film on the gate oxide film after the heat treatment step Forming a gate electrode, and when the first processing temperature is T ° C. and the amount of p-type impurities introduced is K times the amount of n-type impurities introduced, the value of K is 1 <K ≦ − A semiconductor device manufacturing method of 0.075T + 92.5 is adopted.

  According to the invention described in claim 3 of the claims, in the invention described in claim 1 or 2, the first treatment temperature is 900 ° C. or more and 1100 ° C. or less, and the second treatment is performed. The temperature is preferably 1000 ° C. or higher and 1150 ° C. or lower.

According to the invention described in claim 4 of the claims, in the invention described in claim 1 or 2, the thickness of the gate oxide film is preferably 50 nm or more and 600 nm or less.
Further, according to the invention described in claim 5, in the invention described in claim 1 or 2, the thermal oxidation is performed by introducing oxygen gas, dry oxidation, oxygen gas and hydrogen gas. Pyro-oxidation performed by burning the gas or steam oxidation is preferable.

  According to the invention described in claim 6 of the claims, in the invention described in claim 1 or 2, the thermal oxidation step and the heat treatment step may be continuously performed in the same apparatus.

According to the present invention, the following effects can be obtained.
First, after forming a gate oxide film by thermal oxidation (thermal oxidation at a first processing temperature), heat treatment is performed at a second processing temperature higher than the first processing temperature, thereby forming a gate oxide film. In the process, P (phosphorus) piled up and B (boron) sucked out are redistributed by thermal diffusion, and the distribution is made uniform in a direction to improve the local concentration distribution bias.

  The 1st process temperature at that time shall be the range of 900 to 1100 degreeC, and the 2nd process temperature shall be the range of 1000 to 1150 degreeC. Further, when the first treatment temperature is T ° C. and the introduction amount (dose amount) of p-type impurity (boron) is K times the introduction amount (dose amount) of n-type impurity (phosphorus), the value of K is 1 <K ≦ −0.075T + 92.5.

  As a result, even when a thick gate oxide film is formed, or when a MOSFET element having a high P (phosphorus) concentration that piles up immediately below the gate oxide film is manufactured, n-type near the silicon substrate interface is avoided. Thus, a semiconductor device having an n-channel MOSFET element that operates normally can be manufactured. In addition, since the range of manufacturing conditions for normal operation is widened, the degree of freedom in device design can be increased. Furthermore, since the range of manufacturing conditions is expanded, it becomes possible to manufacture MOSFET devices with higher functions.

Second, only the heat treatment is performed to compensate for the deviation in concentration distribution, and no ion implantation is performed, so that the gate oxide film is not damaged. This ensures the quality and reliability of the gate oxide film.
Third, the throughput and productivity can be improved because the formation of the gate oxide film and the heat treatment for uniforming the bias of the impurity concentration distribution caused by the formation of the gate oxide film can be continuously performed with the same apparatus. Can be achieved.

  Fourth, it is possible to manufacture a semiconductor device having a p-channel MOSFET element that operates normally by reducing the surface concentration of the channel layer of the p-channel MOSFET element to optimize the gate threshold voltage.

It is principal part manufacturing process sectional drawing of the semiconductor device of one Example of this invention. FIG. 2 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the embodiment of the invention, following FIG. 1; FIG. 3 is a main-portion manufacturing process cross-sectional view of the semiconductor device of the embodiment of the invention, following FIG. 2; FIG. 4 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the embodiment of the invention, following FIG. 3; FIG. 5 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the embodiment of the invention, following FIG. 4; FIG. 6 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the embodiment of the invention, following FIG. 5; FIG. 7 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the embodiment of the invention, following FIG. 6; It is a figure which shows the area | region which prevents n conversion by this invention. It is a figure which shows the impurity concentration distribution after heat-processing at 2nd process temperature. It is principal part sectional drawing of the high voltage | pressure-resistant MOSFET of this invention. It is principal part manufacturing process sectional drawing of the semiconductor device of one Example of this invention. FIG. 12 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the embodiment of the invention, following FIG. 11; FIG. 13 is a main-portion manufacturing process cross-sectional view of the semiconductor device of one embodiment of the present invention, following FIG. 12; FIG. 14 is a main-portion manufacturing process cross-sectional view of the semiconductor device of the embodiment of the invention, following FIG. 13; FIG. 15 is a main-portion manufacturing process cross-sectional view of the semiconductor device of one embodiment of the present invention, following FIG. 14; FIG. 16 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the embodiment of the invention, following FIG. 15; FIG. 17 is a main-portion manufacturing process cross-sectional view of the semiconductor device of the embodiment of the invention, following FIG. 16; It is principal part sectional drawing of the conventional MOSFET element. FIG. 6 is a cross-sectional view of a main part manufacturing process when a thick gate oxide film 4a is formed on a p-type diffusion layer 3 formed on a surface layer of an n-type diffusion layer 2; It is the impurity concentration distribution map of the diffusion depth direction on the Y1-Y1 line right under the gate oxide film 4 investigated by SIMS analysis. It is an enlarged view of the surface vicinity of FIG. It is a figure which shows the density | concentration difference with respect to the formation temperature of P (phosphorus) and B (boron) which arise in the formation process of the gate oxide film 4a.

  Embodiments will be described in the following examples.

1 to 7 are cross-sectional views showing a main part manufacturing process showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of processes. The figure shows the location of the n-channel MOSFET device.
For the p-type semiconductor substrate 8 (p-type silicon substrate) containing the p-type impurity, for example, ion implantation of P (phosphorus) that is an n-type impurity is performed at 2 × 10 ¹³ cm through a mask such as a resist. ^A deep n-type diffusion layer 9 is formed by performing thermal diffusion with an introduction amount of ^-2 (dose amount) (FIG. 1).

Next, ion implantation of B (boron), which is a p-type impurity, is performed again through a mask such as a resist with an introduction amount (dose amount) of 5 × 10 ¹³ cm ⁻² , and thermal diffusion is performed. Then, a p-type diffusion layer 10 having a shallower depth than the n-type diffusion layer 9 is formed (FIG. 2).

  Here, in the present invention, it is not always necessary to provide a difference in concentration so that the concentration of the p-type impurity exceeds the concentration of the n-type impurity in anticipation of pile-up of the n-type impurity and suction of the p-type impurity. However, when the first processing temperature is set to 900 ° C. in the next gate oxide film forming step, the n-type impurity concentration is 25 times the p-type impurity concentration in the surface layer of the silicon substrate as can be seen from FIG. Therefore, if the introduction amount of the p-type impurity is set to be more than 25 times the introduction amount of the n-type impurity at the maximum, if there is no fluctuation in the first processing temperature, the p-type diffusion is performed in the next oxidation step. Although the layer 10 does not become n-type, as described above, the p-type diffusion layer has a steep profile at the pn junction between the p-type diffusion layer 3 and the n-type diffusion layer 2 and the breakdown voltage decreases. Further, if B (boron) is introduced excessively, the gate threshold value is increased, and further, the channel resistance is increased, so that the device characteristics are deteriorated and the concentration of the p-type diffusion layer 3 cannot be significantly increased. Therefore, the degree of freedom in device design (diffusion profile design, etc.) is reduced.

On the other hand, the introduction amount of P (phosphorus) in the n-type diffusion layer 2 (for example, 1 ×) with respect to the appropriate introduction amount of B (boron) in the p-type diffusion layer 3 (for example, 5 × 10 ¹³ cm ⁻³ ). 10 ¹³ cm ⁻³ or less), the impurity concentration of the n-type diffusion layer 2 becomes too low, and the n-type diffusion layer 2 sandwiched between the p-type silicon substrate 1 and the p-type diffusion layer 3 punches through. It becomes easier and the pressure resistance decreases.

  On the other hand, in the present invention, even when the introduction amount of the p-type impurity is substantially equal to the introduction amount of the n-type impurity, the n-type of the p-type diffusion layer 10 is performed by performing heat treatment at the second treatment temperature described later. Is eliminated. When the first processing temperature is 900 ° C., the amount of p-type impurities introduced is set to 25 times or less of the amount of n-type impurities introduced, and when the first processing temperature is 1100 ° C. In this case, the amount of introduction of p-type impurities is 10 times or less than the amount of introduction of n-type impurities, so that the degree of freedom in device design and device performance are not reduced. The n-type conversion of the p-type diffusion layer 10 is eliminated by the heat treatment at the processing temperature of 2.

FIG. 8 shows the relationship between the first treatment temperature T and the impurity introduction ratio K.
When the first treatment temperature is T ° C. and the amount of p-type impurities introduced is K times the amount of n-type impurities introduced, from FIG. 8, the value of K is in the range of 900 ° C. ≦ T ≦ 1100 ° C. Even in the region represented by 1 <K ≦ −0.075T + 92.5 (indicated by hatching), the degree of freedom in element design and the decrease in element performance are not caused. The n-type conversion of the p-type diffusion layer 10 is eliminated by the heat treatment at the above processing temperature.

Next, thermal oxidation is performed at the first processing temperature to grow the gate oxide film 11 (FIG. 3).
Here, the first treatment temperature is preferably 900 ° C. to 1100 ° C., and the thickness of the gate oxide film 11 is preferably 50 nm to 600 nm. If the first treatment temperature is less than 900 ° C., the growth rate of the oxide film is slow, and it takes too much time to form the gate oxide film thickness of the present invention, which is not practical. Further, if the temperature exceeds 1100 ° C., the oxide film softens and fluidizes, which may induce interface states, defects, and the like in the gate oxide film, which is not preferable as a condition for forming the gate oxide film. When the thickness of the gate oxide film 11 is as thin as less than 50 nm, the effect of using the present invention is reduced in addition to the low breakdown voltage of the gate oxide film required for the circuit configuration. If the thickness exceeds 600 nm, the influence of the gate oxide film thickness on the threshold voltage at which the MOSFET element is turned on becomes dominant, so that the threshold voltage increases and becomes impractical for circuit operation.

  As for the thermal oxidation method, pyro-oxidation is preferable from the viewpoint of throughput and productivity, and the effect of using the production method of the present invention is great, but the same applies when thermal oxidation is performed by dry oxidation. Since a phenomenon occurs, an equivalent effect can be obtained by using the manufacturing method of the present invention.

The impurity concentration distribution after the thermal oxidation at the first processing temperature is the same as the impurity distribution shown in FIGS. This impurity concentration distribution is a distribution on the Y1-Y1 line.
Next, heat treatment is performed at a second treatment temperature higher than the first treatment temperature at which thermal oxidation is performed (FIG. 4). Here, the heat treatment at the second treatment temperature is 1000 ° C. or higher in an atmosphere (or in a vacuum) with a non-oxidizing gas such as nitrogen or argon in order to prevent further localization of the impurity concentration due to oxidation. Heat treatment is performed at a treatment temperature of 1150 ° C. or lower. If the second treatment temperature is less than 1000 ° C., it takes too much time to redistribute B (boron) and P (phosphorus). When the temperature exceeds 1150 ° C., the time required for redistribution can be shortened, but the silicon substrate (the surfaces of the n-type diffusion layer 9, the p-type diffusion layer 10, and the p-type semiconductor substrate 8 under the gate oxide film 11 can be reduced. It is desirable that the temperature be 1150 ° C. or lower because defects such as slip may be introduced into the layer) and the device characteristics may be deteriorated.

FIG. 9 is a diagram showing an impurity concentration distribution after heat treatment at the second treatment temperature. This impurity concentration distribution is a distribution on the Y2-Y2 line of FIG. Here, the dose amount of phosphorus is 2 × 10 ¹³ cm ⁻² , and the dose amount of boron is 5 × 10 ¹³ cm ⁻² .

  When the heat treatment is performed at the second treatment temperature, the n-type and p-type impurities localized near the surface layer of the p-type diffusion layer 10 are thermally diffused from the high concentration region to the low region. P (phosphorus), which is an n-type impurity locally distributed in the surface layer, is thermally diffused from the surface in the depth direction and is reduced in concentration on the surface of the p-type diffusion layer 10.

  On the other hand, B (boron), which is a p-type impurity whose concentration has been reduced in the vicinity of the surface of the p-type diffusion layer 10, undergoes thermal diffusion in the surface direction and the depth direction. The concentration increases.

  As a result of the redistribution of the impurity concentration in this way, the concentration distribution in the biased depth direction becomes uniform, the n-type conversion near the surface caused by the formation of the gate oxide film 11 is eliminated, and the MOSFET element is It will be able to operate normally.

  Therefore, by using such a method, it is not necessary to take a method such as increasing the concentration of p-type impurity introduced at an initial stage so that the vicinity of the surface does not become n-type, and a design satisfying predetermined element characteristics is possible. Therefore, the degree of freedom in design increases.

  Further, the heat treatment at the second treatment temperature may be performed by a processing apparatus different from the thermal oxidation performed at the first heat treatment temperature, but the same processing apparatus (for example, an apparatus for forming a gate oxide film). The same effect can be obtained even if the processing is continuously performed. In this case, the throughput can be shortened as compared with the case where individual processing is performed by separate processing apparatuses.

Next, in this state, for example, a polysilicon film 12 is grown by a low pressure CVD method to form a gate electrode film (FIG. 5).
Next, for example, a resist pattern 13 is formed using a normal photolithography technique, and a gate electrode 14 is formed using the resist pattern 13 as a mask (FIG. 6).

Next, the entire resist pattern 13 is removed, and, for example, arsenic (As), which is an n-type impurity, is implanted by ion implantation to form an n ⁺ source layer 15 and an n ⁺ drain layer 16 using the gate electrode 14 as a mask ( FIG. 7).

Next, although not shown, the surface is covered with an interlayer insulating film, a contact hole is opened in the interlayer insulating film, and the source electrode and drain connected to the n ⁺ source layer 15 and the n ⁺ drain layer 16 through the contact hole An electrode is formed to form a MOSFET element in which the gate electrode 14 has a self-aligned structure.

  Here, it can be inferred that the same effect can be obtained even when the second heat treatment is performed after forming the gate electrode or at the time of forming the source layer and the drain layer. However, first, when the second heat treatment is performed after the gate electrode is formed, impurities in the gate electrode are diffused into the gate oxide film or stress due to the gate electrode is applied. Reliability will be affected. Second, when the second heat treatment is performed at the time of forming the source layer and the drain layer, the source layer and the drain layer are deepened. It is not preferable because the results are in conflict.

  In the above embodiment, the case where the p-type diffusion layer 10 is formed on the surface layer of the n-type diffusion layer 9 has been described. However, the present invention also applies to the case where the n-type diffusion layer is formed on the surface layer of the p-type diffusion layer. The same effect can be obtained by applying. In this case, the MOSFET element is a p-channel type, and the effect of lowering the gate threshold can be expected by applying the present invention.

Also, as shown in FIG. 10, the n ⁺ drain layer 16 is formed on the surface layer of the n-type diffusion layer 9, and only the n ⁺ source layer 15 is formed on the p-type diffusion layer 10 to increase the MOSFET element. The same effect can be obtained by applying the present invention to the case of the withstand voltage element. In this case, the n ⁺ source layer is formed using the gate electrode 14 as a mask, while the n ⁺ drain layer 16 is formed using a resist as a mask.

  Further, when the p-type semiconductor substrate 8 is replaced with an n-type semiconductor substrate, for example, an n-type diffusion layer is formed on the surface layer of the SOI substrate, and a p-type diffusion layer is formed on the n-type diffusion layer. Even when an n-channel MOSFET element is formed in the layer, the present invention can be applied and the same effect can be obtained.

  In addition, in a MOS device such as an IGBT (insulated gate bipolar transistor), when the present invention is applied to the formation of an n drift layer, a p well layer, a gate oxide film, a gate electrode, and the like, the same effect as described above can be obtained. .

  In addition, B (boron) and P (phosphorus) have been described as impurities. However, as for other impurities, n-type impurities (such as As) cause a pile-up phenomenon, and p-type impurities (such as Al) cause a suction phenomenon. By applying the invention, the same effect can be obtained by redistributing impurities.

FIGS. 11 to 17 are cross-sectional views of the main part manufacturing process shown in the order of steps in the semiconductor device manufacturing method according to the second embodiment of the present invention. This figure shows a p-channel MOSFET device.
The difference from Example 1 is that the conductivity type is reversed. By thermally oxidizing at the first processing temperature, the surface concentration of the n-type diffusion layer that has risen excessively is heat-treated at the second processing temperature, so that the n-type impurities and the p-type impurities are redistributed, and the n-type impurities are redistributed. The surface concentration of the impurity is lowered to an appropriate level, and the gate threshold voltage is set to a desired value.

For the n-type semiconductor substrate 28 (n-type silicon substrate) containing n-type impurities, for example, ion implantation of B (boron), which is a p-type impurity, is performed at 2 × 10 ¹³ cm through a mask such as a resist. ^A deep p-type diffusion layer 29 is formed by performing thermal diffusion with an introduction amount of ^-2 (dose amount) (FIG. 11).

Next, ion implantation of P (phosphorus), which is an n-type impurity, is performed again through a mask such as a resist with an introduction amount (dose amount) of 5 × 10 ¹³ cm ⁻² and thermal diffusion is performed. Then, the n-type diffusion layer 30 having a shallower depth than the p-type diffusion layer 9 is formed (FIG. 12).

Next, thermal oxidation is performed at the first processing temperature to grow the gate oxide film 31 (FIG. 13).
Here, the first treatment temperature is preferably 900 ° C. to 1100 ° C., and the thickness of the gate oxide film 31 is preferably 50 nm to 600 nm. If the first processing temperature is less than 900 ° C., the growth rate of the oxide film is slow, and it takes much time to form the thickness of the gate oxide film 31 of the present invention, which is not practical. If the temperature exceeds 1100 ° C., the oxide film softens and fluidizes, which may induce interface states and defects in the gate oxide film. Therefore, the conditions for forming the gate oxide film 31 are not preferable. When the thickness of the gate oxide film 31 is as thin as less than 50 nm, the effect of using the present invention is reduced in addition to the low breakdown voltage of the gate oxide film 31 required for the circuit configuration. If it exceeds 600 nm, the influence of the thickness of the gate oxide film 31 on the threshold voltage at which the p-channel MOSFET element is turned on becomes dominant, so that the threshold voltage increases and becomes impractical for circuit operation.

  As for the thermal oxidation method, pyro-oxidation is preferable from the viewpoint of throughput and productivity, and the effect of using the production method of the present invention is great, but the same applies when thermal oxidation is performed by dry oxidation. Since a phenomenon occurs, an equivalent effect can be obtained by using the manufacturing method of the present invention.

  Next, heat treatment is performed at a second treatment temperature higher than the first treatment temperature at which thermal oxidation is performed (FIG. 14). Here, the heat treatment at the second treatment temperature is performed at a temperature of 1000 ° C. or higher and 1150 ° C. or lower in an atmosphere of a non-oxidizing gas such as nitrogen or argon in order to prevent further localization of the impurity concentration due to oxidation. By performing heat treatment at a temperature, the surface concentration of P (phosphorus) can be lowered until the gate threshold voltage becomes an appropriate value. If the second treatment temperature is less than 1000 ° C., it takes too much time to redistribute B (boron) and P (phosphorus). If the temperature exceeds 1150 ° C., the time required for redistribution can be shortened, but the silicon substrate (the surfaces of the p-type diffusion layer 29, the n-type diffusion layer 30 and the n-type semiconductor substrate 28 under the gate oxide film 11). It is desirable that the temperature be 1150 ° C. or lower because defects such as slip may be introduced into the layer) and the device characteristics may be deteriorated.

The dose amount of boron is 2 × 10 ¹³ cm ⁻² and the dose amount of phosphorus is 5 × 10 ¹³ cm ⁻² .
When the heat treatment is performed at the second treatment temperature, the p-type and n-type impurities localized near the surface layer of the n-type diffusion layer 30 are thermally diffused from the high concentration region to the low region. P (phosphorus), which is an n-type impurity locally distributed in the surface layer, is thermally diffused in the depth direction from the surface to be reduced in concentration.

  On the other hand, B (boron), which is a p-type impurity whose concentration has been reduced near the surface of the n-type diffusion layer 30, undergoes thermal diffusion in the surface direction and the depth direction. The concentration increases.

  As a result of the redistribution of the impurity concentration as described above, the concentration distribution in the biased depth direction becomes uniform, and the high concentration of P (phosphorus) in the vicinity of the surface caused by the formation of the gate oxide film 31 is eliminated. Thus, an appropriate threshold voltage is ensured and the p-channel MOSFET device can operate normally.

  The heat treatment at the second treatment temperature may be performed by a treatment apparatus different from the thermal oxidation performed at the first heat treatment temperature, but the same treatment apparatus (for example, an apparatus for forming the gate oxide film 31) The same effect can be obtained even if the processing is continuously performed in (). In this case, the throughput can be shortened as compared with the case where individual processing is performed by separate processing apparatuses.

Next, in this state, for example, a polysilicon film 32 is grown by a low pressure CVD method to form a gate electrode film (FIG. 15).
Next, for example, a resist pattern 33 is formed using a normal photolithography technique, and the gate electrode 34 is formed using the resist pattern 33 as a mask (FIG. 16).

Next, the resist pattern 33 is removed from the entire surface, and, for example, p-type impurities are implanted by ion implantation to form a p ⁺ source layer 35 and a p ⁺ drain layer 36 using the gate electrode 34 as a mask (FIG. 17).

Next, although not shown, the surface is covered with an interlayer insulating film, a contact hole is opened in the interlayer insulating film, and the source electrode and drain connected to the p ⁺ source layer 35 and the p ⁺ drain layer 36 through the contact hole An electrode is formed to form a p-channel MOSFET element having the gate electrode 34 having a self-aligned structure.

  As described above, by applying the present invention to a p-channel MOSFET element, it is possible to prevent the gate threshold voltage from becoming excessively high by reducing the surface concentration of the n-type diffusion layer serving as the channel layer.

8 p-type semiconductor substrate 9 n-type diffusion layer 10 p-type diffusion layer 11 gate oxide film 12 polysilicon film 13 resist pattern 14 gate electrode 15 n ⁺ source layer 16 n ⁺ drain layer 28 n-type semiconductor substrate 29 p-type diffusion layer 30 n-type diffusion layer 31 gate oxide film 32 polysilicon film 33 resist pattern 34 gate electrode 35 p ⁺ source layer 36 p ⁺ drain layer

Claims (6)

In a method of manufacturing a semiconductor device having a MOS gate structure, a step of forming a second conductivity type second diffusion layer on a surface layer of the first conductivity type first diffusion layer, and a gate oxide film on the second diffusion layer Forming at a first processing temperature, a step of heat-treating at a second processing temperature higher than the first processing temperature, and a step of forming a gate electrode on the gate oxide film after the heat-treating step. And a method of manufacturing a semiconductor device, wherein an introduction amount of the second conductivity type impurity in the second diffusion layer is higher than an introduction amount of the first conductivity type impurity in the first diffusion layer. In a method of manufacturing a semiconductor device having a MOS gate structure, a step of forming a p-type diffusion layer on a surface layer of an n-type diffusion layer, and a step of forming a gate oxide film on the p-type diffusion layer at a first processing temperature And a step of heat-treating at a second treatment temperature higher than the first treatment temperature, and a step of forming a gate electrode on the gate oxide film after the heat treatment step, wherein the first treatment temperature is T A method of manufacturing a semiconductor device, wherein the value of K is 1 <K ≦ −0.075T + 92.5 when the temperature is set to ° C. and the amount of introduced p-type impurity is K times the amount of introduced n-type impurity. 3. The semiconductor device according to claim 1, wherein the first processing temperature is 900 ° C. or higher and 1100 ° C. or lower, and the second processing temperature is 1000 ° C. or higher and 1150 ° C. or lower. Method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a thickness of the gate oxide film is not less than 50 nm and not more than 600 nm. 3. The semiconductor device according to claim 1, wherein the thermal oxidation is dry oxidation performed by introducing oxygen gas, pyrooxidation performed by burning oxygen gas and hydrogen gas, or steam oxidation. Manufacturing method. The method for manufacturing a semiconductor device according to claim 1, wherein the thermal oxidation step and the heat treatment step are continuously performed in the same apparatus.

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