JPH11284172A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and method for manufacturing it wherein inverse short channel effect of a minute n-type MOSFET is suppressed with no degraded reliability of a gate oxide film. SOLUTION: A source/drain region 120 comprising a second conductivity diffusion layer is formed in a well region 102 of first conductivity which is formed on a substrate 101, and a gate electrode part 104 is formed, with a gate oxide film 103 in between, on the surface of substrate 101 sandwiching the source/drain region 120, in an MOSFET. Here, the source region and the drain region (120) formed, with a channel region formed below the gate electrode part 104 as a center, on its both sides comprise diffusion regions 122, 123, and 124 each of which comprises at least 3-stage of second conductivity impurity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly, to a method for effectively preventing a reverse short channel effect in a miniaturized MOSFET, and particularly for a logic circuit system. The present invention relates to a semiconductor device capable of operating accurately and stably when used.

[0002]

2. Description of the Related Art Conventionally, generally, miniaturized N-MOS
In the case of an N-MOS type transistor which targets a transistor having a gate length of 0.2 μm or less, the threshold voltage is reduced before the threshold voltage decreases due to the short channel effect as the gate length decreases. Is once increased, an inverse short channel effect is observed.

That is, in a conventional MOSFET described later, as shown in FIG. 4, the gate length L (μm) is gradually reduced, and as the gate length approaches 0.25 μm, the threshold voltage of the MOSFET is reduced. When the voltage Vth becomes higher than a predetermined threshold voltage, for example, 0.5 V, a so-called reverse short channel effect phenomenon occurs, and when the gate length becomes smaller than 0.20 μm, the threshold voltage V becomes lower.
It has been confirmed that th decreases rapidly.

[0004] The occurrence of the inverse short channel effect is caused by a malfunction of logic processing due to a change in threshold value, particularly when the miniaturized N-MOS transistor is used in a logic circuit system. It may cause a decrease in performance. First, the cause of the above-described problem in a miniaturized MOS transistor will be described below.

[0005] That is, a conventional example of a method for manufacturing an N-type MOSFET will be described with reference to FIGS. 2A and 2B.
The reason why the reverse short channel effect phenomenon occurs will be described. First, as shown in FIG. 2A, B ⁺ ions are implanted into a P-type semiconductor substrate 1 for threshold voltage adjustment to form a P-type well region 2, and then a gate oxide film 3 and a gate electrode 4 are formed. Form.

Further, an N-type impurity 5 is ion-implanted to form an N-type LDD region 6. After that, as shown in FIG. 2B, a sidewall 7 is formed, an N-type impurity 8 is ion-implanted, activation heat treatment is performed, and an N-type source / drain region 9 is formed. However, in the conventional example shown in FIG. 2, when the sidewall 7 is formed, silicon ions generated by point defects generated in the LDD region during ion implantation of the N-type impurity 5 cause boron atoms to form a well channel. Form a pair with
As shown in FIG. 2B, a pile-up region 10 of boron is formed near the gate end.

That is, when a silicon atom which is detached from the silicon lattice due to the above point defect encounters a high temperature of, for example, 700 to 800 ° C. at the time of forming the sidewall portion, the silicon atom is bonded to the boron to form a pair. As a result, the LDD region 6 is formed below the gate oxide film as a result of the enhanced diffusion and the attraction toward the gate oxide film.
, The boron is concentrated, and the concentration of the boron is
A portion 10 which is relatively higher than the boron concentration in other well regions is formed.

[0008] Such an area is called a pile-up area. As an example, if the concentration of boron in the P-type well region is 4 × 10
Even in the case of about ¹⁷ cm ^-3, the density of the pile-up area is 1.
It may be about 3 × 10 ¹⁸ cm ^-3 . As the gate length L decreases, the ratio of the pile-up region 10 to the entire channel increases, so that the threshold voltage increases.

The inverse short channel effect is caused by the gate length L
Has become remarkable in micro devices targeted at 0.2 μm or less. In other words, an N-MOS with a target gate length L of 0.3 μm or more
In the manufacture of FETs, heat treatment is generally performed at, for example, about 900 ° C. for about 1 hour at the time of source-drain activation heat treatment. Because of the distribution, the reverse short channel effect does not appear.

On the other hand, in an N-MOSFET having a gate length L of 0.2 μm or less as a target, in order to suppress the spread of impurities, a high-speed heat treatment (for example, at 1000 ° C. for about 10 seconds) is performed at the time of the source-drain activation heat treatment. RT
A) is used, and boron in the piled-up channel region does not redistribute and stays in the well region below the channel region as shown in the figure, so that an inverse short channel effect appears. .

On the other hand, a method of manufacturing a fine N-type MOSFET in which the above-mentioned inverse short channel effect is suppressed is described in, for example, K. Takeuchi et al., High performance sub
-tenth micron CMOS using advanced boron dopi
ng and WSi ₂ dual gateprocess, Symp.on VLSI
Tech., P. 9, 1995 ”and the like, the outline of which is described in detail with reference to FIGS. 3 (A) to 3 (C).

First, as shown in FIG. 3A, a gate oxide film 22 and a gate electrode 23 are formed on a P-type semiconductor substrate 20. After that, the N-type impurity 24 is ion-implanted,
An N-type LDD region 25 is formed. After that, as shown in FIG. 3B, after forming a sidewall 26, ions of an N-type impurity 27 are implanted and activation heat treatment is performed to form an N-type source-drain region 28.

[0013] Thereafter, as shown in FIG. 3 (C), B ⁺ 2
9 is ion-implanted over the entire surface of the substrate to form a P-type well region 21. According to the conventional example shown in FIG.
After ion implantation of 4 and 27, activation heat treatment is performed to eliminate point defects generated at the time of ion implantation, and then B ⁺ 29 forming a channel is ion-implanted.

Therefore, the pile of boron is increased by the enhanced diffusion.
Up area is not formed, and therefore
The tunnel effect can be suppressed. However, FIG.
In the conventional example shown in FIGS.
After forming the film 22, through this gate oxide film 22,
B for threshold voltage adjustment ⁺Do 29 ion implantations
As a result, the quality of the gate oxide film 22 is deteriorated,
Is reduced.

Further, Japanese Patent Application Laid-Open No. 8-78682 discloses that
In order to prevent the pile-up of boron and the like, after forming a diffusion region in the MOSFET, an impurity such as boron is ion-implanted in advance under the gate electrode to prevent redistribution of the impurity. Therefore, there is a problem that the number of lithographic steps increases.
Also, in Japanese Patent Application Laid-Open No. 8-18047,
In order to prevent the point defect generated at the time of drain implantation from being caused by enhanced heat treatment in a later step, a method for channel ion implantation after performing ion implantation and activation of source-drain impurities is disclosed. However, such a method has a problem that the number of lithographic steps increases.

[0016]

SUMMARY OF THE INVENTION Accordingly, a main object of the present invention is to reduce the reliability of a gate oxide film without deteriorating its reliability.
It is an object of the present invention to provide a semiconductor device that suppresses the inverse short channel effect of a miniaturized n-type MOSFET and a method of manufacturing the same.

[0017]

The present invention basically employs the following technical configuration in order to achieve the above object. That is, according to a first aspect of the present invention, a source and drain region including a diffusion layer having a second conductivity is formed in a well region having a first conductivity formed in a substrate, and A MOSFET in which a gate electrode portion is formed on the surface of the substrate sandwiching the source and drain regions, the source region being formed on both sides of a channel region formed below the gate electrode portion; The drain region is a semiconductor device including a diffusion region containing at least three levels of second conductive impurities. In a second embodiment, a second conductive region is formed in a well region having first conductivity.
Source and drain regions having conductivity of
A MOS in which a gate electrode portion is formed via a channel region provided between the source and drain regions
In the FET, the threshold voltage adjustment region is projected into the well region from an end of the LDD region including the source and drain regions facing the channel toward the channel. This is a method for manufacturing a semiconductor device to be formed.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device and the method of manufacturing the semiconductor device according to the present invention employ the above-described technical configuration. Therefore, in a miniaturized N-MOS, Vth increases as the gate length becomes shorter. A once rising inverse short channel effect occurs. This is because boron forming the channel is redistributed when the sidewall is formed, a high boron concentration region is formed near the gate end, and the proportion of this region increases as the gate length becomes shorter.

According to the present invention, an N-type impurity is implanted at a lower dose and obliquely than in an N-type LDD diffusion layer, and an N ⁻ region is formed in advance near the gate end at a position shallower than the LDD diffusion layer. The reverse short channel effect is suppressed by canceling the high boron concentration region near the gate end due to boron redistribution.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a semiconductor device according to the present invention. That is, FIG. 1C is a cross-sectional view showing the outline of the configuration of one specific example of the semiconductor device 30 according to the present invention. In the drawing, a first conductive well region 102 formed on a substrate 101 is shown. Then, source and drain regions 120 made of a diffusion layer having second conductivity are formed, and a gate electrode portion 104 is formed on the surface of the substrate 101 sandwiching the source and drain regions 120 with a gate oxide film 103 interposed therebetween. And the source region and the drain region 120 formed on both sides of a channel region 121 formed below the gate electrode portion 104, each of which has at least three stages of a second stage.
The semiconductor device 30 including the diffusion regions 122, 123, and 124 containing conductive impurities is shown.

In the semiconductor device 30 according to the present invention, each of the diffusion regions 122, 1
23 and 124 are configured to have second conductive impurity concentrations different from each other. Preferably, the diffusion region 122 in a portion in contact with the channel region 121 is a first diffusion region. The diffusion region 123 in contact with the first diffusion region is a second diffusion region, and the diffusion region 124 in contact with the second diffusion region is a third diffusion region.
Of the diffusion regions 122, 123, and 12 in the direction away from the channel region 121.
It is preferable that the second conductive impurities included in each of the diffusion regions 4 are sequentially increased in concentration.

That is, the concentration of the second conductive impurity in the first diffusion region 122 is the lowest, and the concentration of the second conductive impurity in the third diffusion region 124 is the highest. It is desirable to configure it. As is apparent from the above description, the third diffusion region 124 is
The second diffusion region 123 corresponds to a source-drain diffusion region generally used in an SFET, and the second diffusion region 123 corresponds to a conventional LLD diffusion region.

Further, in the semiconductor device 30 according to the present invention, each of the diffusion regions 122 and 1 including the three-stage second conductive impurities constituting the source and drain regions is provided.
It is desirable that the diffusion regions 23 and 124 be configured such that the thickness of each diffusion region increases from the center of the channel region toward the direction away from the channel region.

In the semiconductor device 30 according to the present invention, at least a part of the first diffusion region 122 includes a first conductive impurity, for example, boron contained in the well region 102, and It is necessary to be configured so as to overlap with a region portion relatively concentrated as compared with the other portion, that is, at least a part of the pile-up region 112 described above.

Further, in the present invention, the concentration of the second conductive impurity, for example, arsenic As contained in the first diffusion region 122 in the semiconductor device 30 is determined in the well region 102. The first conductive impurity is concentrated in the pile-up region portion 112 and the first conductive impurity
It is desirable that the concentration be set to a value that can offset at least a part of the concentration of the conductive impurity.

That is, in the present invention, the first diffusion region 122 closest to the center of the channel region 121 in the semiconductor device 30 is the MOSFE.
It has a threshold voltage adjusting function of T and forms a threshold voltage adjusting region 122. More specifically, in the threshold voltage adjustment region 122 corresponding to the first diffusion region 122, it is desirable that the impurity concentration of the second conductive impurity be approximately 8 × 10 ¹⁷ cm ⁻³ .

As a specific example of the semiconductor device 30 according to the present invention, the first conductive impurity is boron (B), and the second conductive impurity is arsenic (As). If a more specific example of the configuration of the semiconductor device 30 according to the present invention is shown, a first conductive well region 102 formed on a substrate 101 is formed of a diffusion layer having a second conductivity. Source and drain regions 120 are formed,
A MOSFE in which a gate electrode portion 104 is formed on the surface of the substrate sandwiching the source and drain regions 120
T, the source region and the drain region are formed on the channel region 121 side of the source region and the drain region 120 formed on both sides of the channel region 121 formed below the gate electrode portion 104. A second conductive LDD diffusion region 123 containing a second conductive impurity at a concentration lower than the concentration of the second conductive impurity contained in region 124 is formed, and extends from LDD diffusion region 123 to further form. This is a semiconductor device in which a diffusion region 122 extending toward the channel region 121 and including a second conductive impurity having a concentration lower than the concentration of the second conductive impurity included in the LDD diffusion region 123 is formed.

Further, when the semiconductor device 30 according to the present invention is grasped from another viewpoint, the semiconductor device 30 has the following configuration. That is, in the MOSFET, the second conductive well region 102 provided on the substrate 101 is
Is formed, and the gate electrode portion 10 is formed via a channel region 121 provided between the source and drain regions 120.
4, a gate electrode portion 104, a sidewall portion 109 is formed, a part of the source and drain region 124 is included, and a diffusion layer of the source and drain region 124 is formed. An LDD region portion 123 having a thickness smaller than that of the LDD region portion 123 and having the same conductivity as that of the source and drain regions and formed so as to protrude in the channel direction;
A threshold voltage adjustment projecting from the end of the D region 123 facing the channel toward the channel side into the well region 121 and having the same conductivity as the source and drain regions. A region including a region 122 and at least a part of the threshold voltage adjustment region 122 and a common region, and a region in which impurities contained in the well region 102 are relatively concentrated in the well region 102 112 shows a semiconductor device composed of the first and second semiconductor devices.

The gate length L in the semiconductor device 30 according to the present invention targets a length of 0.2 μm or more, and therefore, in the semiconductor device 30 according to the present invention. , The gate length L is 0.2 μm
In the following, the short channel effect occurs, but when the gate length is 0.2 μm or more, the threshold voltage Vth of the MOSFET is maintained almost constant, and the reverse short channel effect hardly occurs. It is a characteristic.

Hereinafter, the semiconductor device 30 according to the present invention will be described.
A specific example of the manufacturing method will be described with reference to FIGS.
This will be described in detail. As shown in FIG.
A P-type well region 102 is formed on a substrate 101. First guide
The P-type well region 102 which is an electric type is, for example, a first conductive type.
B which is an impurity ⁺Energy of ion implantation 300 ke
V, dose amount 2 × 10¹³cm^-2After injection under the conditions of⁺
With an ion implantation energy of 30 keV and a dose of 8 × 1
0¹²cm^-2And formed by injection.

A typical concentration near the surface of the P-type well region 102 is about 5 × 10 ¹⁷ cm ⁻³ . Thereafter, a gate oxide film 103 having a thickness of, for example, about 5 nm is formed by a thermal oxidation method, and then a polycrystalline silicon film having a thickness of about 200 nm is deposited. After that, the gate electrode 104 is formed by a photolithography step and a dry etching step.

Thereafter, for example, As 105 is ion-implanted with an ion implantation energy amount of 15 keV and a dose amount of 2 × 10 ¹⁴ cm ⁻² to form an N-type LDD region 106. Note that a typical N-type LDD region 106 has an impurity concentration of 1 × 10 ¹⁹ cm.
It is about ^-3 . Then, as shown in FIG.
⁺ 107 is, for example, 50 ke
V, a dose amount of 3.2 × 10 ¹³ cm ⁻² and an ion implantation angle of 60 ° are obliquely implanted.

Thus, N-type impurity region 108 is formed at a position closer to the channel than N-type LDD region 106. A part of the N-type impurity region 108 constitutes the first diffusion region 122 which is the above-described threshold voltage adjustment region, and the typical impurity concentration of the N-type impurity region 108 is 8 It is about × 10 ¹⁷ cm ⁻³ . Thereafter, as shown in FIG. 1C, a sidewall 109 made of an oxide film is formed. The side wall 109 is formed by depositing an oxide film having a thickness of about 120 nm by a CVD method at a growth temperature of about 700 ° C. to about 800 ° C. and then performing an etch back by an RIE method.

After that, As ⁺ 110 is ion-implanted with an ion implantation energy amount of 50 keV and a dose amount of about 3 × 10 ¹⁵ cm ⁻² , and then an activation heat treatment (RTA) is performed in a nitrogen atmosphere at 1000 ° C. for about 10 seconds. As a result, an N-type source / drain region 120 (124) is formed. During the formation of the sidewalls 109, boron in the P-type well region 102 undergoes accelerated diffusion to form a pile-up region 112 of boron near the gate end.

The typical concentration of the boron pile-up region 112 is about 8 × 10 ¹⁷ cm ⁻² higher than the surrounding area, and is about 1.3 × 10 ¹⁸ cm ⁻³ . However, the threshold voltage adjustment region 1 of the pile-up region 112
In No. 22, the N-type impurity region of about 8 × 10 ¹⁷ cm ⁻³ was formed in advance, and the boron was piled up by the enhanced diffusion, which was canceled out, and the uniform P-type area of about 5 × 10 ¹⁷ cm ^−3. It becomes a type impurity region.

That is, in the present invention, in the channel region 121 in the well region 102, the pile-up amount of the first conductive impurity gathered from the other well region 102 is substantially equal. Amount of the second conductive impurity is mixed into the channel region 121 in advance,
By canceling out and neutralizing the electrical characteristics caused by the extra conductive first conductive impurity, the channel region 121 has the initially designed amount of the first conductive impurity in the channel region 121. It is configured to be revealed.

The constituent materials and various numerical values in the above specific examples of the present embodiment are merely examples of the semiconductor device according to the present invention, and the present invention is not limited to the various numerical values described above. . Here, a comparison result regarding the dependency of the threshold voltage on the gate length L in the semiconductor device 30 according to the present invention and the conventional semiconductor device will be described below with reference to FIG.

In FIG. 4, ● indicates an example of a conventional semiconductor device, and white circles indicate a semiconductor device according to the present invention. now,
In the vicinity of a target gate length L (0.2 μm), in order to match the threshold values Vth of both, in a conventional semiconductor device, boron B ⁺ which is a first conductive impurity for forming the channel is used. Was set to 6.5 × 10 ¹² cm ^−2, and the dose according to the present invention was set to 8 × 10 ¹² cm ⁻² .

Therefore, in a region where the gate length L is long, for example, when the gate length L is 0.7 μm or more, the threshold voltage Vth of the semiconductor device 30 according to the present invention becomes lower than that of the conventional semiconductor device. It has been found that the threshold voltage Vth of the conventional semiconductor device is higher as the gate voltage L becomes higher than the threshold voltage Vth and the gate length L becomes shorter.

That is, in the conventional semiconductor device, as the gate length L becomes shorter, the threshold voltage Vth
, The threshold voltage Vth increases up to the gate length L of 0.25 μm. Further, when the gate length L is further shortened, a so-called short channel effect becomes dominant, and a phenomenon is seen in which the threshold voltage Vth drops sharply.

Referring to the case where the target gate length L in the semiconductor device 30 is set to around 0.20 μm, as shown in FIG. 4, the present invention is more suitable for the gate having the threshold voltage Vth. It can be seen that the long L dependency can be reduced. This is because when the threshold voltage Vth near the gate length L (L = 0.20 μm) is adjusted to a desired value, the conventional semiconductor device takes the channel into consideration in consideration of the increase in Vth due to the inverse short channel effect. The dose amount of, for example, boron B ⁺ , which is the first conductive impurity for formation, is 6.5 × 1
0 ¹² cm it was necessary to keep the order of ^-2, in the present invention, since it inhibited the reverse short channel effect, increasing the dose of boron B ⁺ for forming a channel to the 8 × 10 ¹² cm ^-2 I can do things.

Therefore, the boron concentration near the center of the channel can be increased, so that the gate length L is 0.2 μm.
Short channel effects occurring in the following regions can be reduced. As described above, by using the present invention to suppress the reverse short channel effect in the semiconductor device,
Threshold voltage Vth in the region where short channel effect occurs
It has been found that it is possible to reduce the dependence on the gate length L.

The first diffusion region 1 according to the present invention
22, that is, the ion implantation angle when obliquely implanting the second conductive impurity into the surface of the substrate 101 when forming the threshold voltage adjustment region 122 is:
Although not particularly limited, it is preferable that the processing is performed in a range of 45 degrees to 60 degrees. In the method of manufacturing the semiconductor device 30 according to the present invention, the device used is:
There is no particular limitation, and it is possible to use a well-known device conventionally used in manufacturing a MOSFET. However, the first diffusion region 122, that is, the threshold voltage adjustment region 122 is used. It is desirable that the ion implantation angle of the ion implantation apparatus at the time of forming is set so that it can be set to an arbitrary angle.

In the method of manufacturing a semiconductor device according to the present invention, basically, a first conductive well region is formed in a well region.
A source and drain region having second conductivity is formed, and a gate electrode portion is formed via a channel region provided between the source and drain regions.
In the OSFET, the threshold voltage adjustment region is projected into the well region from an end of the LDD region including the source and drain regions facing the channel toward the channel. This is a method for manufacturing a semiconductor device to be formed. Specifically, after forming the gate electrode, an LDD region is formed, and then, a predetermined impurity is ion-implanted at an oblique angle with respect to the surface of the semiconductor device. This is a method for manufacturing a semiconductor device in which the threshold voltage adjustment region 122 is formed from the end of the LDD region 123 facing the channel toward the channel region 121.

In the present invention, it is desirable that the threshold voltage adjusting region 122 is formed so as to have the same conductivity as the LDD region 123. It is desirable that the depth of the adjustment region 122 be formed to be smaller than the depth of the LDD region 123. In addition, the threshold voltage adjustment region 12 according to the present invention.
At the same time, a predetermined impurity is ion-implanted so that the impurity concentration of No. 2 becomes approximately 8 × 10 ¹⁷ cm ^−3, and at least a part of the threshold voltage adjustment region 122 is in the semiconductor device 30. A position formed at a portion of the well region portion 102 adjacent to the channel region 121 and overlapping with at least a part of the pile-up region 112 formed by relatively concentrating impurities contained in the channel region. It needs to be formed.

Although the degree of overlap between the two regions in the present invention is not particularly limited, as described above, the first conductive impurity concentration in the pile-up region 112 is set in advance in the well region 102. The condition for adjusting the concentration of the first conductive impurity included is selected. Furthermore, to explain a more specific method of manufacturing the semiconductor device 30 according to the present invention, a first step of forming a well region having one conductivity on a predetermined substrate, the surface of the well region A second step of forming a gate electrode on the gate oxide film, a third step of forming a predetermined electrode portion using a conductive film on the gate oxide film, and using the electrode portion as a mask to form a predetermined impurity on the gate. A fourth step of implanting ions from above the oxide film to form an LDD region having a conductivity different from the conductivity of the well region, and using the electrode portion as a mask, diagonally implanting a predetermined impurity from above the gate oxide film; To the semiconductor device from the direction of
Forming a threshold voltage adjusting region having the same conductivity as that of the LDD region and projecting into the well region from an end of the D region facing the channel toward the channel side; A step of forming a sidewall using the predetermined oxide film on the electrode portion, and ion-implanting a predetermined impurity using the side wall as a mask to have the same conductivity as that of the LDD region. A seventh step of forming source and drain regions having conductivity and a thickness greater than the thickness of the LDD region.

In the step of ion-implanting a predetermined impurity into the semiconductor device from the gate oxide film in an oblique direction from the gate oxide film according to the present invention, for example, a semiconductor device manufacturing apparatus including a conventionally well-known sputtering device is used. However, the present invention can be easily implemented by using a device configured so that the plane of the mounting table of the semiconductor device in the semiconductor device manufacturing equipment can be changed and adjusted in an arbitrary direction and at an arbitrary angle. .

[0048]

The semiconductor device and the method for manufacturing the semiconductor device according to the present invention have the above-described structure, and therefore, before the pile-up region of boron is formed near the gate end, the pile-up region is formed. By inverting the portion to be N-type, an increase in channel concentration due to boron pile-up can be offset.

By forming the N-type impurity region 109 formed beforehand shallower than the N-type LDD region 107, the short channel effect is not increased.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views illustrating steps of a specific example of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating steps of a specific example related to a conventional method of manufacturing a semiconductor device.

FIGS. 3A to 3C are cross-sectional views illustrating steps of another specific example related to a conventional method for manufacturing a semiconductor device.

FIG. 4 is a graph illustrating an effect difference between the semiconductor device according to the present invention and a conventional semiconductor device.

[Explanation of symbols]

1, 20, 101: substrate 2, 21, 102: first conductivity type well region 3, 22, 103: gate oxide film 4, 23, 104: gate electrode portion 5, 24, 105, 107: second conductivity type Impurities 6, 25, 106, 123 ... N-type LLD regions 7, 26, 109 ... Side walls 8, 27 ... Second conductivity type impurities 9, 28, 120, 111 ... Source-drain regions 10, 112 ... Pile-up region 29 ... First conductive impurities 30 ... Semiconductor devices 108, 122 ... Second conductive impurity regions, threshold voltage adjustment regions

Claims (22)

[Claims] 1. A source and drain region comprising a second conductive diffusion layer formed in a first conductive well region formed on a substrate, and the substrate sandwiching the source and drain region. In a MOSFET having a gate electrode portion formed on the surface, the source region and the drain region formed on both sides of a channel region formed below the gate electrode portion each have at least 3 A semiconductor device comprising: a diffusion region containing a second conductive impurity in a step. 2. The three-stage diffusion region including the second conductive impurity constituting the source region and the drain region, wherein each diffusion region extends from a portion in contact with the channel region in a direction away from the channel region. 2. The semiconductor device according to claim 1, wherein the concentration of the second conductive impurity contained in the semiconductor device is increased. 3. The three-stage diffusion region including the second conductive impurity constituting the source region and the drain region, the diffusion region extending from the center of the channel region in a direction away from the channel region. 3. The semiconductor device according to claim 1, wherein the semiconductor device is configured to have a large thickness. 4. The first diffusion region closest to the center of the channel region forms a threshold voltage adjustment region having a threshold voltage adjustment function of the MOSFET. The second connected to the value voltage adjustment area
4. The diffusion region according to claim 1, wherein the third diffusion region connected to the LDD diffusion region constitutes a normal diffusion region. Semiconductor device. 5. The first diffusion region, wherein at least one of the region portions where the first conductive impurity contained in the well region is relatively concentrated compared to other portions of the well region. The semiconductor device according to claim 1, wherein the semiconductor device is configured to overlap a part. 6. The concentration of the second conductive impurity contained in the threshold voltage adjusting region that is the first diffusion region is such that the concentration of the first conductive impurity is concentrated in the well region. 6. The semiconductor device according to claim 5, wherein a concentration is set such that at least a part of the concentration of the first conductive impurity in the region where the first conductive impurity is set can be offset. 7. The semiconductor device according to claim 1, wherein said threshold voltage adjustment region contains an impurity having an impurity concentration of approximately 8 × 10 ¹⁷ cm ^−3. . 8. The semiconductor according to claim 1, wherein said first conductive impurity is boron (B), and said second conductive impurity is arsenic (As). apparatus. 9. A source and drain region comprising a diffusion layer having a second conductivity formed in a well region having a first conductivity formed in a substrate, and the substrate sandwiching the source and the drain region. A MOSFET in which a gate electrode portion is formed on the surface, and a source region and a drain region formed on both sides of a channel region formed below the gate electrode portion on the side of the channel region. Forming a second conductive LDD diffusion region containing a second conductive impurity at a concentration lower than the concentration of the second conductive impurity contained in the source region and the drain region, and extending from the LDD diffusion region. And a second conductive impurity having a concentration lower than that of the second conductive impurity contained in the LDD diffusion region and extending toward the channel region. A semiconductor device, wherein a diffusion region is formed. 10. The diffusion region extended to the channel region side from the LDD diffusion region is the MOSFE.
10. The semiconductor device according to claim 9, wherein a threshold voltage adjusting region having a threshold voltage adjusting function of T is formed. 11. In a MOSFET, a source and a drain region having a second conductivity are formed in a well region having a first conductivity, and a channel region provided between the source and the drain region. A MOSFET having a gate electrode portion formed therebetween, and a sidewall portion is formed on the gate electrode portion,
Includes a part of the source and drain regions, is thinner than the diffusion layers of the source and drain regions, and has the same conductivity as the source and drain regions, and protrudes in the channel direction. L formed on
A threshold that is projected into the well region from the end of the DD region portion facing the channel of the LDD region toward the channel side and has the same conductivity as that of the source and drain regions; A value voltage adjustment region, and a region having at least a part of the threshold voltage adjustment region and a common region portion, and a region where impurities contained in the well region portion are relatively concentrated. Characteristic semiconductor device. 12. A short channel effect occurs when the gate length of the MOSFET is 0.2 μm or less, but when the gate length is 0.2 μm or more, the short channel effect occurs.
12. The semiconductor device according to claim 1, wherein the threshold voltage Vth of the FET is maintained substantially constant. 13. A well region having a first conductivity,
A source and drain region having second conductivity is formed, and a gate electrode portion is formed via a channel region provided between the source and drain regions.
In the OSFET, the threshold voltage adjustment region is projected into the well region from an end of the LDD region including the source and drain regions facing the channel toward the channel. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device; 14. An LDD region is formed after a gate electrode is formed, and thereafter, a predetermined impurity is ion-implanted at an oblique angle with respect to the surface of the semiconductor device to thereby form an end opposite to the channel of the LDD region. 14. The method according to claim 13, wherein the threshold voltage adjustment region is formed from the portion toward the channel region. 15. The threshold voltage adjustment region includes:
The method according to claim 13, wherein the semiconductor device is formed so as to have the same conductivity as the DD region. 16. The depth of the threshold voltage adjustment region is
16. The method of manufacturing a semiconductor device according to claim 13, wherein the LDD region is formed to be shallower than the depth of the LDD region. 17. The semiconductor device according to claim 13, wherein a predetermined impurity is ion-implanted so that an impurity concentration of the threshold voltage adjusting region is approximately 8 × 10 ¹⁷ cm ^−3. 13. A method for manufacturing a semiconductor device according to 18. An impurity contained in the channel region, which is formed in a portion of the well region in the semiconductor device close to the channel region, is relatively concentrated in the threshold voltage adjustment region. 18. The method of manufacturing a semiconductor device according to claim 13, wherein the semiconductor device is formed at a position overlapping with a pile-up region formed by the method. 19. The method according to claim 18, wherein the impurity contained in the threshold voltage adjustment region is As, and the impurity contained in the pile-up region is B. 20. A first step of forming a well region having one conductivity type on a predetermined substrate, a second step of forming a gate oxide film on the surface of the well region, and a conductive step on the gate oxide film. A third step of forming a predetermined electrode portion using a conductive film, using the electrode portion as a mask, ion-implanting a predetermined impurity from above the gate oxide film, and forming a conductive material having a conductivity different from that of the well region. A fourth step of forming an LDD region having a property, using the electrode portion as a mask, ion-implanting predetermined impurities into the semiconductor device from above the gate oxide film in an oblique direction, and opposing a channel of the LDD region; Projecting from the end portion toward the channel side into the well region, having the same conductivity as that of the LDD region,
A fifth step of forming a threshold voltage adjustment region, a sixth step of forming a sidewall of the electrode portion using a predetermined oxide film, and ion implantation of a predetermined impurity using the sidewall as a mask. A seventh step of forming source and drain regions having the same conductivity as that of the LDD region and having a thickness larger than the thickness of the LDD region. Manufacturing method of a semiconductor device. 21. In the threshold voltage adjustment region, impurities contained in the channel region formed in a portion of the well region portion close to the channel region in the semiconductor device are relatively concentrated. 21. The method of manufacturing a semiconductor device according to claim 20, wherein the semiconductor device is formed at a position overlapping with a pile-up region formed by the method. 22. The concentration of the second conductive impurity contained in the threshold voltage adjusting region is determined by adjusting the concentration of the first conductive impurity in the pile-up region in the well region. 21. The method of manufacturing a semiconductor device according to claim 20, wherein the concentration is set to be able to offset at least a part of the concentration of the first conductive impurity.