JP2011146733A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent insulation breakdown of a gate electrode caused by needle-like projections occurring inside an element isolation trench during the formation of the gate electrode. <P>SOLUTION: After a silicon oxide film 4 is formed on a silicon nitride film 3 which is to serve as an etching mask for forming the element isolation trench, prior to a step of patterning the silicon nitride film 3, with a photoresist film 6 provided with an antireflection film 5 in a lower layer as a mask, the surface of a substrate 1 is cleaned with a hydrofluoric acid-based etchant, to thereby remove (lift off) a foreign matter 7 attached to the surface of the silicon oxide film 4. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a process of manufacturing an element isolation trench (Shallow Trench Isolation; STI) in a semiconductor substrate.

  A general method for forming an element isolation trench in a semiconductor substrate is as follows. First, a single crystal silicon substrate is thermally oxidized to form a thin silicon oxide film on its surface, and a silicon nitride film is deposited thereon by a CVD (Chemical Vapor Deposition) method, followed by dry etching using a photoresist film as a mask. The silicon nitride film and the silicon oxide film in the element isolation region are removed by etching. Next, after removing the photoresist film and forming a groove in the substrate by dry etching using the silicon nitride film as a mask, the substrate is thermally oxidized to form a thin silicon oxide film on the inner wall of the groove. This silicon oxide film is formed for the purpose of removing etching damage generated on the inner wall of the groove and relieving the stress of the silicon oxide film embedded in the groove in a later step.

  Next, after a thick silicon oxide film is deposited on the substrate including the inside of the groove by a CVD method, the substrate is heat-treated, and the silicon oxide film embedded in the inside of the groove is densely baked (densified). Subsequently, the silicon oxide film on the upper part of the silicon nitride film is removed by a chemical mechanical polishing (CMP) method to leave the silicon oxide film only in the groove, and then the silicon nitride film that is no longer needed is removed. Remove by etching.

  The element isolation groove formed by the above method has a step between the surface of the silicon substrate when the silicon nitride film is removed and the surface of the silicon oxide film in the element isolation groove. In the cleaning process, a phenomenon occurs in which the silicon oxide film at the end of the element isolation groove is recessed (recessed) downward.

  Therefore, the gate oxide film formed on the substrate surface of the active region is locally thinned at the end (shoulder) of the active region, and the electric field of the gate voltage is concentrated on the shoulder, so that the drain current can be generated even at a low gate voltage. It is known that a phenomenon of flowing (called kink characteristics) occurs, and as a countermeasure for solving this phenomenon, a technique of rounding the shoulder of the active region has been proposed.

  For example, Japanese Patent Laid-Open No. 63-2371 (see Patent Document 1) describes a threshold when a fine MISFET having a channel width of 1 μm or less is formed in an active region of a substrate surrounded by the element isolation trench as described above. It points out the problem that the so-called narrow channel effect, in which the value voltage (Vth) is lowered, becomes apparent and cannot be used as a device. In order to suppress such a narrow channel effect, a groove is formed in the substrate, and then wet oxidation at 950 ° C. is performed to give a curvature (roundness) to the shoulder of the active region. Discloses a technique for preventing the threshold voltage from decreasing by increasing the thickness of the gate oxide film.

  Japanese Patent Application Laid-Open No. 2-260660 (see Patent Document 2) rounds the shoulder of the active region by the following method. First, the element formation region of the semiconductor substrate is covered with a mask made of a laminated film of an oxide film and an oxidation-resistant film, and the substrate is thermally oxidized in this state, whereby one end of the element isolation region is formed on the element formation region. An oxide film is formed so as to bite. Next, the oxide film in the element isolation region is removed by wet etching using the oxidation resistant film as a mask, and then the substrate in the element isolation region is formed by reactive ion etching using the oxidation resistant film as a mask. After the groove is formed, the substrate is thermally oxidized to form a thermal oxide film on the inner wall surface of the groove, and the shoulder of the groove is rounded.

JP-A 63-2371 JP-A-2-260660

  As a result of studying a conventional element isolation groove forming method, the present inventor has newly found the following problems. As described above, in the step of forming the element isolation trench, first, a silicon nitride film is deposited on the silicon substrate via a thin thermal silicon oxide film, and then the element isolation region is formed by dry etching using the photoresist film as a mask. The silicon nitride film is removed. This silicon nitride film is used as a mask when the trench is formed by etching the silicon substrate in the element isolation region. However, since it has a property that is not easily oxidized, it prevents the surface of the underlying silicon substrate from being oxidized. Also functions as an oxidation resistant film.

  However, when a photoresist film is formed on the silicon nitride film, foreign matter is generated on the surface of the silicon nitride film. This foreign matter is considered to be mainly derived from components in the antireflection film provided in the lower layer of the photoresist film, and there is a problem that a manufacturing failure due to such a foreign matter is caused.

  An object of the present invention is to provide a technique for removing the cause of manufacturing defects induced in the element isolation groove forming step.

  Another object of the present invention is to provide a technique for improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A manufacturing method of a semiconductor device which is a preferred embodiment of the present invention includes the following steps.
(A) forming a silicon nitride film on the main surface of the silicon substrate via the first silicon oxide film;
(B) forming a photoresist film having an element isolation region opened on the second silicon oxide film after forming the second silicon oxide film on the silicon nitride film;
(C) after the step (b), performing a wet etching process on the second silicon oxide film exposed in the element isolation region;
(D) After the step (c), exposing the silicon substrate in the element isolation region by dry etching the silicon nitride film and the first silicon oxide film using the photoresist film as a mask;
(E) removing the photoresist film;
(F) After the step (e), a step of forming a groove in the silicon substrate in the element isolation region by dry etching the silicon substrate using the silicon nitride film as a mask;
(G) After a third silicon oxide film is formed on the silicon substrate including the inside of the groove, a chemical mechanical polishing method or a chemical mechanical polishing method is performed on the third silicon oxide film outside the groove. A step of forming an element isolation trench in the silicon substrate in the element isolation region by removing by etching back after leaving the third silicon oxide film inside the trench;
(H) A step of removing the silicon nitride film.

The method for manufacturing a semiconductor device of the present invention includes the following steps.
(A) forming a silicon nitride film on the main surface of the silicon substrate via the first silicon oxide film;
(B) forming a photoresist film having an element isolation region opened on the silicon nitride film;
(C) exposing the silicon substrate in the element isolation region by dry etching the silicon nitride film and the first silicon oxide film using the photoresist film as a mask;
(D) removing the photoresist film;
(E) after the step (d), forming a groove in the silicon substrate in the element isolation region by dry etching the silicon substrate using the silicon nitride film as a mask;
(F) After the step (e), by oxidizing each of the silicon substrate and the silicon nitride film exposed to the inside of the groove using an ISSG oxidation method that performs a radical oxidation reaction, Forming a silicon dioxide film and forming a third silicon oxide film on the upper surface and side walls of the silicon nitride film;
(G) After the step (f), after forming a fourth silicon oxide film on the silicon substrate including the inside of the groove, the fourth silicon oxide film outside the groove is formed by a chemical mechanical polishing method. Forming an element isolation trench in the silicon substrate in the element isolation region by removing and leaving the fourth silicon oxide film inside the trench;
(H) removing the silicon nitride film by wet etching;
(I) A step of performing a wet etching process on the first, third and fourth silicon oxide films after the step (h).

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  The cause of manufacturing defects induced in the element isolation trench process can be removed.

  In addition, the reliability of the semiconductor device can be improved.

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 2 is a main-portion cross-sectional view of the semiconductor substrate, illustrating the manufacturing process of the semiconductor device following FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 2; It is a principal part expanded sectional view of FIG. FIG. 4 is an essential part enlarged cross-sectional view of the semiconductor substrate, showing a manufacturing step of the semiconductor device following that of FIG. 3; FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, showing the manufacturing process of the semiconductor device following FIG. 5; It is a principal part expanded sectional view of FIG. FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 6; It is a principal part expanded sectional view of FIG. FIG. 9 is an essential part enlarged cross-sectional view of a semiconductor substrate showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 11 is an essential part enlarged cross-sectional view of a semiconductor substrate showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is an essential part enlarged cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 15; FIG. 17 is an essential part enlarged cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 17; It is a principal part expanded sectional view of FIG. FIG. 19 is an essential part enlarged cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 18; It is a principal part expanded sectional view of the semiconductor substrate which shows the manufacturing process of a comparative example. FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 20; FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating a manufacturing step of the semiconductor device following that of FIG. 22; It is a top view which shows the gate electrode formed in each of a p-type well and an n-type well. FIG. 24 is a main part cross-sectional view of the semiconductor substrate, showing the manufacturing process of the semiconductor device following FIG. 23; It is a principal part expanded sectional view of the semiconductor substrate which shows the manufacturing defect caused by the conventional manufacturing method.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  First, a manufacturing defect in the element isolation groove forming process newly found by the present inventor will be described. In the step of forming the element isolation trench, a silicon nitride film is first deposited on a silicon substrate via a thin thermal silicon oxide film, and then the silicon nitride film in the element isolation region is formed by dry etching using a photoresist film as a mask. Remove. This silicon nitride film is used as a mask when the trench is formed by etching the silicon substrate in the element isolation region. However, since it has a property that is not easily oxidized, it prevents the surface of the underlying silicon substrate from being oxidized. Also functions as an oxidation resistant film.

  However, when a photoresist film is formed on the silicon nitride film, foreign matter is generated on the surface of the silicon nitride film. This foreign matter is considered to be mainly derived from the components in the antireflection film provided under the photoresist film, and when the silicon nitride film in the element isolation region is dry etched with this foreign matter attached, the foreign matter is etched. The underlying silicon nitride film remains without being removed. Therefore, when the groove is formed in the silicon substrate by dry etching using the silicon nitride film as a mask, the silicon substrate is not etched in the lower part of the silicon nitride film remaining under the foreign matter. Silicon protrusions are formed.

  Since the tip of the needle-like protrusion is extremely thin, the tip of the protrusion is hardly oxidized even if the silicon substrate is thermally oxidized in the next step to form a thin silicon oxide film on the inner wall of the groove. In addition, the electric field tends to concentrate on the tip of the protrusion. Therefore, after forming a device isolation trench by embedding a silicon oxide film inside the trench, a gate oxide film is formed on the surface of the silicon substrate in the active region, and a gate electrode is formed on top of it to cross the device isolation trench. This causes a problem that dielectric breakdown occurs between the gate electrode and the needle-like silicon protrusion. FIG. 26 is a diagram showing a manufacturing failure caused by a conventional manufacturing method. The acicular silicon protrusion 31 formed in the element isolation groove 30 and the gate electrode 32 formed so as to cross over the element isolation groove 30 cause dielectric breakdown due to the acicular silicon protrusion. I understand.

  A method of manufacturing a MISFET according to the present embodiment will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 1, a p-type single crystal silicon substrate (hereinafter simply referred to as a substrate) 1 having a specific resistance of, for example, about 1 to 10 Ωcm is thermally oxidized at about 800 to 1100 ° C., and a film is formed on the surface. After forming a thin silicon oxide film 2 having a thickness of about 11 nm, a silicon nitride film 3 having a thickness of about 190 nm to 200 nm is deposited on the silicon oxide film 2 by a CVD method. The silicon nitride film 3 is used as a mask when the substrate 1 in the element isolation region is etched to form a groove. However, since the silicon nitride film 3 is difficult to be oxidized, the surface of the lower substrate 1 is prevented from being oxidized. Also functions as an oxidation resistant film. The silicon oxide film 2 below the silicon nitride film 3 relieves stress generated at the interface between the substrate 1 and the silicon nitride film 3 and causes defects such as dislocations on the surface of the substrate 1 due to the stress. Form to prevent.

  Next, as shown in FIG. 2, for example, a silicon oxide film 4 having a thickness of about 13 nm is formed as an insulating film on the silicon nitride film 3. The silicon oxide film 4 is formed by, for example, an ISSG (In-Situ Steam Generation) oxidation method (a method of performing a radical oxidation reaction on a heated substrate by directly introducing hydrogen and oxygen into a reduced-pressure heat treatment chamber). ). The silicon oxide film 4 can be deposited using a CVD method in addition to the ISSG oxidation method.

  Next, as shown in FIG. 3, an antireflection film (BARC: Bottom-Anti-Reflective Coating) 5 and a photoresist film 6 are formed on top of the silicon oxide film 4 and then exposed and developed. Thus, the antireflection film 5 and the photoresist film 6 in the region where the element isolation trench is to be formed are removed. At this time, foreign matter 7 is generated on the surface of the silicon oxide film 4 as shown in FIG. This foreign substance 7 is considered to be mainly derived from components constituting the antireflection film 5 formed on the silicon oxide film 4.

  Therefore, in this embodiment, after performing the exposure and development processes described above, the surface of the substrate 1 is washed with a hydrofluoric acid-based etching solution. By performing this hydrofluoric acid cleaning process, as shown in FIG. 5, the silicon oxide film 4 exposed in the region where the photoresist film 6 and the antireflection film 5 are removed (element isolation region) is etched. Foreign matter 7 adhering to the surface of the silicon oxide film 4 in this region is lifted off. That is, the insulating film (silicon oxide film 4) is formed as a protective film for preventing foreign matters from being formed on the silicon nitride film 3. Although the silicon oxide film 4 is interposed between the silicon nitride film 3 and the antireflection film 5 here, it is not limited to the silicon oxide film 4 and is removed by an etching solution that does not dissolve the silicon nitride film 3. Another thin film that can be formed, for example, a polycrystalline silicon film or an amorphous silicon film may be interposed. Also in this case, like the silicon oxide film 4, it can function as a protective film for preventing foreign matters from being formed on the silicon nitride film 3.

  Next, as shown in FIG. 6, the silicon nitride film 3 in the element isolation region and the underlying silicon oxide film 2 are removed by dry etching using the photoresist film 6 and the antireflection film 5 as a mask. The surface of the substrate 1 is exposed. At this time, if the silicon oxide film 2 remains on the exposed surface of the substrate 1, foreign matter is generated. Therefore, the substrate 1 is over-etched to completely remove the silicon oxide film 2. The overetching amount of the substrate 1 at this time may be about 10 to 30 nm.

  FIG. 7 is an enlarged cross-sectional view of the substrate 1 exposed by the dry etching. If the etching amount of the silicon oxide film 4 is insufficient during the hydrofluoric acid cleaning process described above, a part of the foreign matter 7 may remain without being lifted off. In this case, since the remaining foreign matter 7 becomes a mask for dry etching, as shown in the figure, when the silicon nitride film 3 and the underlying silicon oxide film 2 are dry-etched, an insulating film below the foreign matter 7 is formed. The (silicon oxide film 4, silicon nitride film 3 and silicon oxide film 2) are not etched and remain on the substrate 1. At this time, the foreign substance 7 remaining on the substrate 1 and the insulating film (the silicon oxide film 4, the silicon nitride film 3, and the silicon oxide film 2) below the foreign substance 7 are removed in a process described later.

  Next, as shown in FIG. 8, the photoresist film 6 and the antireflection film 5 are removed by ashing, and then SC-1 solution (ammonia water / hydrogen peroxide solution mixture) and SC-2 solution ( After cleaning the surface of the substrate 1 using a mixed solution of hydrochloric acid / hydrogen peroxide solution, cleaning with a hydrofluoric acid-based etching solution is performed. When this hydrofluoric acid cleaning treatment is performed, the silicon oxide film 2 exposed under the end of the silicon nitride film 3 (location indicated by the arrow in the drawing) is etched as shown in FIG. Also retracts inward (active region side). At this time, if the retraction amount of the silicon oxide film 2 is increased, the contact area between the silicon nitride film 3 and the silicon oxide film 2 is reduced, and peeling is likely to occur at the interface between them. It is desirable to stop within a range that does not greatly exceed the film thickness of 2.

  Next, as shown in FIG. 10, the substrate 1 is thermally oxidized at about 800 to 1100 ° C., so that the surface of the substrate 1 exposed in the element isolation region is thicker than the silicon oxide film 2 (for example, A silicon oxide film 8 having a thickness of about 20 nm is formed. By performing this thermal oxidation treatment, the silicon oxide film 8 grows in a bird's beak shape from the end of the silicon nitride film 3 toward the inside (active region side) thereof.

  Next, as shown in FIG. 11, the silicon oxide film 8 formed by the above thermal oxidation treatment is removed with a hydrofluoric acid-based etching solution. By performing this etching process, a gentle inclined surface is formed on the surface of the substrate 1 below the end of the silicon nitride film 3, and the silicon oxide film 4 on the silicon nitride film 3 is removed. Further, even when an insulating film (silicon oxide film 4, silicon nitride film 3 and silicon oxide film 2) due to residual foreign matter remains on the surface of the substrate 1 in the element isolation region, oxidation of the lower portion of the silicon nitride film 3 is performed. Since the silicon film 2 is removed, the silicon nitride film 3 and the foreign material 7 on the silicon film 2 are lifted off. That is, even if a part of the foreign matter 7 remains without being lifted off in the step of cleaning the silicon oxide film 4 on the silicon nitride film 3 with a hydrofluoric acid-based etching solution (see FIG. 5), the silicon oxide film 8 is It can be removed at the same time in the above-described step (see FIG. 11) of removing with an acid-based etching solution.

  Next, as shown in FIG. 12, the substrate 1 is dry-etched using the silicon nitride film 3 as a mask, thereby forming a groove 9a having a depth of about 330 nm in the substrate 1 in the element isolation region. At this time, by adjusting the composition of the etching gas and providing the side wall of the groove 9a with a taper of about 80 °, the silicon oxide film (11) is easily filled in the groove 9a in a later step.

  Next, the etching residue adhered to the inner wall of the groove 9a is removed by cleaning with the SC-1 solution, the SC-2 solution and dilute hydrofluoric acid, and then the substrate 1 is oxidized as shown in FIG. A silicon oxide film 10 having a thickness of about 20 nm is formed on the inner wall of the trench 9a. This silicon oxide film 10 recovers the dry etching damage generated on the inner wall of the groove 9a and alleviates stress generated at the interface between the silicon oxide film (11) embedded in the groove 9a and the substrate 1 in the next step. Form to do.

  In the present embodiment, an ISSG oxidation method is used as a method of oxidizing the substrate 1 to form the silicon oxide film 10 on the inner wall of the groove 9a. As described above, the ISSG oxidation method is a method in which hydrogen and oxygen are directly introduced into a reduced-pressure heat treatment chamber and a radical oxidation reaction is performed on a heated substrate, and not only silicon but also silicon nitride is oxidized. Has an oxidizing action. Therefore, when the silicon oxide film 10 is formed on the inner wall of the trench 9a by using this ISSG oxidation method, a silicon oxide film 10 ′ having a thickness of about 13 nm is formed on the upper surface and the side wall of the silicon nitride film 3 as shown in FIG. It is formed. The silicon oxide films 10 and 10 ′ formed by the ISSG oxidation method have higher etching resistance to hydrofluoric acid than the silicon oxide film deposited by the CVD method and the thermal oxide film formed by the existing wet oxidation method (etching rate). Is small). That is, the etching rate for a solution containing hydrofluoric acid is lower than that of an insulating film (silicon oxide film 11) formed by a CVD method in a later step. In other words, the silicon oxide films 10 and 10 'are formed as hydrofluoric acid resistant films. Thus, in the present embodiment, the silicon nitride film 3 that originally functions as an oxidation resistant film is actively oxidized to form the silicon oxide film 10 ′ on the surface thereof.

  Next, as shown in FIG. 15, an insulating film is deposited in the trench 9a. This insulating film can be deposited using the silicon oxide film 11 on the substrate 1 including the inside of the groove 9a by using, for example, a high-density plasma CVD method. The silicon oxide film 11 is deposited with a thickness such that the thickness of the upper portion of the trench 9a is about 600 nm, and the trench 9a is filled with the silicon oxide film 11 without any gap. A thin silicon nitride film (not shown) may be deposited between the inner wall of the trench 9a and the silicon oxide film 10. This silicon nitride film suppresses the silicon oxide film 10 formed on the inner wall of the groove 9a from growing thickly on the active region side when the silicon oxide film 11 embedded in the groove 9a is densified (baked). There is. As a method for forming this silicon nitride film, there are a method of depositing by a CVD method before forming the silicon oxide film 10 and a method of forming by performing a heat treatment in an atmosphere containing nitrogen.

  Next, a substrate 1 is thermally oxidized in a nitrogen atmosphere at about 1150 ° C. to perform a densification (baking) process for improving the film quality of the silicon oxide film 11 embedded in the trench 9a, and then to FIG. As shown, the surface of the silicon oxide film 11 above the groove 9a is polished by chemical mechanical polishing (CMP) to flatten the surface. This polishing is performed using the silicon nitride film 3 as a stopper, and the end point is when the height of the surface of the silicon oxide film 11 becomes the same as that of the silicon nitride film 3. Therefore, when this polishing is performed, the silicon oxide film 10 ′ on the upper surface of the silicon nitride film 3 is removed, but the silicon oxide film 10 ′ remains on the sidewall of the silicon nitride film 3. Through the steps so far, the element isolation trench 9 in which the silicon oxide film 11 is embedded in the trench 9a is completed. Further, here, the polishing of the silicon oxide film 11 is performed by the CMP method. However, as another method, for example, an etching back method may be used. Alternatively, the etch back method can be combined with the CMP method.

  Here, after the densification (baking) process, prior to the CMP process, the silicon oxide film 11 on the silicon nitride film 3 is removed in advance by dry etching using a photoresist film as a mask by dry etching or the like. It can also be done (not shown). As the pattern of the photoresist film at this time, the reverse pattern of the photoresist film used when dry etching the silicon nitride film 3 in the element isolation region can be used. In this manner, by removing the silicon oxide film 11 in advance, the amount of polishing of the silicon oxide film 11 in the CMP process can be reduced, so that the processing time of the CMP process can be shortened. Further, by reducing the polishing amount of the silicon oxide film 11, it is possible to reduce the variation in thickness after polishing in each element isolation region.

  Next, as shown in FIG. 17, the silicon oxide film 11 buried in the element isolation trench 9 and the silicon oxide film 10 ′ on the side wall of the silicon nitride film 3 are etched back, and the surfaces thereof are made as those of the silicon nitride film 3. Then, the silicon nitride film 3 is removed by wet etching using hot phosphoric acid, as shown in FIG. In the wet etching using hot phosphoric acid, the etching selectivity of silicon nitride to silicon oxide is about 30. Therefore, even if the silicon nitride film 3 is completely removed, the silicon oxide films 2, 10, 10 ′, 11 The etching amount is small. Therefore, when the silicon nitride film 3 is removed by wet etching using hot phosphoric acid, the surface of the silicon oxide film 2 on the substrate 1 in the active region and the element isolation trench 9 are removed as shown in FIG. A step is generated between the surface of the silicon oxide film 11 and the silicon oxide film 10 ′ formed on the side wall of the silicon nitride film 3 remains on the side wall of the silicon oxide film 11.

  Next, as shown in FIG. 20, in order to reduce the level difference, the silicon oxide films 2, 10 ', and 11 are wet-etched using a hydrofluoric acid-based etchant. When this wet etching is performed, only the upper surface is exposed to the etching solution in the vicinity of the central portion of the element isolation groove 9, whereas the upper surface and the side surface are exposed to the etching solution at the end of the element isolation groove 9. . However, the silicon oxide film 10 ′ formed by the ISSG oxidation method has a lower etching rate (about 0.83) for hydrofluoric acid than the silicon oxide film 11 deposited by the CVD method. When the silicon oxide film 10 ′ is formed on the side wall, the amount of recession (recess) of the silicon oxide film 11 at the end of the element isolation trench 9 is suppressed. On the other hand, when the silicon oxide film 10 ′ is not formed on the side wall of the silicon oxide film 11, the silicon oxide film 11 at the end of the element isolation trench 9 is formed at the center of the silicon oxide film as shown in FIG. Compared to the film 11, the film recedes downward (recess). Thus, according to the present embodiment in which the silicon oxide film 10 ′ having a lower etching rate than the silicon oxide film 11 embedded in the element isolation trench 9 is formed at the end of the element isolation trench 9, The amount of recession (recess) at the end can be reduced.

  Next, as shown in FIG. 22, the substrate 1 is thermally oxidized at about 800 to 1100 ° C. to form a silicon oxide film 12 having a thickness of about 15 nm on the surface of the substrate 1 in the active region. Subsequently, an n-type impurity (for example, phosphorus) is ion-implanted into a part of the substrate 1 through the silicon oxide film 12 and a p-type impurity (boron) is ion-implanted into the other part, and then the substrate 1 is heat-treated at about 950 ° C. By extending and diffusing the impurities, the p-type well 13 is formed in a part of the substrate 1 and the n-type well 14 is formed in the other part.

  Next, after removing the silicon oxide film 12 on the surface of the substrate 1 by wet etching using hydrofluoric acid, a gate insulating film 15 is formed on the substrate 1 as shown in FIG. The gate insulating film 15 is formed by thermally oxidizing the substrate 1 at about 800 to 850 ° C. to form a clean gate oxide film having a thickness of about 4 nm on the surface thereof. Subsequently, a gate electrode 16 is formed on the gate insulating film 15. The gate electrode 16 is made of a conductive film. For example, a polycrystalline silicon film doped with phosphorus is deposited on the gate insulating film 15 by a CVD method, and then a WSi (tungsten silicide) film is deposited thereon by a sputtering method. Further, after a silicon oxide film 17 is deposited thereon by CVD, these films are patterned by dry etching using a photoresist film (not shown) as a mask. FIG. 24 is a plan view showing the gate electrode 16 formed in each of the p-type well 13 and the n-type well 14.

  According to the present embodiment, the amount of recession (recess) at the end of the element isolation trench 9 is reduced, so that when the gate electrode material is dry-etched to form the gate electrode 16, Since no etching residue of the gate electrode material occurs along the boundary with the regions (p-type well 13 and n-type well 14), it is possible to prevent the occurrence of a short circuit between adjacent gate electrodes 16. .

Next, as shown in FIG. 25, n-type impurities (phosphorus or arsenic) are ion-implanted into the p-type well 13 to form an n ⁻ -type semiconductor region 18, and p-type impurities (boron) are implanted into the n-type well 14. After forming the p ⁻ -type semiconductor region 19 by ion implantation, a side wall spacer 20 is formed on the side wall of the gate electrode 16 by anisotropically etching the silicon oxide film deposited on the substrate 1 by the CVD method. . Thereafter, n-type impurity (phosphorus or arsenic) is ion-implanted into the p-type well 13 to form a high impurity concentration n ⁺ -type semiconductor region 21 (source, drain), and the p-type impurity (boron) is formed in the n-type well 14. ) Is implanted to form a high impurity concentration p ⁺ type semiconductor region 22 (source, drain). The n-channel MISFET (Qn) and the p-channel MISFET (Qp) are completed through the steps so far.

  According to the present embodiment, the amount of recession (recess) at the end of the element isolation trench 9 is reduced, so that the gate insulating film 15 formed on the surface of the substrate 1 in the active region becomes the end ( Since the phenomenon of locally thinning at the shoulder portion is suppressed, the kink characteristics of the n-channel MISFET (Qn) and the p-channel MISFET (Qp) can be suppressed.

  The following is a brief description of an effect obtained by the typical embodiment of the embodiments disclosed in the present application.

  In order to remove foreign substances caused by components constituting the antireflection film, a foreign substance can be removed by forming a silicon oxide film on the silicon nitride film and performing wet etching on the silicon oxide film. Further, the needle-like protrusions can be removed by performing thermal oxidation and wet cleaning after patterning the silicon nitride film. Thereby, the dielectric breakdown of the gate electrode caused by the needle-like protrusion can be prevented. Thereby, the reliability of the semiconductor device can be improved.

  When the gate electrode is formed by dry etching the gate electrode material by reducing the amount of recession (recess) at the end of the element isolation trench, the gate electrode material is formed along the boundary between the element isolation trench and the active region. Therefore, it is possible to prevent the occurrence of a defect in which adjacent gate electrodes are short-circuited. Thereby, the reliability of the semiconductor device can be improved.

  The phenomenon that the gate oxide film formed on the surface of the substrate in the active region is locally thinned at the end (shoulder) of the active region due to the reduction of the recess (recess) amount at the end of the element isolation trench. Therefore, the kink characteristics of the MISFET can be suppressed. Thereby, the reliability of the semiconductor device can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to an element isolation structure for forming a fine MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a technique effective when applied to a formation process thereof.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Silicon oxide film 3 Silicon nitride film 4 Silicon oxide film 5 Antireflection film 6 Photoresist film 7 Foreign substance 8 Silicon oxide film 9 Element isolation groove 9a Groove 10, 10'11, 12 Silicon oxide film 13 P-type well 14 n-type well 15 gate insulating film 16 gate electrode 17 silicon oxide film 18 n ⁻ type semiconductor region 19 p ⁻ type semiconductor region 20 sidewall spacer 21 n ⁺ type semiconductor region 22 p ⁺ type semiconductor region 30 element isolation trench 31 silicon protrusion 32 Gate electrode Qn n-channel MISFET
Qp p-channel MISFET

Claims (5)

A semiconductor device manufacturing method including the following steps:
(A) forming a silicon nitride film on the main surface of the silicon substrate via the first silicon oxide film;
(B) forming a photoresist film having an element isolation region opened on the silicon nitride film;
(C) exposing the silicon substrate in the element isolation region by dry etching the silicon nitride film and the first silicon oxide film using the photoresist film as a mask;
(D) removing the photoresist film;
(E) after the step (d), forming a groove in the silicon substrate in the element isolation region by dry etching the silicon substrate using the silicon nitride film as a mask;
(F) After the step (e), the silicon substrate and the silicon nitride film exposed inside the groove are each oxidized using an ISSG oxidation method that performs a radical oxidation reaction, thereby forming an inner wall of the groove. Forming a second silicon oxide film, and forming a third silicon oxide film on an upper surface and a sidewall of the silicon nitride film;
(G) After the step (f), after forming a fourth silicon oxide film on the silicon substrate including the inside of the groove, the fourth silicon oxide film outside the groove is formed by a chemical mechanical polishing method. Forming an element isolation trench in the silicon substrate in the element isolation region by removing and leaving the fourth silicon oxide film inside the trench;
(H) removing the silicon nitride film by wet etching;
(I) A step of performing a wet etching process on the first, third and fourth silicon oxide films after the step (h). 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step between the step (g) and the step (h).
(J) etching back the third and fourth silicon oxide films to cause the respective surfaces of the third and fourth silicon oxide films to recede below that of the silicon nitride film;
A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, further comprising, after the step (i),
(K) forming a fifth silicon oxide film on the surface of the silicon substrate in the active region surrounded by the element isolation trench by oxidizing the silicon substrate;
(L) After the step (k), introducing an impurity for forming a well in the silicon substrate;
A method for manufacturing a semiconductor device, comprising: 4. The method of manufacturing a semiconductor device according to claim 3, further comprising, after the step (l),
(M) forming a gate insulating film on the surface of the silicon substrate, and forming a MISFET gate electrode on the gate insulating film;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the ISSG oxidation method is a method in which hydrogen and oxygen are introduced into a chamber and the radical oxidation reaction is performed on the silicon substrate. Production method.

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