JP2008047691A - Semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve flatness of a substrate surface by a shallow trench isolation method. <P>SOLUTION: According to the semiconductor device manufacturing method, a trench 16 is formed on the surface of a semiconductor substrate 10 composed of silicon to surround an element placement region 10a by etching processing that uses a silicon oxide film 12 and a silicon nitride film 14 as a selection mask. Thereafter, a CVD oxide film is formed to embed the trench 16. The CVD oxide film is removed to be flat by CMP processing, and part of the CVD oxide film 18a is left in the trench 16. Anneal processing after implanting Ar<SP>+</SP>on top surface of the substrate reduces an etch rate of the surface of the film 18a. After the selection mask comprising the films 12, 14 is removed, a silicon oxide film is formed as a sacrifice film, and the sacrifice film is etch-removed. The amount of film 18a reduced by the etching is small, making an element separation region comprising the film 18a substantially flush with the element placement region 10a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an improvement of an element isolation method called an STI (Shallow Trench Isolation) method.

Conventionally, as the STI method, one in which argon ions Ar ⁺ are implanted into a silicon nitride film used as a selection mask during trench etching is known (see, for example, Patent Document 1), and an example thereof is described with reference to FIG. To do.

  For example, a mask silicon nitride film 3 is formed on the surface of a semiconductor substrate 1 made of silicon via a pad silicon oxide film 2 by a CVD (chemical vapor deposition) method. After a silicon oxide film 2 and a silicon nitride film 3 are overlaid, a hole corresponding to a desired trench is provided to form a selective mask made of films 2 and 3, and then a trench is formed on the substrate surface by selective etching using this selective mask. 4 is formed.

  Next, in order to reduce damage during etching, the inner wall of the trench 4 is oxidized to form a silicon oxide film 5. Then, a silicon nitride film 6 for preventing oxidation is formed by a CVD method so as to cover the silicon oxide film 5 and the silicon nitride film 3. Thereafter, a silicate glass film 7 is formed so as to fill the trench 4, and the film 7 is subjected to an annealing process for densification.

Next, a CMP (chemical / mechanical polishing) process is performed on the upper surface of the substrate to remove the silicate glass film 7 in a flat state until the silicon nitride film 6 is exposed. Then, Ar ⁺ is implanted into the upper surface of the substrate to damage the silicon nitride film 3 and increase the etch rate of the film 3. Thereafter, the silicon nitride films 6 and 3 are removed by etching with phosphoric acid. At this time, since the etching rate of the silicon nitride film 3 is increased, the removal time of the film 3 is shortened, and the silicon nitride film 6 is excessively etched between the silicon oxide film 2 and the silicate glass film 7 to be recessed. Can be prevented. The remaining silicate glass film 7 constitutes an element isolation region.
JP 2000-31267 A

According to the conventional technique described above, Ar ⁺ is also injected into the silicate glass film 7. However, Patent Document 1 does not describe anything about how the silicate glass film 7 is affected by Ar ⁺ related to implantation. Further, Patent Document 1 does not describe whether annealing is performed after Ar ⁺ is implanted.

  According to the research of the inventors of the present application, it has been found that there is a problem that the flatness of the substrate surface is impaired because the insulating film constituting the element isolation region is excessively etched in the STI method. A method of manufacturing a semiconductor device according to the inventor's research will be described with reference to FIGS.

  In the process of FIG. 1, for example, one main surface of a semiconductor substrate 10 made of silicon is subjected to thermal oxidation to form a pad silicon oxide film 12. Then, a mask silicon nitride film 14 is formed on the silicon oxide film 12 by a CVD method.

  Next, a photolithography and etching process is performed on the stack of the silicon oxide film 12 and the silicon nitride film 12 to form a selective mask for trench etching having a closed loop hole K surrounding the element placement region 10a. The element arrangement area 10a is an area in which circuit elements such as MOS transistors are to be arranged. A closed loop trench 16 is formed on the substrate surface by selective etching using the formed selective mask. Thereafter, a silicon oxide film 18 is formed by CVD so as to fill the trench 16 and cover the silicon nitride film 14.

  In the process of FIG. 2, the upper surface of the substrate is subjected to CMP to remove the silicon oxide film 18 until the silicon nitride film 14 is exposed, and a part 18 a of the silicon oxide film 18 remains in the trench 16.

  In the process of FIG. 9, the silicon nitride film 14 and the silicon oxide film 12 are sequentially removed by wet etching. At this time, since the silicon oxide film 18a has a relatively high etch rate, the portion indicated by the broken line is removed.

  In the process of FIG. 10, a silicon oxide film 20 as a sacrificial film is formed by performing a thermal oxidation process on the upper surface of the substrate. Then, in the process of FIG. 11, the silicon oxide film 20 is removed by a wet etching process to expose a clean surface on one main surface of the substrate 10. At this time, since the silicon oxide film 18a is removed as indicated by a broken line, the upper surface of the silicon oxide film 18a is lower than the upper surface of the element arrangement region 10a, and a step is generated. The silicon oxide film 18a remaining in the trench 16 constitutes an element isolation region.

  In the process of FIG. 12, a silicon oxide film 22 for a gate insulating film is formed on one main surface of the substrate 10 by thermal oxidation. Then, a polysilicon layer 24 for a gate electrode (or wiring) is formed on the silicon oxide film 22 by a CVD method. The polysilicon layer 24 is doped with impurities for reducing resistance during or after deposition.

  In the process of FIG. 13, the polysilicon layer 24 is patterned according to a gate electrode (or wiring) pattern by photolithography and dry etching. Reference numerals 24a to 24c denote patterned polysilicon layers, respectively.

  According to the manufacturing method described above, in the step of FIG. 11, a step is generated at the boundary between the silicon oxide film 18a constituting the element isolation region and the element arrangement region 10a, and the flatness of the substrate surface is deteriorated. For this reason, (a) a DOF (depth of focus) margin is lowered in the exposure process at the time of polysilicon patterning in FIG. 13, and (b) a polysilicon residue P remains at the time of polysilicon patterning in FIG. (C) there is a problem that the silicon oxide film 22 for the gate insulating film has insufficient withstand voltage at the portion Q covering the step.

  An object of the present invention is to provide a novel method for manufacturing a semiconductor device capable of improving the flatness of a substrate surface.

The manufacturing method of the semiconductor device according to the present invention is as follows:
Forming a selection mask having a closed loop-shaped hole surrounding the element arrangement region on one main surface of the semiconductor substrate;
Forming a closed loop-shaped trench in the one main surface by selective etching using the selective mask;
Forming a first insulating film covering the selection mask so as to fill the trench;
Removing the first insulating film in a flat shape so as to leave a part of the first insulating film in the trench;
An etch rate reducing substance is ion-implanted into the surface layer portion of the first insulating film remaining in the trench in a state where the selection mask is present on the one main surface, and an annealing treatment is performed to etch the surface layer portion. Reducing the process,
After the annealing treatment, removing the selection mask to expose the one main surface;
Oxidizing the exposed portion of the one main surface to form a second insulating film as a sacrificial film;
And a step of removing the second insulating film by etching while allowing etching of the surface layer portion of the first insulating film in the trench.

  According to the method of manufacturing a semiconductor device of the present invention, the etch rate reducing substance is ion-implanted into the surface layer portion of the first insulating film remaining in the trench, and an annealing process is performed, whereby the etch rate of the surface layer portion is increased. Reduced. Therefore, when the first insulating film and the second insulating film are both silicon oxide films, for example, when the second insulating film is removed by etching, the surface loss of the first insulating film is suppressed, and the first insulating film is suppressed. The element isolation region made of an insulating film forms a substantially flat surface with the element arrangement region.

  In the method of manufacturing a semiconductor device according to the present invention, in the step of forming the selection mask, the selection mask is configured by stacking a mask insulating film on a pad insulating film, and in the step of removing the selection mask, the mask insulating film is removed. After that, the pad insulating film may be removed by an etching process while allowing the surface layer portion of the first insulating film in the trench to be etched. In this case, when the pad insulating film is removed by etching using both the pad insulating film and the first insulating film as, for example, a silicon oxide film, film loss of the surface layer portion of the first insulating film is suppressed. Therefore, it is useful to make the element isolation region almost the same level as the element arrangement region.

  According to the present invention, since the etching rate of the surface layer portion of the first insulating film in the trench is reduced by the ion implantation process so as to suppress the film loss of the surface layer portion, the element isolation region is separated from the element arrangement region. An effect is obtained that can form a substantially flat surface (no step is formed).

  1 to 7 show a method of manufacturing a semiconductor device according to an embodiment of the present invention, and steps (1) to (7) corresponding to the respective drawings will be sequentially described.

  (1) A mask silicon nitride film 14 is formed on one main surface of a semiconductor substrate 10 made of, for example, silicon via a pad silicon oxide film 12 in the same manner as described above. The thickness of the silicon oxide film 12 can be about 100 to 300 mm, and the thickness of the silicon nitride film can be about 1000 to 2000 mm.

  Next, a closed-loop hole K is formed in the stacked layer of the silicon oxide film 12 and the silicon nitride film 14 in the same manner as described above, and a selection mask made of the stacked layer is obtained. Then, a closed-loop trench 16 is formed on the substrate surface by selective etching using this selective mask. The trench 16 is formed so as to surround the element arrangement region 10a. Thereafter, a silicon oxide film 18 is formed on the upper surface of the substrate as described above. The thickness of the silicon oxide film 18 can be about 5000 to 7000 mm.

  (2) As described above, the silicon oxide film 18 is removed in a flat shape, and a portion 18a of the silicon oxide film 18 is left in the trench.

(3) An etch rate reducing substance is ion-implanted into the surface layer portion of the silicon oxide film 18a in the trench 16 in a state where the stack (selection mask) of the silicon oxide film 12 and the silicon nitride film 14 exists. As an example of the etch rate reducing substance, Ar is ion-implanted. The Ar ⁺ implantation can be performed with an acceleration energy of 40 to 80 keV and a dose of about 2 × 10 ¹⁵ to 4 × 10 ¹⁵ cm ⁻² . At the time of ion implantation, the stack of the silicon oxide film 12 and the silicon nitride film 14 acts as a mask, so that the implantation of Ar ⁺ into the substrate 10 is prevented. After ion implantation, the silicon oxide film 18a is annealed to reduce damage and defects. As the annealing process, an RTA (rapid thermal annealing) process can be used. As an example, the annealing can be performed at 1150 ° C. for about 12 seconds.

  (4) The silicon nitride film 14 and the silicon oxide film 12 are sequentially removed by wet etching. At this time, the surface layer portion of the silicon oxide film 18a has a reduced etch rate, so that the amount of film reduction is small.

  (5) A silicon oxide film 20 as a sacrificial film is formed on one main surface of the substrate 10 by thermal oxidation.

  (6) The silicon oxide film (sacrificial film) 20 is removed by a wet etching process and a cleaning process is performed on the upper surface of the substrate to expose a clean surface on one main surface of the substrate 10. In the wet etching process of the silicon oxide film 20, since the etch rate of the surface layer portion of the silicon oxide film 18a is reduced, the amount of film reduction of the surface layer portion can be reduced, and the element isolation region (silicon oxide film 18a) It forms an almost flat surface with the element arrangement region 10a.

  Next, a silicon oxide film 22 for a gate insulating film is formed on one main surface of the substrate 10 by thermal oxidation. Then, a polysilicon layer for a gate electrode (or wiring) is formed on the upper surface of the substrate by the CVD method so as to cover the silicon oxide films 18a and 22. The polysilicon layer 24 is doped with impurities for reducing resistance during or after deposition.

  (7) The polysilicon layer 24 is patterned according to the gate electrode (or wiring) pattern by photolithography and dry etching. Reference numerals 24a to 24c denote patterned polysilicon layers, respectively.

FIG. 8 shows the relationship between the Ar ⁺ dose and the wet etch rate for a silicon oxide film formed by the CVD method. An experiment for obtaining such a relationship was performed as follows. First, first to sixth six silicon wafers were prepared. Then, a silicon oxide film having a thickness of about 2000 mm is formed on the surface of each wafer by a low pressure CVD method using TEOS (tetra-ethyl-ortho-silicate) as a raw material, and the thickness of the silicon oxide film for each wafer. Was measured. Ar ⁺ was implanted into the second to sixth wafers excluding the first wafer. The Ar ⁺ implantation is performed in two steps (first step: 40 keV, second step: 80 keV) with different acceleration energies for any of the second to sixth wafers, and the dose amount is the second wafer: 2. × 10 ¹⁴ cm ⁻² , third wafer: 6 × 10 ¹⁴ cm ⁻² , fourth wafer: 1 × 10 ¹⁵ cm ⁻² , fifth wafer: 2 × 10 ¹⁵ cm ⁻² , sixth wafer: 4 × 10 ¹⁵ cm ⁻² . Next, RTA treatment (1150 ° C., 12 seconds) was performed on the silicon oxide films of the first to sixth wafers. A wet etching process (130 BHF, 50 seconds) was performed on the silicon oxide films of the first to sixth wafers. Thereafter, the thickness of the silicon oxide film was measured for each wafer, and the etch rate of the silicon oxide film (film thickness measurement value before etching−film thickness measurement value after etching) was determined for each wafer.

According to FIG. 8, the silicon oxide film (without Ar ⁺ implantation) of the first wafer has an etch rate of 560 mm, whereas the fifth and sixth wafers (Ar ⁺ dose 2 × 10 ¹⁵ cm ^−2). From the above, it can be seen that the etch rate is reduced to about 450%. Note that the two-step implantation as described above can also be adopted in the ion implantation step of FIG. 3, and the above-described wet etching process can also be used in the silicon oxide film etching of FIGS.

  According to the manufacturing method according to the above-described embodiment, since the flatness of the substrate surface is improved as shown in FIG. 6, the DOF margin is improved in the exposure process at the time of polysilicon patterning in FIG. Is possible. Further, there is no situation in which polysilicon residues remain during the polysilicon patterning shown in FIG. 7, and short circuit defects can be prevented. Further, as shown in FIGS. 6 and 7, since the silicon oxide film 22 for the gate insulating film does not cover the step at the boundary between the element isolation region (silicon oxide film 18a) and the element arrangement region 10a, the breakdown voltage is reduced. Can be prevented.

  Note that the etch rate reducing material is not limited to Ar, and F or the like may be used.

It is sectional drawing which shows the silicon oxide film formation process in the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. It is sectional drawing which shows the planarization process following the process of FIG. FIG. 3 is a cross-sectional view showing an ion implantation step and an annealing step following the step of FIG. FIG. 4 is a cross-sectional view showing a selective mask removing process following the process of FIG. 3. FIG. 5 is a cross-sectional view showing a silicon oxide film forming step that follows the step of FIG. 4. FIG. 6 is a cross-sectional view showing a silicon oxide film removing process, a silicon oxide film forming process, and a polysilicon deposition process following the process of FIG. 5. FIG. 7 is a cross-sectional view showing a polysilicon patterning step following the step of FIG. 6. It is a graph which shows the relationship between Ar ⁺ dose amount and wet etch rate about a silicon oxide film. It is sectional drawing which shows the selective mask removal process in the manufacturing method of the semiconductor device which concerns on inventors' research. FIG. 10 is a cross-sectional view showing a silicon oxide film forming step following the step of FIG. 9. FIG. 11 is a cross-sectional view showing a silicon oxide film removal step that follows the step of FIG. 10. FIG. 12 is a cross-sectional view showing a silicon oxide film formation step and a polysilicon deposition step following the step of FIG. 11. FIG. 13 is a cross-sectional view showing a polysilicon patterning step following the step of FIG. 12. It is sectional drawing for demonstrating an example of the conventional STI method.

Explanation of symbols

  10: semiconductor substrate, 12, 18, 20, 22: silicon oxide film, 14: silicon nitride film, 16: trench, 24: polysilicon layer.

Claims (2)

Forming a selection mask having a closed loop-shaped hole surrounding the element arrangement region on one main surface of the semiconductor substrate;
Forming a closed loop-shaped trench in the one main surface by selective etching using the selective mask;
Forming a first insulating film covering the selection mask so as to fill the trench;
Removing the first insulating film in a flat shape so as to leave a part of the first insulating film in the trench;
An etch rate reducing substance is ion-implanted into the surface layer portion of the first insulating film remaining in the trench in a state where the selection mask is present on the one main surface, and an annealing treatment is performed to etch the surface layer portion. Reducing the process,
After the annealing treatment, removing the selection mask to expose the one main surface;
Oxidizing the exposed portion of the one main surface to form a second insulating film as a sacrificial film;
And a step of removing the second insulating film by etching while allowing etching of a surface layer portion of the first insulating film in the trench.   In the step of forming the selection mask, the selection mask is configured by stacking a mask insulating film on a pad insulating film, and in the step of removing the selection mask, the mask insulating film is removed and then the first mask in the trench is formed. The method of manufacturing a semiconductor device according to claim 1, wherein the pad insulating film is removed by an etching process while allowing etching of a surface layer portion of the insulating film.

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