JP2003017595A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a comparatively small electronic trap having comparatively high gate voltage resistance without concentrating stress and an electric field on a semiconductor substrate and the end of an amorphous silicon film. SOLUTION: The semiconductor device is provided with the semiconductor substrate 10 having a substrate surface 12 forming an element, a gate electrode 30 insulated electrically from the semiconductor substrate and having an opposite face 32 opposite to the substrate surface 12, and a trench 60 formed so as to penetrate the gate electrode and reach the semiconductor substrate. A boundary part 15 between a substrate side 14 and the substrate surface constituting part of the side of the trench out of the semiconductor substrate and a boundary part 35 between a gate side 34 and the opposite face constituting part of the side out of the gate electrode make a curved face shape having a radius of curvature 30 Å or longer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which elements are isolated by STI.

[0002]

2. Description of the Related Art Conventionally, in order to miniaturize a semiconductor device, instead of a method of element isolation by a selective oxidation method,
A method of element isolation by STI (Shallow Trench Isolation) is used. By providing a trench, the STI electrically insulates an element region, which forms an element, of a semiconductor device from other regions. That is, in STI, a trench is formed in the element isolation region instead of the selective oxidation method.

FIG. 8 shows a semiconductor device 7 having a conventional STI.
It is an expanded sectional view in the middle of manufacture of 00. A gate insulating film 20 is formed on the substrate surface of the semiconductor substrate 10. A gate electrode 30 made of an amorphous silicon film is formed on the gate insulating film 20. A silicon nitride film 40 is deposited on the gate electrode 30.
A silicon oxide film 50 is deposited on the silicon nitride film 40.

The silicon nitride film 40 and the silicon oxide film 50 are etched into a predetermined pattern by using photolithography. Next, the gate electrode 30, the gate insulating film 20, and the semiconductor substrate 10 are etched using the silicon oxide film 50 as a mask. By this etching, the trench 60 reaching the semiconductor substrate 10 is formed.

Subsequently, the side surface and the bottom surface of the trench 60 are oxygen O 2 by RTO (Rapid Thermal Oxidation).
₂ Oxidized at 1000 ° C in an atmosphere. FIG. 8 shows an enlarged cross-sectional view of the trench 60 and its periphery after the RTO is processed.

A silicon oxide film 70 is formed by RTO on the side and bottom surfaces of the trench 60. The semiconductor substrate 10 and the like are protected by the silicon oxide film 70.

[0007]

Generally, the diffusion coefficient of oxidizing species into a silicon single crystal used as a semiconductor substrate is smaller than that of amorphous silicon.

Therefore, in the oxidation process by RTO, the film thickness T ₂ of the silicon oxide film 70b formed on the semiconductor substrate 10 made of silicon single crystal is equal to the film thickness T _{1 of the} silicon oxide film 70a formed on the gate electrode 30. Thin compared to.

In addition, as compared with a flat surface portion of a silicon single crystal or amorphous silicon, an edge portion such as a side or a corner at a boundary between the surfaces is stressed as oxidation progresses. Is added. Oxidizing species are less likely to diffuse at the end of the silicon single crystal or amorphous silicon to which stress is applied. Therefore, there occurs a phenomenon in which the flat surface of silicon single crystal or amorphous silicon is easily oxidized, while the edges are difficult to be oxidized.

FIG. 2B shows an end portion of the semiconductor substrate 10 surrounded by a broken line circle in FIG. 8 and the gate electrode 30.
It is an enlarged view of an end portion of FIG. Since the edge of the semiconductor substrate 10 and the edge of the gate electrode 30 are less likely to be oxidized than their flat surfaces, the oxide film formed is closer to the edge of the semiconductor substrate 10 and the edge of the gate electrode 30. Is thinner than the oxide film formed on the flat surface. Therefore, the end portion of the semiconductor substrate 10 and the end portion of the gate electrode 30 have a pointed shape (see the broken line circle in FIG. 2B). The sharper the edges of the semiconductor substrate 10 and the gate electrode 30, the more stress is likely to be applied to those edges, and the electric field is more likely to concentrate at those edges.

Further, since the thickness of the silicon oxide film 70b is smaller than that of the silicon oxide film 70a, the edge of the gate electrode 30 when viewed from the direction perpendicular to the substrate surface 12 of the semiconductor substrate 10. The portion overlaps with the flat portion of the substrate surface 12 (see the alternate long and short dash line in FIG. 2B).

The greater the stress applied to the gate electrode 30, the more electrons trapped in the gate electrode 30 (hereinafter referred to as electron traps). The threshold voltage changes as the number of electron traps increases (see FIG. 6).

Due to the change in the threshold voltage, the semiconductor device 70
0 does not operate normally. When the gate electrode 30 is used as a floating gate electrode of a memory, there is a problem that the number of times that read / write is possible (hereinafter referred to as R / W number) is reduced (see FIG. 7).

Further, when viewed from the direction perpendicular to the substrate surface 12 of the semiconductor substrate 10, the end portion of the gate electrode 30 where the electric field tends to concentrate overlaps with the flat portion of the substrate surface 12, so that the semiconductor device 700. However, there is a problem that the gate breakdown voltage of the device decreases.

Therefore, an object of the present invention is to provide a semiconductor device in which stress and electric field are not concentrated on the edge of a semiconductor substrate or an amorphous silicon film, electron traps are relatively small, and gate breakdown voltage is relatively high. Is.

[0016]

A semiconductor device according to an embodiment of the present invention has a semiconductor substrate having a substrate surface on which elements are formed, and a facing surface facing the substrate surface,
A gate electrode electrically insulated from the semiconductor substrate by a gate insulating film, and an element region and another region of the substrate surface where the element is formed so as to penetrate the gate electrode and reach the semiconductor substrate. A first boundary portion between a substrate side surface and a substrate surface forming a part of the side surface of the trench of the semiconductor substrate, and a part of the side surface of the trench of the gate electrode. The second boundary portion between the side surface of the gate and the facing surface constituting the above has a curved surface shape having a radius of curvature of 30 Å or more.

A semiconductor device according to an embodiment of the present invention has a semiconductor substrate having a substrate surface on which elements are formed, and a facing surface facing the substrate surface, and electrically connected to the semiconductor substrate by a gate insulating film. An insulated gate electrode and a trench that penetrates through the gate electrode and reaches the semiconductor substrate and electrically separates an element region on the substrate surface where an element is formed from other regions. Prepare,
A first boundary portion between a substrate side surface forming a part of a side surface of a trench of a semiconductor substrate and a substrate surface, and between a gate side surface forming a part of a side surface of a trench of a gate electrode and a facing surface. A second boundary appears to be nearly coincident when viewed from a direction perpendicular to the substrate surface.

Preferably, the film thicknesses of the oxide films formed on the side surface of the substrate and the side surface of the gate are substantially equal to each other.

The gate electrode may be a floating gate electrode whose periphery is electrically insulated.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes a step of forming a gate insulating film on a semiconductor substrate and a step of forming a gate electrode on the gate insulating film so as to electrically insulate the semiconductor substrate. A step of forming, a step of etching the gate electrode, the gate oxide film, and the semiconductor substrate to form a trench that electrically separates an element region in which an element is formed from other areas of the substrate surface, and a semiconductor And oxidizing the side surface of the substrate forming a part of the side surface of the trench and the side surface of the gate electrode forming a part of the side surface of the trench in a hydrogen H ₂ and oxygen O ₂ atmosphere.

A method of manufacturing a semiconductor device according to another embodiment of the present invention includes a step of forming a gate insulating film on a semiconductor substrate, and a gate for electrically insulating the gate insulating film from the semiconductor substrate. Forming electrodes,
A step of etching the gate electrode, the gate oxide film and the semiconductor substrate to form a trench that electrically separates the element region where the device is formed and the other region of the substrate surface; And oxidizing the side surface of the substrate forming a part of the side surface and the side surface of the gate of the gate electrode forming a part of the side surface of the trench in an ozone O ₃ atmosphere.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The present embodiment does not limit the present invention.

1 (A), 1 (B) and 1 (C)
FIG. 6 is an enlarged cross-sectional view of a trench of a semiconductor device 100 having an STI and its periphery according to an embodiment of the present invention. The semiconductor device 100 is manufactured in the order of FIG. 1 (A), FIG. 1 (B) and FIG. 1 (C).

First, referring to FIG. 1A, a gate insulating film 20 made of, for example, a silicon oxide film having a thickness of about 10 nm is formed on the surface of a semiconductor substrate 10. On the gate insulating film 20, a gate electrode 30 formed of, for example, an amorphous silicon film having a thickness of about 60 nm is formed. A silicon nitride film 40 is formed on the gate electrode 30.
Have been deposited. A silicon oxide film 50 is deposited on the silicon nitride film 40.

The silicon nitride film 40 and the silicon oxide film 50 are etched into a predetermined pattern by utilizing photolithography. Next, using the silicon oxide film 50 as a mask, the gate electrode 30 and the gate insulating film 2
0 and the semiconductor substrate 10 are etched. By this etching, the gate electrode 30 and the gate insulating film 2
A trench 60 that penetrates 0 and reaches the semiconductor substrate 10 is formed.

Subsequently, referring to FIG. 1B, the side surface portion and the bottom surface portion of the trench 60 formed by etching are oxidized by RTO at 1000 ° C. in an atmosphere of hydrogen H ₂ and oxygen O ₂ . FIG. 1B shows an enlarged cross-sectional view of the trench 60 and its periphery after the oxidation treatment in a hydrogen H ₂ and oxygen O ₂ atmosphere. The film thicknesses T ₃ and T ₄ of the oxide films formed on the side surface of the semiconductor substrate 10 and the side surface of the gate electrode 30 are substantially equal. In the case of the present embodiment, the film thickness T ₃ and the film thickness T
₄ is about 6 nm.

Further, referring to FIG. 1C, the silicon oxide material 80 is filled in the trench 60 with HDP (High Density Plas).
sma) method. Silicon oxide material 80 is CMP
After being planarized by the method, the semiconductor substrate 10 is heated in a nitrogen atmosphere at about 900 ° C. After exposing the semiconductor substrate 10 to the NH ₄ F solution, the silicon nitride film 40 is removed by phosphoric acid treatment at about 150 ° C. After that, silicon oxide material 80
A doped polysilicon 90 containing phosphorus is formed on the gate electrode 30 by the low pressure CVD method.

Further, after that, through a predetermined process, the semiconductor device 100 in which the elements are separated by the trench 60 is formed.

FIG. 2A is an enlarged cross-sectional view of the end portion of the semiconductor substrate 10 and the end portion of the gate electrode 30 in the semiconductor devices 100 and 700 before the oxidation treatment by RTO. Figure 2
(B) is a conventional semiconductor device 7 after oxidation treatment by RTO
End of semiconductor substrate 10 and gate electrode 3
It is an expanded sectional view of the edge part of 0. FIG. 2C is an enlarged cross-sectional view of the end portion of semiconductor substrate 10 and the end portion of gate electrode 30 in semiconductor device 100 according to the embodiment of the present invention after the oxidation treatment by RTO.

FIG. 2C shows an enlarged view of the end portion of the semiconductor substrate 10 and the end portion of the gate electrode 30 which are surrounded by a broken line circle in FIG. 1B.

As shown in FIG. 2C, the semiconductor device 100 according to the present embodiment is electrically insulated from the semiconductor substrate 10 and faces the substrate surface 12 of the semiconductor substrate.
2 and a trench 60 formed to penetrate the gate electrode 30 and reach the semiconductor substrate 10. Semiconductor substrate 10 and gate electrode 30
A gate insulating film 20 is formed between the semiconductor substrate 1 and
0 and the gate electrode 30 are electrically insulated.

The semiconductor substrate 10 is formed of, for example, a silicon single crystal. The gate insulating film 20 is, for example, a silicon oxide film formed by oxidizing the semiconductor substrate 10. The gate electrode 30 is formed by depositing amorphous silicon, for example.

Oxidation treatment by RTO gives a semiconductor substrate.
A silicon oxide film 70a is formed on the substrate side surface 14 of the plate 10.
On the gate side surface 34 of the gate electrode 30
The chemical film 70b is formed. In this embodiment,
Thickness T of the recon oxide film 70a _ThreeAnd silicon oxide film 7
0b film thickness T_FourAre almost equal.

As is conventional, the sides of trench 60 and
When oxidizing the bottom surface, oxygen O _Two(Dry oxygen) atmosphere
When oxidizing in air, the diffusion coefficient of oxidizing species is relatively small.
Sai. In particular, the oxidizing species should be silicon single rather than amorphous silicon.
The diffusion coefficient into the crystal is small. Therefore, as shown in FIG.
As described above, the thickness T of the silicon oxide film 70b is_TwoIs silicon
Thickness T of oxide film 70a₁Formed thinner.

On the other hand, in the present embodiment, hydrogen H _{2 is used} when the side surface and the bottom surface of the trench 60 are oxidized.
When the oxidation treatment is performed in an oxygen O ₂ atmosphere, the diffusion coefficient of the oxidizing species becomes relatively large. In particular, the increase of the diffusion coefficient is more remarkable in silicon single crystal than in amorphous silicon. Therefore, the difference in the oxidation rate between the silicon single crystal and the amorphous silicon becomes small. Therefore, the silicon oxide film 70a
Thickness _{T 3} and the thickness _{T 4} of the silicon oxide film 70b is substantially equal to. In the present embodiment, hydrogen H ₂ and oxygen O ₂ are reacted at high temperature by RTO to generate oxygen radicals. The oxygen radicals become oxidizing species.
However, even if the oxidizing process is performed using O ₃ (ozone) instead of hydrogen H ₂ and oxygen O ₂ , the same shape as the semiconductor device 100 according to the present embodiment can be obtained.

In the present embodiment, the relatively large diffusion coefficient of the oxidizing species promotes the oxidation of the end portion of the semiconductor substrate 10 and the end portion of the gate electrode 30 where stress is easily applied. Therefore, in the semiconductor device 100 according to the present embodiment, the end portion of the semiconductor substrate 10 and the gate electrode 30 are provided.
The edges are not as sharp as they used to be.

That is, the semiconductor device 10 according to the present embodiment.
0, the boundary portion 15 between the substrate side surface 14 that forms a part of the side surface of the trench 60 in the semiconductor substrate 10 and the substrate surface 12, and the gate side surface that forms a part of the side surface of the trench 60 in the gate electrode 30. A boundary portion 35 between 34 and the facing surface 12 is formed into a curved surface shape having a radius of curvature of 30 Å or more. In the conventional semiconductor device 700, the boundary portion of the semiconductor substrate 10 and the boundary portion of the gate electrode 30 are not clear.
It is expressed as an edge of 0 and an edge of the gate electrode 30. Therefore, the boundary portion 15 of the semiconductor device 100 according to the present embodiment is
The boundary portion 35 is substantially the same as the end portion of the semiconductor substrate 10 and the end portion of the gate electrode 30, respectively.

Since the boundary portions 15 and 35 have a radius of curvature equal to or larger than a certain radius of curvature, the concentration of stress on the boundary portions 15 and 35 is relieved. Further, local concentration of the electric field on the boundary portion 15 and the boundary portion 35 is alleviated.

Since the film thickness T ₃ of the silicon oxide film 70a and the film thickness T ₄ of the silicon oxide film 70b are substantially equal to each other, in the semiconductor device 100 according to the present embodiment, it is viewed from the direction perpendicular to the substrate surface 12. Sometimes the substrate surface 12
And the boundary portion 35 do not overlap. Furthermore, the facing surface 12
Boundary 15 does not overlap. That is, when viewed from the direction perpendicular to the substrate surface 12, the boundary portion 35 and the boundary portion 15 overlap each other.

Therefore, even if the electric field is concentrated on the boundary portions 15 and 35, the gate insulating film 20 is less likely to be destroyed. Therefore, the yield of semiconductor devices is improved.

FIG. 3 is a diagram showing a graph showing the relationship between the radius of curvature of the boundary 15 and the boundary 35 and the variation (ΔVge) of the electron trap. This graph shows the amount of change in electron traps after a constant current stress of 0.1 A / cm ² was applied to the gate insulating film 20 from the gate electrode 30 for 20 seconds and a charge of about 2 C / cm ² was injected.

When the radii of curvature of the boundary portions 15 and 35 are smaller than about 30Å, ΔVge is large and the amount of electron traps is large. On the other hand, the boundary 15 and the boundary 3
When the radius of curvature of 5 is about 30 Å or more, ΔVge is small and the amount of electron traps is small. Also, the radius of curvature is about 30.
When it exceeds Å, the degree of decrease in ΔVge decreases. Therefore, the radii of curvature of the boundary portion 15 and the boundary portion 35 are about 30Å
In the above case, stress and electric field concentration on the boundary portions 15 and 35 are effectively alleviated.

FIG. 4 is a graph showing the relationship between the stress of the gate insulating film 20 and the electron trap. The horizontal axis of the graph shown in FIG. 4 represents the stress in the gate oxide film 20,
The vertical axis represents the amount of change in electron trap (ΔVge). This graph shows that in each of the conventional semiconductor device 700 and the semiconductor device 100 according to the present embodiment, a constant current stress of 0.1 A / cm ² is applied to the gate insulating film 20 from the gate electrode 30 for 20 seconds, and then approximately 2 C / cm ^{2 is applied.} The amount of change in the electron traps after the injection of the charges is shown. According to FIG. 4, the gate electrode 2
The smaller the stress in 0, the smaller ΔVge.

As the difference between the thickness of the silicon oxide film 70a and the thickness of the silicon oxide film 70b increases, the gate insulating film 2
The stress of 0 also increases, and the stress of the gate insulating film 20 increases as the stress of the boundary 15 and the boundary 35 increases. Therefore, it can be understood that the amount of electron traps in the semiconductor device 100 according to the present embodiment is smaller than the amount of electron traps in the conventional semiconductor device 700.

FIG. 5 is a graph showing a general relationship between the time for which a constant current is applied to the gate insulating film 20 and the amount of electron traps (Vge). From FIG. 5, it can be seen that the longer the constant current is applied to the gate insulating film 20, the larger the amount of electron traps.

FIG. 6 is a graph showing a general relationship between the threshold voltage (Vt) of the semiconductor device and the amount of electron traps (ΔVge) in the gate insulating film 20. It can be seen from FIG. 6 that the threshold voltage of the semiconductor device changes in proportion to the amount of electron traps.

The semiconductor device 100 according to the present embodiment is
The amount of electrons (ΔVge) trapped in the gate insulating film 20 is smaller than that of the conventional semiconductor device 700 (see FIG. 5).
Therefore, the change in the threshold voltage is small (see FIG. 6). Therefore,
The semiconductor device 100 is more resistant to electrical stress than the semiconductor device 700 and has a longer life.

FIG. 7 shows R / in the memory of the semiconductor device.
It is the figure which showed the graph showing the general relationship between the number of times of W and the threshold voltage of a semiconductor device. According to FIG. 7, as the number of R / W increases, the amount of electrons trapped in the gate insulating film 20 increases and the threshold voltage of the semiconductor device changes.

Therefore, also in the nonvolatile semiconductor memory device having the gate electrode 30 as the floating gate electrode, the semiconductor device 100 according to the present embodiment is the conventional semiconductor device 700.
Compared with, the change amount (ΔVge) of the electron trap is small and the change of the threshold voltage is small even if the R / W number is large. Also,
Even if the number of R / Ws is large, the semiconductor device 100 is different from the semiconductor device 700 in that the gate electrode 3 as the floating gate electrode
The charge can be held at 0 for a long period of time.

In the description of FIGS. 4 to 7, only electron traps have been described, but the same applies to hole traps.

[0051]

According to the semiconductor device of the present invention, the stress and the electric field are not concentrated on the edge of the semiconductor substrate or the amorphous silicon film, the number of electron traps is relatively small, and the gate breakdown voltage is relatively high.

According to the method of manufacturing a semiconductor device according to the present invention, stress and electric field are not concentrated on the edge of the semiconductor substrate or the amorphous silicon film, electron traps are relatively small, and gate breakdown voltage is relatively high. A semiconductor device can be manufactured.

[Brief description of drawings]

FIG. 1 is an enlarged cross-sectional view of a trench of a semiconductor device 100 having an STI and its periphery according to an embodiment of the present invention.

FIG. 2 is an enlarged cross-sectional view of an end portion of a semiconductor substrate and an end portion of a gate electrode in a semiconductor device before and after an oxidation process by RTO.

FIG. 3 is a diagram showing a graph showing a relationship between a radius of curvature of a boundary portion 15 and a boundary portion 35 and a variation amount (ΔVge) of an electron trap.

FIG. 4 is a graph showing a relationship between stress in a gate insulating film and electron traps.

FIG. 5 is a diagram showing a graph showing the relationship between the time for which a constant current is applied to the gate insulating film 20 and the amount of electron traps (ΔVge).

FIG. 6 is a threshold voltage (Vt) of a semiconductor device and a gate insulating film 2
The figure showing the graph showing the relation with the amount (ΔVge) of the electron trap at 0.

FIG. 7 is a graph showing a relationship between the R / W count in a memory of a semiconductor device and a threshold voltage of the semiconductor device.

FIG. 8 is an enlarged cross-sectional view of a conventional semiconductor device 700 having an STI during manufacturing.

[Explanation of symbols]

100,700 Semiconductor device 10 Semiconductor substrate 12 Substrate surface 14 Board side 15, 35 border 20 Gate insulating film 30 gate electrode 32 Opposing surface 34 Gate side 40 Silicon nitride film 50 Silicon oxide film 60 trench 70 Silicon oxide film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/792 (72) Inventor Koichi Matsuno 800 No. 1, Yamanoichishiki-cho, Yokkaichi-shi, Mie Toshiba Yokkaichi Co., Ltd. F term in the factory (reference) 5F032 AA36 AA44 AA45 AA69 BA01 CA17 DA04 DA33 DA53 DA74 5F083 GA19 GA21 GA24 GA27 JA33 NA01 PR13 PR21 5F101 BA23 BD35 BE07 BF03 BH16 BH30 5F140 BF44 BF34 BF44 BF04 BF14 BF14 BF14 BF14 BF14 BF14 BF14 BF14 BF14 BF14 BF14 BF14 BF14 BF14 BF14

Claims (6)

[Claims] 1. A semiconductor substrate having a substrate surface on which an element is formed, a gate electrode having a facing surface facing the substrate surface, and electrically insulated from the semiconductor substrate by a gate insulating film, A trench that is formed so as to reach the semiconductor substrate through the gate electrode and electrically separates an element region in which an element is formed and another region of the substrate surface from each other, A first boundary portion between the substrate side surface and the substrate surface forming a part of the side surface of the trench, and a gate side surface and a facing surface forming a part of the side surface of the trench of the gate electrode A semiconductor device characterized in that a second boundary portion between them has a curved shape having a radius of curvature of 30 Å or more. 2. A semiconductor substrate having a substrate surface on which an element is formed, a gate electrode having a facing surface facing the substrate surface and electrically insulated from the semiconductor substrate by a gate insulating film, A trench that is formed so as to reach the semiconductor substrate through the gate electrode and electrically separates an element region in which an element is formed and another region of the substrate surface from each other, A first boundary portion between the substrate side surface and the substrate surface forming a part of the side surface of the trench, and a gate side surface and a facing surface forming a part of the side surface of the trench of the gate electrode 3. The semiconductor device according to claim 1, wherein the second boundary portions between the two appear substantially coincident with each other when viewed from a direction perpendicular to the substrate surface. 3. The semiconductor device according to claim 2, wherein the oxide films formed on the side surface of the substrate and the side surface of the gate have substantially the same film thickness. 4. The semiconductor device according to claim 1, wherein the gate electrode is a floating gate electrode whose periphery is electrically insulated. 5. A step of forming a gate insulating film on a semiconductor substrate; a step of forming a gate electrode on the gate insulating film so as to be electrically insulated from the semiconductor substrate; Etching the gate electrode, the gate oxide film, and the semiconductor substrate to form a trench that electrically separates a device region to be formed from other regions; and a side surface of the trench of the semiconductor substrate. A side surface of the substrate forming a part of the gate electrode and a side surface of the gate forming a part of the side surface of the trench in the gate electrode in a hydrogen H ₂ and oxygen O ₂ atmosphere. Production method. 6. A step of forming a gate insulating film on a semiconductor substrate; a step of forming a gate electrode on the gate insulating film so as to be electrically insulated from the semiconductor substrate; Etching the gate electrode, the gate oxide film, and the semiconductor substrate to form a trench that electrically separates a device region to be formed from other regions; and a side surface of the trench of the semiconductor substrate. A side surface of the substrate forming a part of the gate electrode and a gate side surface of the gate electrode forming a part of the side surface of the trench in an ozone O ₃ atmosphere.