JPH0629550A - Manufacture of semiconductor nonvolatile storage - Google Patents

Abstract

PURPOSE:To prevent a phenomenon of weak writing from occurring by forming an impurity region of a conductivity type which is opposite to that of a semiconductor substrate on the semiconductor substrate of a region where an address gate electrode and a memory gate electrode overlap in first ion implantation process. CONSTITUTION:A vapor growth film 17 consisting of a silicon nitride film is etched without any etching mask. In this case, the etching speed of the vapor growth film 17 greatly differs between a plane part 17a and a side-wall part 17b and the etching speed of the side-wall part 17b is far than that of the plane part 17b by 10 times or more. Thus, the side-wall part 17b of the vapor growth film 17 is etched selectively and the slide of a side-wall opening 19 is formed. Then, an impurity whose conductivity type is N, for example arsenic, is introduced into a semiconductor substrate 11 via the side-wall opening 19, thus informing an impurity region 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor nonvolatile memory device capable of electrically rewriting information.

[0002]

2. Description of the Related Art As a semiconductor nonvolatile memory device capable of electrically rewriting information, for example, Japanese Laid-Open Patent Publication No. 2-1109.
MNOS (metal-silicon nitride film-
Silicon oxide film-semiconductor) type memory element and this MNO
A silicon oxide film is further formed on the silicon nitride film that is the second-layer memory gate insulating film of the S-type storage element, and has a barrier height sufficient to prevent injection of carriers from the memory gate electrode side. An MO having a three-layer memory gate insulating film is disclosed in, for example, Japanese Patent Application Laid-Open No. 3-41775.
A NOS (metal-silicon oxide film-silicon nitride film-silicon oxide film-semiconductor) type storage element is conventionally known.

When the memory transistors composed of these MNOS type storage elements and MONOS type storage elements are arranged in a matrix to form a memory array, in order to prevent malfunction caused by application of a high voltage at the time of rewriting information, a MOS is used. A memory cell structure having an address transistor for address selection composed of (metal-silicon oxide film-semiconductor) transistor is required.

FIG. 5 shows a sectional structure of a memory cell including the address transistor and the memory transistor.

As shown in the sectional view of FIG. 5, the memory cell is composed of two transistors, an address transistor 31 for address selection and a memory transistor 33 for storing information.

The memory cell further includes a source region 37 provided on the semiconductor substrate 11, a drain region 39, and an impurity layer 35 provided between the memory transistor 33 and the address transistor 31.

In the memory cell structure shown in FIG. 5,
When a high voltage (hereinafter referred to as Vpp) for rewriting information is applied to the drain region 39, the memory gate insulating film 23 of the memory transistor 33 near the drain region 39 is damaged.

As a result, there are problems that the number of times of rewriting of the semiconductor nonvolatile memory device is limited and that the memory gate insulating film 23 suffers a dielectric breakdown.

Therefore, in order to solve the above problems, a memory cell structure shown in FIG. 6 has been proposed.

In the memory cell shown in FIG. 6, a pair of address gate electrodes 15 are provided on a semiconductor substrate 11 with an address gate insulating film 13 interposed therebetween, and the two address gate electrodes 15 partially overlap each other. Gate insulating film 2
A memory gate electrode 27 is provided via

Further, a source / drain region 29 is provided on the semiconductor substrate 11 in a region where the memory gate electrode 27 and the address gate electrode 15 are aligned with each other.

In the memory cell structure shown in FIG. 6, when Vpp is applied to memory gate electrode 27, source / drain region 29 does not exist near memory gate electrode 27. Therefore, even if Vpp is applied,
The memory gate insulating film 23 is not damaged by electric field concentration.

However, the address gate electrode 15 and the memory gate electrode 27 need to be insulated and separated.

Therefore, a gap corresponding to the insulating separation film, that is, a gap corresponding to the film thickness of the address gate insulating film 13 always exists between the address gate electrode 15 and the memory gate electrode 27.

As a result, in the boundary region between the semiconductor substrate 11 under the address gate electrode 15 and the semiconductor substrate 11 under the memory gate electrode 27, there is a small region (not shown) where no channel is formed. become.

When it is desired not to change the stored information even if Vpp is applied to the memory gate electrode 27, that is, to prevent writing, for example, Vpp is applied to the address gate electrode 15 and the source / drain region 29 is also applied. V
pp and 0 V are applied to the semiconductor substrate 11, respectively.

By doing so, the potential difference with the channel region formed on the surface of the semiconductor substrate 11 under the memory gate electrode 27 is minimized, and writing is not performed.

However, the depletion layer existing in the boundary region between the semiconductor substrate 11 under the address gate electrode 15 and the semiconductor substrate 11 under the memory gate electrode 27 causes a slight voltage drop.

Therefore, a potential difference is generated between the memory gate electrode 27 and the channel region under the memory gate electrode 27, and extremely weak writing is performed.

As a result, there is a problem that the reliability of the semiconductor nonvolatile memory device is impaired.

In order to solve this problem, for example, a method of manufacturing a semiconductor nonvolatile memory device has been proposed in Japanese Patent Laid-Open No. 3-177074. The manufacturing method described in this publication will be described with reference to the sectional views of FIGS.

First, as shown in FIG. 7, a semiconductor substrate 11 having a P-type conductivity is provided with an address gate insulating film 13 interposed therebetween.
Two address gate electrodes 15 are formed. A high concentration of phosphorus is introduced into the address gate electrode 15.

Then, ion implantation is used to introduce phosphorus as an N-type impurity into the semiconductor substrate 11 in the aligned region of the address gate electrode 15 to form a first impurity introduction region of the opposite conductivity type to the semiconductor substrate 11. 41 is formed.

Next, as shown in FIG. 8, an oxidation process is performed to form an oxide film 45 on the surface of the semiconductor substrate 11 and the surface of the address gate electrode 15.

This oxide film 45 is formed on the address gate electrode 1
A silicon oxide film containing phosphorus is formed on the surface of No. 5, and a silicon oxide film is formed on the surface of the semiconductor substrate 11. Regarding the thickness of the oxide film 45, the silicon oxide film containing phosphorus on the surface of the address gate electrode 15 is several times thicker than the silicon oxide film on the surface of the semiconductor substrate 11.

After that, boron, which is an impurity having a conductivity type opposite to that of the first impurity introduction region 41, is introduced into the semiconductor substrate 11 by the ion implantation method.

As a result, the semiconductor substrate 11 in the region where the oxide film 45 formed on the side surface of the address gate electrode 15 is aligned.
A second impurity introduction region 41 is formed in the. Since boron is not introduced into the region below the oxide film 45 on the side surface of the address gate electrode 15, the first impurity introduction region 41 remains.

Next, as shown in FIG. 9, the semiconductor substrate 11
The upper oxide film 45 is removed using a hydrofluoric acid aqueous solution. As described above, the oxide film 45 on the surface of the address gate electrode 15 is formed.
Is thicker than the oxide film 45 on the semiconductor substrate 11. Therefore, even if the oxide film 45 on the semiconductor substrate 11 is removed using a hydrofluoric acid aqueous solution, the oxide film 45 on the surface of the address gate electrode 15 remains without being removed.

Next, as shown in FIG. 10, a memory gate insulating film 23 is formed. This memory gate insulating film 23
Is composed of a silicon oxide film, a silicon nitride film and a silicon oxide film, or a laminated film of a silicon oxide film and a silicon nitride film.

After that, a memory gate electrode material 25 made of a polycrystalline silicon film is formed.

Next, as shown in FIG. 11, the memory gate electrode material 25 and the memory gate insulating film 23 are etched to form the memory gate electrode 27 and the memory gate insulating film 23.
And pattern.

After that, arsenic is introduced into the semiconductor substrate 11 as an N-type impurity to form source / drain regions 29.

[0033]

In the method of manufacturing the semiconductor nonvolatile memory device described with reference to FIGS. 7 to 11, the semiconductor substrate 11 below the region where the address gate electrode 15 and the memory gate electrode 27 overlap each other. In this region, a first impurity introduction region 41 having a conductivity type opposite to that of the semiconductor substrate 11 is formed. Therefore, there is an effect that sufficient write blocking performance can be obtained.

However, in the method of manufacturing the semiconductor nonvolatile memory device shown in FIGS. 7 to 11, the first impurity introduction region 41 is formed in the semiconductor substrate 11 in the region where the address gate electrode 15 and the memory gate electrode 27 overlap. To do so, two ion implantation steps are required.

That is, the first impurity introduction region 4 formed in the semiconductor substrate 11 below the side wall of the address gate electrode 15.
A first ion implantation step (FIG. 7) for forming 1;
Second for forming the second impurity introduction region 43 by compensating for impurities other than the first impurity introduction region 41 formed in the semiconductor substrate 11 in the region where the address gate electrode 15 and the memory gate electrode 27 overlap each other. The ion implantation step (FIG. 8) and the ion implantation step of FIG.

The object of the present invention is to solve the above problems by
It is an object of the present invention to provide a method of manufacturing a semiconductor nonvolatile memory device capable of forming an impurity introduction region having a conductivity type opposite to that of the semiconductor substrate under the side wall of the address gate electrode in a single ion implantation step.

In order to achieve the above object, the method of manufacturing a semiconductor nonvolatile memory device of the present invention employs the following steps.

According to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, a pair of address gate electrodes are formed on a first conductivity type semiconductor substrate through an address gate insulating film, and the entire surface is subjected to chemical vapor deposition in a reduced pressure atmosphere. A step of forming a vapor phase growth film by a growth method, and a side wall opening is formed by selectively removing the vapor phase growth film on the side wall of the address gate electrode, and a second conductive film is formed in the side wall opening by an ion implantation method. Type impurity is introduced to form an impurity region, a memory gate insulating film and a memory gate electrode material are formed, a memory gate electrode is formed by photoetching, and a second conductivity type impurity is added to the semiconductor. Forming a source / drain region on the substrate.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor nonvolatile memory device according to the present invention will be described below with reference to the drawings. 1 to 4 are cross-sectional views showing a method of manufacturing a semiconductor nonvolatile memory device of the present invention in the order of steps.

First, as shown in FIG. 1, a semiconductor substrate 11 made of silicon having a conductivity type of P is heat-treated in an oxygen atmosphere to form a film having a thickness of 35 n made of a silicon oxide film.
An address gate insulating film 13 of m is formed.

After that, a film thickness 40 of a polycrystalline silicon film is formed by a chemical vapor deposition method using monosilane as a reaction gas.
An address gate electrode material 14 of 0 nm is formed.

Thereafter, this address gate electrode material 14
For example, oxygen and phosphine (PH
Heat treatment is performed in a mixed gas atmosphere with ₃ ) to introduce phosphorus, which is an N-type impurity, into the address gate electrode material 14 made of a polycrystalline silicon film.

After that, a photosensitive resin (not shown) is formed on the entire surface by a spin coating method, exposed and developed using a predetermined photomask to pattern the photosensitive resin, and the patterned photosensitive resin is applied. The address gate electrode 15 is formed by so-called photo-etching in which the address gate electrode material 14 is etched as an etching mask.

The etching of the address gate electrode material 14 made of this polycrystalline silicon film is performed by sulfur hexafluoride (S
An anisotropic ion etching method using F ₆ ) as an etching gas is used.

After that, a chemical vapor deposition method in a reduced pressure atmosphere,
For example, by the plasma chemical vapor deposition method, the vapor deposition film 1
As 7, a silicon nitride film having a film thickness of 400 nm is formed on the entire surface.

Vapor phase growth film 1 made of this silicon nitride film
A mixed gas of ammonia and dichlorosilane is used as a reaction gas when forming 7 by the chemical vapor deposition method.

Next, as shown in FIG. 2, the vapor phase growth film 17 made of a silicon nitride film is etched without an etching mask to form sidewall openings 19.

The vapor phase growth film 17 is etched by using a reactive ion etching device and a mixed gas of sulfur hexafluoride, helium and trifluoromethane as a reaction gas.

When the vapor phase growth film 17 is etched under the above-described etching conditions, the etching rates of the flat surface portion 17a and the side wall portion 17b are significantly different, and the side wall portion 17b is etched 10 times or more as compared with the flat surface portion 17a. The speed is high.

As a result, the side wall portion 17b of the vapor phase growth film 17 is formed.
Can be preferentially etched to form sidewall openings 19.

The phenomenon in which the etching rate of the vapor phase growth film 17 differs greatly between the flat surface portion 17a and the side wall portion 17b is as follows.
The reason is as follows.

That is, in the chemical vapor deposition method in a reduced pressure atmosphere, the active species involved in film deposition reach the semiconductor substrate 11 from a fixed direction. Therefore, the flat surface portion 17a and the side wall portion 17b have different film deposition mechanisms of the vapor phase growth film 17, and a phenomenon occurs in which the flat surface portion 17a and the side wall portion 17b have different etching rates.

The opening size of the side wall opening 19 can be controlled by the film thickness of the vapor phase growth film 17.

After that, arsenic, for example, as an N type conductivity type impurity is introduced into the semiconductor substrate 11 through the side wall opening 19 by the ion implantation method to form the impurity region 21.
The ion implantation amount of arsenic by the ion implantation method is set to about 10 ¹³ to 10 ¹⁴ atoms / cm ² .

After that, the vapor growth film 17 is removed. The vapor phase growth film 17 made of the silicon nitride film is removed using heated phosphoric acid.

Next, as shown in FIG. 3, a memory gate insulating film 23 composed of a silicon oxide film, a silicon nitride film and a silicon oxide film is formed.

The silicon oxide film which is the first layer memory gate insulating film 23 formed on the semiconductor substrate 11 is heat-treated at a temperature of 900 ° C. in an oxidizing atmosphere to have a film thickness of 2.1 nm on the semiconductor substrate 11. A first layer memory gate insulating film 23 made of a silicon oxide film is formed.

The silicon nitride film, which is the memory gate insulating film 23 of the second layer, is formed by a chemical vapor deposition method using ammonia and dichlorosilane as a reaction gas, and the second layer memory is a silicon nitride film having a thickness of 14 nm. Gate insulating film 23
To form.

The silicon oxide film, which is the memory gate insulating film 23 of the third layer, has a film thickness of 5 nm by heat-treating the silicon nitride film, which is the memory gate insulating film of the second layer, at a temperature of 1000 ° C. in a steam oxidizing atmosphere. Forming a third layer of memory gate insulating film 23 of the silicon oxide film.

After that, a memory gate electrode material 25 made of a polycrystalline silicon film having a film thickness of 400 nm is formed by a chemical vapor deposition method using monosilane as a reaction gas.

Next, as shown in FIG. 4, a photosensitive resin (not shown) is formed on the entire surface of the memory gate electrode material 25 by a spin coating method so that the photosensitive resin may straddle the address gate electrode 15. Then, the memory gate electrode material 25 is etched by using the patterned photosensitive resin as an etching mask to form the memory gate electrode 27.

The memory gate electrode 27 is etched by anisotropic etching using sulfur hexafluoride as an etching gas, and the memory gate insulating film 23 is also etched in the same pattern shape as the memory gate electrode 27.

Then, on the semiconductor substrate 11 in the region where the address gate electrode 15 and the memory gate electrode 27 are aligned,
As the N-type impurity, for example, arsenic is introduced by the ion implantation method to form the source / drain region 29.

The ion implantation amount for forming the source / drain region 29 is about 2 × 10 ¹⁵ / cm ² .

After that, although not shown, an interlayer insulating film made of a silicon oxide film to which phosphorus and boron are added is formed by a chemical vapor deposition method, and a connection hole is formed in this interlayer insulating film by a photoetching technique. After that, aluminum to which silicon is added is formed by a sputtering method, and wiring is formed by a photoetching technique, so that a semiconductor nonvolatile memory device is formed.

In the above description, the memory gate insulating film 23 is a memory gate insulating film having three layers of a silicon oxide film, a silicon nitride film and a silicon oxide film. A silicon oxide film is used as the first layer memory gate insulating film, and a silicon nitride film is used as the second layer memory gate insulating film to form a memory gate insulating film having a two-layer structure, and the memory gate is formed on the silicon nitride film. The electrode 27 may be formed.

Further, in the above description, the silicon nitride film is used as the vapor phase growth film 17, but a silicon oxide film formed by the vapor phase growth method in a reduced pressure atmosphere can also be applied. Even in the silicon oxide film formed by the chemical vapor deposition method in the reduced pressure atmosphere, the etching rate of the side wall portion is 10 times or more higher than that of the flat surface portion.

Further, as the etching process for etching the vapor phase growth film 17 to form the side wall opening 19, the dry etching using the reactive ion etching apparatus has been described, but the vapor phase growth film 17 is also etched by wet etching. It is possible to form the side wall opening 19.

Wet etching of the vapor phase growth film 17 made of, for example, a silicon nitride film is performed using phosphoric acid,
Wet etching of the vapor growth film 17 made of a silicon oxide film can be performed using a hydrofluoric acid-based etching solution, and the vapor growth film 17 can be etched to form the sidewall opening 19.

The etching of the vapor phase growth film 17 is preferably performed by wet etching so that the semiconductor substrate 11 is not damaged.

Although an example of forming the N-channel type has been described, when the P-channel type is used, the semiconductor substrate 11 is used.
As a semiconductor substrate made of silicon having an N conductivity type, boron is introduced into the polycrystalline silicon film by heat treatment in a mixed atmosphere of diborane, oxygen and nitrogen.

[0072]

As is apparent from the above description, according to the method for manufacturing a semiconductor nonvolatile memory device of the present invention, the semiconductor in the region where the address gate electrode and the memory gate electrode overlap in one ion implantation step. It is possible to form an impurity region having a conductivity type opposite to that of the semiconductor substrate on the substrate.

As a result, it is possible to prevent the phenomenon that weak writing is performed, and the reliability of the semiconductor nonvolatile memory device is improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor nonvolatile memory device of the present invention.

FIG. 2 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device of the present invention.

FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device of the present invention.

FIG. 4 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device of the present invention.

FIG. 5 is a cross-sectional view showing a semiconductor nonvolatile memory device in a conventional example.

FIG. 6 is a cross-sectional view showing a semiconductor nonvolatile memory device in a conventional example.

FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the conventional example.

FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the conventional example.

FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the conventional example.

FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the conventional example.

FIG. 11 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory device in the conventional example.

[Explanation of symbols]

 13 Address Gate Insulating Film 15 Address Gate Electrode 17 Vapor Growth Film 19 Sidewall Opening 21 Impurity Region 23 Memory Gate Insulating Film 27 Memory Gate Electrode 29 Source / Drain Region

Claims (1)

[Claims] 1. A pair of address gate electrodes are formed on a first conductive type semiconductor substrate with an address gate insulating film interposed therebetween.
A step of forming a vapor deposition film on the entire surface by a chemical vapor deposition method in a reduced pressure atmosphere, and a vapor deposition film on the side wall of the address gate electrode is selectively removed to form a side wall opening. Introducing a second conductivity type impurity into the semiconductor substrate by an ion implantation method to form an impurity region; forming a memory gate insulating film and a memory gate electrode material;
The memory gate electrode is formed by photoetching, and the second
A step of introducing a conductive type impurity into a semiconductor substrate to form a source / drain region, a method for manufacturing a semiconductor nonvolatile memory device.