JP2011142417A - A/d converter and a/d conversion method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an A/D converter, which can perform A/D conversion faster than an existing A/D converter with a circuit configuration simpler than that of the existing A/D converter, and in which a circuit scale can be reduced. <P>SOLUTION: The A/D converter includes: a comparing part 102 comprising comparators 114, 124, 134 and 144 for respectively comparing analog input voltage Vin with reference potentials Vref1 to Vref4 to derive respective bit outputs D1 to D4; a base potential generating part 101 for generating a base potential to be a base of each of the reference potentials Vref1 to Vref4; and a feedback part 103 for performing the feedback of each output of the comparators to a reference potential side of a comparator corresponding to a lower order bit, in order to make the reference potentials Vref1 to Vref4 of the comparators 114, 124 and 134 corresponding to a lower-order bit variable in accordance with each output state of the comparators 114, 124 and 134. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an A / D converter and an A / D conversion method.

  An A / D converter defines a potential range to be converted (the description is a potential range where the minimum voltage is 0 V), and the range is divided into 2 n power ranges and input. The potential of the analog voltage is read as a digital value. There are various types of existing A / D conversion methods, but each has advantages and disadvantages, and the method is selected according to the intended use.

  One of them is a parallel type A / D converter, and its basic principle is that the highest voltage is generated using 2 n resistors in order to decompose the conversion potential range into 2 n resistors. The threshold value is generated by dividing the voltage to generate 2 n regions. For this reason, 2 n −1 comparators are required, and the circuit scale becomes huge by the high speed that can be processed in parallel (see Patent Document 1).

  Another example is a successive approximation A / D converter. The basic principle of the A / D converter is that a reference potential is generated by including a D / A converter having the same resolution. The potential range is decomposed into n-th power. For this reason, only one comparator is required. However, in order to bring the output of the D / A converter close to the analog input voltage, the input voltage is fixed by the sample hold circuit and the reference generated by the D / A converter is generated. It is necessary to switch the potential several times. Therefore, n-bit A / D conversion requires a circular operation for n clocks, and it takes time until the digital output is determined (see Patent Document 2).

JP 2003-101411 A Japanese Patent Laid-Open No. 7-086946

  As described above, the parallel A / D converter has a high speed conversion process and a simple operation principle. However, for n-bit A / D conversion, n-1 comparators and 2 An encoder circuit that converts the output to an n-bit binary number according to the n-th power comparator output is required, and there is a problem that it is difficult to reduce the circuit scale.

  Further, since the successive approximation A / D converter generates a reference potential by the D / A converter, only one comparator is required as compared with the parallel type, but the circuit is small. The / D conversion requires a circular operation for n clocks, and there is a problem that the conversion takes time.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an A / D converter and an A / D conversion method that have a simpler circuit configuration than an existing A / D converter, can perform A / D conversion at high speed, and can reduce the circuit scale. That is.

The A / D converter according to the present invention is:
n-bit (n is an integer of 2 or more) A / D converter,
A comparator comprising n comparators for comparing each of the analog input voltage and n reference potentials to derive each bit output;
A basic potential generator for generating n basic potentials that are the basis of each of the n reference potentials;
In order to vary the reference potential of the comparator corresponding to the lower bit according to each output state of the comparator, each output of the comparator is shifted to the reference potential side of the comparator corresponding to the lower bit. A feedback section for feedback,
It is characterized by including.

The A / D conversion method according to the present invention includes:
An A / D conversion method for converting an analog input voltage into an n-bit (n is an integer of 2 or more) digital signal,
Comparing the analog input voltage and n reference potentials with n comparators, respectively, to derive each bit output;
Generating n basic potentials that are the basis of each of the n reference potentials;
In order to vary the reference potential of the comparator corresponding to the lower bit according to each output state of the comparator, each output of the comparator is shifted to the reference potential side of the comparator corresponding to the lower bit. Feedback step,
It is characterized by including.

  According to the present invention, the number of comparators can be greatly reduced as compared with a basic parallel A / D converter, and an encoder circuit is not required, so that the circuit scale can be reduced. In addition, unlike the successive approximation type A / D converter, since no revolving operation is required, there is an effect that high-speed A / D conversion is possible. Furthermore, since the circuit can be configured only by the comparator and the resistor, there is an effect that the circuit can be created relatively easily.

It is a circuit diagram of one embodiment of the present invention. FIG. 2 is a timing diagram illustrating an operation of the circuit of FIG. 1. It is a figure which shows the general circuit example of this invention. It is a circuit diagram of other embodiments of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention. For example, a circuit diagram of an A / D converter having a resolution of 4 bits is shown.

  This circuit shown in FIG. 1 is a circuit that decomposes the potential range from 0 V to Vt into the fourth power range with the maximum resolvable voltage as Vt, and digitally outputs the analog input voltage Vin in binary form. is there.

  The circuit shown in FIG. 1 can basically be divided into three blocks. That is, in order to configure an A / D converter having a 4-bit resolution, the basic potential generation unit 101, the comparison unit 102, and the feedback unit 103 can be divided.

  In the figure, blocks 1 to 4 are circuits corresponding to respective bits from MSB (Most Significant Bit) to LSB (Least Significant Bit) which are digital signals D1 to D4 to be output, respectively. It shall be shown.

  The basic potential generation unit 101 is for generating potentials that are the basis of the reference potentials Vref1 to Vref4 of the comparators 114, 124, 134, and 144 that constitute the comparison unit 102.

  The comparator 102 is configured by connecting comparators 114, 124, 134, and 144 that compare the potential of the analog input voltage Vin100 with these reference voltages Vref1 to Vref4, respectively, in parallel.

  The feedback unit 103 is for varying the reference potentials of all the comparators corresponding to the lower bits on the LSB side, as seen from each bit, according to the output states of the comparators 114, 124, 134, and 144.

  The basic potential generator 101 divides the voltage Vt by the balance of the pair of voltage dividing resistors 112a and 112b, 122a and 122b, 132a and 132b, 142a and 142b, respectively, when the maximum convertible voltage is Vt. Thus, a potential of Vt / 2 is generated. In this case, the resistance values of all the voltage dividing resistors are equally R. The potentials generated by each of the pair of voltage dividing resistors are input to the inverting inputs of the corresponding comparators 114, 124, 134, and 144 through the current adjustment resistors 113, 123, 133, and 143, respectively.

なお、上式において、Ｒi は後述する式（２）となる。また、図１の例（４ビット）では、上記式（１）のｍは３，４であり、Ｒa1＝Ｒa2＝０となる。 Here, the resistance values Ra1, Ra2, Ra3, and Ra4 of the current adjustment resistors 113, 123, 133, and 143 are generally expressed as Ram (m = 1, 2, 3, 4), and the following formula (1 ) Shall be set to a value equivalent to.

In the above equation, Ri is the equation (2) described later. In the example of FIG. 1 (4 bits), m in the above equation (1) is 3 and 4, and Ra1 = Ra2 = 0.

  In the comparison unit 102, taking the block 4 corresponding to D4 which is LSB (least significant bit) as an example, the comparator 144 compares the analog input voltage Vin100 and the reference potential Vref4. The reference potential Vref4 is a potential generated by the current 145a flowing from the basic potential generating unit 101 and the current 145b flowing from the feedback unit 103. The comparator 144 outputs Vt when the analog input voltage Vin100 is higher than the reference potential Vref4, and outputs the ground voltage 0V when the analog input voltage Vin100 is lower.

  Taking block 3 corresponding to D3 as the second bit from the lower order as an example, the comparator 134 compares the analog input voltage Vin100 and the reference potential Vref3. The reference potential Vref3 is a potential generated by the current flowing from the basic potential generating unit 101 and the current flowing from the feedback unit 103, as described in the block 4 of the LSB. The comparator 134 outputs Vt when the analog input voltage Vin100 is higher than the reference potential Vref3, and outputs the ground voltage 0V when the analog input voltage Vin100 is lower.

  Taking the block 2 corresponding to D2 as the third bit from the lower order as an example, the comparator 124 compares the analog input voltage Vin100 with the reference potential Vref2. Similarly, the reference potential Vref2 is a potential generated by the current flowing from the basic potential generating unit 101 and the current flowing from the feedback unit 103. The comparator 124 outputs Vt when the analog input voltage Vin100 is larger than the reference potential Vref2, and outputs the ground voltage 0V when it is low.

  Further, taking block 1 corresponding to D1 as the MSB (most significant bit) as an example, the comparator 114 compares the analog input voltage Vin100 and the reference potential Vref1. Similarly, the reference potential Vref1 is a potential generated by the current flowing from the basic potential generating unit 101 and the current flowing from the feedback unit 103. The comparator 114 outputs Vt when the analog input voltage Vin100 is higher than the reference potential Vref1, and outputs the ground voltage 0V when the analog input voltage Vin100 is lower.

  In the feedback unit 103, taking LSB as an example, outputs (comparator outputs) D1, D2 and D3 of all higher bits are connected to resistors (R1) 147a, resistors (R2) 147b, and resistors (R3) 147c. Each of them is fed back by being connected to the inverting input of the comparator 144 of the block 4 corresponding to its own bit D4.

  In block 3 of the next bit D3, all higher-order bit outputs (comparator outputs) D1 and D2 are equivalent to their own bit D3 via resistors (R1) 137a and resistors (R2) 137b, respectively. 3 is connected to the inverting input of the comparator 134 for feedback.

  In block 2 of the next bit D2, the higher-order bit output (comparator output) D1 is connected to the inverting input of the comparator 124 of block 2 corresponding to its own bit D2 via the resistor (R1) 127a. And give feedback. In block 1 of bit D1, which is the MSB, there is no bit higher than this bit, so there is no feedback for the inverting input of the comparator 114 of block 1 corresponding to its own bit D1.

  That is, in this feedback unit 103, the output of the m-th bit (m = 1, 2, 3, 4) comparator is connected to the inverting input of all the lower-order comparators through the feedback resistor Rm. is there.

Here, the resistance value Rm of each of the feedback resistors must be set to a value according to the following equation (2).
Rm = 2 ^m-2 R (m = 1, 2, 3, 4) (2)

  In the circuit configuration described above, FIG. 2 shows the signal behavior of each part when the analog input voltage Vin is supplied when the resistance value satisfying the expressions (1) and (2) is selected. 2, description will be made with reference to block 4 of the fourth bit D4 that is LSB.

  The reference potential Vref is generated based on the voltage Vt / 2 by the basic potential generation unit 101, but current feedback from the feedback unit 103 occurs depending on each comparison output state of the comparison unit 102, and the potential is Vt / 2 will fluctuate around. For example, the reference potential Vref4 of the comparator 144 of the block 4 that is LSB is connected to the three comparison outputs of the comparators 134, 124, and 114 of the upper bits, and each comparator has two potentials of Vt or 0V. Since the current is output, the current 145b flowing from the feedback unit 103 varies, and Vref4 varies to the cube of 2 (eight) potentials depending on the state of the upper bit.

  Since the same principle works for the other blocks (blocks 3, 2, 1), the number of reference potentials that can be set in the case of a 4-bit circuit is 8 + 4 + 2 + 1 = 15. That is, if the threshold value of the circuit is 15, and the threshold value is 15, the conversion potential range can be divided into 16, and an A / D conversion circuit having a 4-bit resolution can be realized.

  These reference potentials Vref1 to Vref4 are set by the resistance values of the feedback resistor Rm and the current adjustment resistor Ram. In order to obtain a uniform division interval for A / D conversion, these current adjustment resistors and feedbacks are used. Each resistance value Ram and Rm of the resistor needs to be a value represented by the above-described equations (1) and (2), respectively. In this case, m = 3 to n in Equation (1) and m = 1 to n in Equation (2).

  In the above embodiment, the A / D converter having a resolution of 4 bits has been described in order to simplify the description. However, generally, as shown in FIG. 3, n bits (n is 2 or more). It is clear that an A / D converter having a resolution of (integer) can be constructed.

  Also, in the circuits of FIGS. 1 and 3 which are the previous embodiments, the grounded portion is replaced with the lowest convertible voltage Vb as shown in FIG. 4, and each output of the comparator is changed to Vt and Vb. By using the binary output, it is possible to A / D convert the arbitrarily specified voltage range (Vb to Vt) with a desired resolution.

  However, in this case, each output of the comparator becomes a binary signal of Vt and Vb, and there is a problem in using it as a digital output of “1” or “0”. Therefore, in order to use as a digital signal of “1” or “0”, it is apparent that a level shift that converts to a desired voltage by the level shift circuit 104 using differential amplification or the like is necessary.

  Note that the A / D conversion circuit of the present invention can monitor only the voltage range necessary for the resolution when the voltage range to be converted is already known, for example, when the remaining battery level is monitored. Therefore, the resolution can be effectively used.

  The A / D conversion circuit according to the present invention can be used for all electronic devices that require digital signal processing, such as performing digital processing by taking analog elements into the digital circuit. For example, video devices such as cameras, telephones, etc. It can be widely applied to audio equipment such as communication equipment that communicates using analog modulation.

100 Analog input Vin
DESCRIPTION OF SYMBOLS 101 Basic voltage generation part 102 Comparison part 103 Feedback part 104 Level shift circuit 112,122,132,142 Voltage dividing resistance 113,123,133,143 for basic potential generation Current adjustment resistance 114,124,134,144 Comparator 127 , 137, 147 Feedback resistance D1-D4 Digital output

Claims (5)

n-bit (n is an integer of 2 or more) A / D converter,
A comparator comprising n comparators for comparing each of the analog input voltage and n reference potentials to derive each bit output;
A basic potential generator for generating n basic potentials that are the basis of each of the n reference potentials;
In order to vary the reference potential of the comparator corresponding to the lower bit according to each output state of the comparator, each output of the comparator is shifted to the reference potential side of the comparator corresponding to the lower bit. A feedback section for feedback,
A / D converter characterized by including. The feedback unit includes a resistor that feeds back each output of the comparator to a reference potential side of a comparator corresponding to a lower-order bit, and the output of the m-th comparator passes through a feedback resistor Rm. It is connected to the reference potential side of the lower bit comparator, and each resistance value Rm of the resistor is
Rm = 2 ^m-2 R (m = integer from 1 to n)
The A / D converter according to claim 1, wherein the A / D converter is set as follows. The basic potential generator includes a current adjustment resistor for supplying each of the n basic potentials to a reference potential side of the comparator, and a resistance value Ram of the current adjustment resistor is:

(M is an integer of 3 to n, and Ra1 = Ra2 = 0)
The A / D converter according to claim 1, wherein the A / D converter is set as follows.   4. The A / D converter according to claim 1, further comprising a level shift circuit that performs a level shift of each output of the comparator. An A / D conversion method for converting an analog input voltage into an n-bit (n is an integer of 2 or more) digital signal,
Comparing the analog input voltage and n reference potentials with n comparators, respectively, to derive each bit output;
A basic potential generating step for generating n basic potentials to be the basis of each of the n reference potentials;
In order to vary the reference potential of the comparator corresponding to the lower bit according to each output state of the comparator, each output of the comparator is shifted to the reference potential side of the comparator corresponding to the lower bit. A feedback step for feedback,
A / D conversion method characterized by including.

Images