JP2000031826A - A/d conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform which precision conversion by means of a continuous conversion system by adding/subtracting k voltage having prescribed value of input analog voltage to/from reference voltage given to a binarizing circuit on the k-th stage in accordance with the output of the binarizing circuit of the k-th stage and giving it as reference voltage to the binarizing circuit on the (k+1)-th stage. SOLUTION: S1,...SN-1 are selectors and E2,...En-1 are exclusive OR inverted output gates. Voltage obtd. by adding/subtracting the central value (1/2)k of values which can be input analog voltages to/from applied voltage to an inverted input terminal (-) of a comparator Ck (k is a positive integer which is 1<=k<=N-1) in accordance with the output of the comparator Ck is produced by resistance partial pressure of resistance Rk1 and Rk2 and is applied to the inverted input terminal (-) of a comparator Ck+1. Input voltage is compared with MSB weight, comparison voltage is changed in accordance with the preceding comparison result, comparison operations are successively performed and input terminal analog voltage is subjected to A/D conversion with N bits and is outputted to output terminals OUTn,..., OUT1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion circuit for converting an analog signal into a digital signal in a cascade connection system.

[0002]

2. Description of the Related Art As a method of converting an analog signal into a digital signal, there is a method called a cascade conversion method. In the cascade conversion method, when converting into an N-bit digital signal, conversion is performed by dividing one bit at a time into N stages.
In this point, the conversion method is the same as the conversion method called the sequential conversion method. However, in the sequential conversion method, the conversion is performed in synchronization with the clock, whereas the cascade conversion method does not require a clock,
This realizes a higher-speed conversion operation.

FIG. 6 shows an example of a conventional configuration of an A / D conversion circuit when N = 3 for converting an analog signal into a digital signal by the cascade conversion method. Comparator C1, C2, and, C3-inverting input terminal of the (-) is connected to the terminal T of the reference voltage V _R is input. In addition, the reference voltage V _R is,
The analog voltage input to the input terminal I is set to the center value of possible values.

The output voltage of each comparator is configured so that the high level is the reference voltage V _R and the low level is 0.

[0005] For the comparator C1 has a non-inverting input terminal (+) is connected to the input terminal I, also, the output side is connected to the output terminal O _3. The subtraction circuit D1
It is connected so that the input voltage to the input terminal I and the output voltage of the comparator C1 are input, and outputs a voltage obtained by subtracting the output voltage of the comparator C1 from the input voltage to the input terminal I. The output side of the subtraction circuit D1 is connected to the input side of the amplification circuit A1 having a double amplification factor.

As for the comparator C2, the non-inverting input terminal (+) is connected to the output side of the amplifier circuit A1.
Further, the output side is connected to the output terminal O _2. The subtraction circuit D2 is connected to the output voltage of the amplification circuit A1 and the comparator C2.
And outputs a voltage obtained by subtracting the output voltage of the comparator C2 from the output voltage of the amplifier circuit A1. The output side of the subtraction circuit D2 is connected to the input side of the amplification circuit A2 having a double amplification factor.

The comparator C3 has a non-inverting input terminal (+) connected to the output side of the amplifier circuit A2,
Also, its output is connected to the output terminal O _1.

With the above configuration, the analog voltage input to the input terminal I is first compared with the center value of the possible values of the input analog voltage, that is, the MSB weight. Next, if the input analog voltage is greater than the MSB weight,
When the input analog voltage is smaller than the MSB weight, the value obtained by doubling the input analog voltage is greater than the MSB weight. On the other hand, when the input analog voltage is smaller than the MSB weight, the value obtained by doubling the input analog voltage itself is:
Each is compared with the MSB weight. This means that if the input analog voltage is greater than the MSB weight, the input analog voltage is compared to (MSB weight) + (2nd MSB weight), while if the input analog voltage is less than the MSB weight, This is equivalent to comparing the voltage with the weight of the 2nd MSB.

In this way, from the value compared with the MSB weight, M is calculated according to the magnitude relationship with the MSB weight.
The process of subtracting one of the SB weight or 0 and subtracting the result of doubling the result is compared with the MSB weight is repeated. In the example shown in FIG. The converted analog voltage is converted into a 3-bit digital voltage and output terminals O ₃ , O ₂ , O ₁ (output terminal O ₃
Are output from the MSB and the output terminal O ₁ is output from the LSB.

[0010]

However, in the conventional A / D conversion circuit using the cascade conversion method, the subtraction result is two times smaller.
Since the process of multiplying and subtracting based on the calculation result and doubling is repeated, the error at the time of the subtraction is amplified and accumulated. An accurate multi-bit A / D conversion circuit could not be realized.

FIG. 7 shows the transition of the LSB output of the conventional 4-bit A / D conversion circuit with respect to the input analog voltage which increases with a constant slope. From the figure, it can be seen that the LSB does not change in a uniform width, and the accuracy of A / D conversion is low. Even in the case of 4-bit A / D conversion, it is impossible to realize a multi-bit A / D converter with the conventional configuration because of such a state.

The voltages input to the inverting input terminals (-) of the comparators C2 and C3 are respectively applied to the comparators C2 and C3.
1/2 of the voltage input to the inverting input terminal (-) of 1
If a circuit of / 4 is provided, an amplifier circuit becomes unnecessary. However, if the number of bits is increased, many types of voltages are required (the same number of voltages as the number of bits are required). The influence of the error at the time of the subtraction becomes larger than that.

It is an object of the present invention to provide a highly accurate multi-bit A / D conversion circuit using a cascade conversion method.

[0014]

In order to achieve the above object, according to the present invention, in an A / D conversion circuit for converting an analog signal into a digital signal by a cascade connection method, an input analog voltage is compared with a reference voltage. An N-stage (N is a positive integer) binarization circuit for performing a binary output according to the magnitude relation between them, and a central value of a value that the input analog voltage can take to a first-stage binarization circuit. A circuit for providing the reference voltage, k
With respect to the reference voltage supplied to the binarization circuit at the stage (k is a positive integer satisfying 1 ≦ k ≦ N−1), (１ ／) ^k of the central value of the possible value of the input analog voltage Voltage of k
A circuit that generates a voltage added or subtracted in accordance with the binary output of the binarization circuit of the stage by resistance division and supplies the reference voltage to the binarization circuit of the (k + 1) th stage. .

According to the above configuration, the subtraction circuit and the amplification circuit become unnecessary, so that the cause of the error can be eliminated.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an N-bit A / D conversion circuit according to a cascade conversion system according to an embodiment of the present invention. Each symbol will be described. C ₁ ,
C ₂ ,..., C _N have _two input terminals, a non-inverting input terminal (+) and an inverting input terminal (−), and the non-inverting input terminal (+)
If the voltage applied to the inverting input terminal (-) is higher than the voltage applied to the inverting input terminal (-), a high-level voltage is output, while the voltage applied to the inverting input terminal (-) is the non-inverting input. If the voltage is higher than the voltage applied to the terminal (+), the comparator outputs a low-level voltage. FIG.
Unlike the case of the above, the high level is the power supply voltage level.

S ₁ , S ₂ ,..., S _N-1 are two input terminals of a first input terminal I ₁ and a second input terminal I ₂ and one output terminal O.
And a switching terminal K. When the input to the switching terminal K is at a high level, the voltage applied to the first input terminal I ₁ is output. On the other hand, when the input to the switching terminal K is at a low level, the second voltage is output. a selector for outputting a voltage applied to the input terminal I _2, for example, as shown in FIG. 2, the MOS transistor Q1 and the MOS type P-channel N-channel first input terminal I ₁ are connected in parallel N is connected in parallel with the second input terminal I ₂ via the transistor Q2.
Channel MOS transistor Q3 and P channel M
The gates of the N-channel MOS transistor Q1 and the P-channel MOS transistor Q1 are connected to the output terminal O via the OS transistor Q4, respectively.
4 is connected to the switching terminal K, and the gate of the P-channel MOS transistor Q2 and the gate of the N-channel MOS transistor Q3 are connected to the output side of the inverting gate INV whose input side is connected to the switching terminal K. It has a connected configuration.

E ₂ , E ₃ ,..., E _{N -1} are such that if the high level or the low level is aligned with the two inputs, the output is the high level, while the high level or the low level is aligned with the two inputs. For example, it is an exclusive OR inverted output gate whose output becomes low level. B ₁ , B ₂ , ..., B _N-1
Is a buffer composed of an operational amplifier.
R _{(1) 1} , R _{(1) 2} , R _{(2) 1} , R _{(2) 2} , ..., R _{(N-1) 1} , R
_{(N-1) 2} is a resistor. The relationship between the resistance values is represented by R _{(1) 1} = R _{(1) 2} , R _{(2) 1} =
R _{(2) 2} , ..., R _{(N-1) 1} = R _{(N-1) 2} .

The connection relationship will be described below. The non-inverting input terminals (+) of the comparators C ₁ , C ₂ ,..., C _N are commonly connected to an input terminal IN to which an analog voltage is input, and the output sides are output terminals OUT _N , OUT, respectively.
_N-1, ..., are connected to the OUT _1.

The inverting input terminal of the comparator C ₁ (-) is the central value of the voltage that can be taken analog voltage input to the input terminal IN (hereinafter, referred to as "central value of the input analog voltage") and a central potential point M It is connected to the.

[0021] With respect to the selector S _1, the input maximum value of the analog voltage can assume values (hereinafter, referred to as "input analog maximum value of the voltage") and a maximum potential point H to the first input terminal I
₁ is connected, and the minimum value that the input analog voltage can take (hereinafter referred to as "minimum value of the input analog voltage")
Second input and terminal I ₂ is connected, switching terminal K is connected to the output side of the comparator C ₁ to minimize potential point L to be.

The maximum potential point H, the minimum potential point L, and
The center potential point M, specifically, as shown in FIG. 3, the resistor R ₁ from the power supply voltage V _DD side, R _2, R _3, R ₄ (where the resistance value of the resistor R ₂ = the resistance R ₃ of the order of the resistance value) with respect to the supply voltage V resistor R ₁ connected in series between the _DD and the ground potential point GND, R _2, R _3, R _4, resistor R _1, resistor R ₂ a connection point between the B _H whose input side is connected to
As the output-side potential point H, the resistor R _3, the resistor R ₄ potential point on the output side of the buffer B _L whose input side is connected to a connection point between the L, the resistance R _2, a connection point between the resistor R ₃ The output side of the buffer B _M to which the input side is connected is set as the center potential point M, and the respective resistance values are adjusted under the condition that the resistance value of the resistor R ₂ is equal to the resistance value of the resistor R _3. The range of the analog voltage that can be A / D converted is variable.

Of course, the maximum potential point H can be set to the power supply voltage V _DD with the resistance value of the resistor R ₁ = 0, or the minimum potential point L can be set to the ground with the resistance value of the resistor R ₄ = 0. .

For the selector S _m (m is a positive integer satisfying 2 ≦ m ≦ N−1), the first input terminal I ₁ is connected to the selector S _m−1
, The second input terminal I ₂ is connected to the inverting input terminal (−) of the comparator C _m−1 , and the switching terminal K is connected to the exclusive OR inverted gate E _m. Is connected to the output side.

The output voltage of the comparator C _m-1 of the output voltage and the comparator C _m is input to the exclusive OR inverted output gate E _m. Resistance _{R (m) 1, R (} m) 2 is the inverting input terminal of the comparator C _m - are connected in series between the side and the output terminal O of the selector S _m (). Resistance R _{(m) 1} , R
_(m) input of buffer B _m to a connection point ₂ are connected to each other. Inverting input terminal of the comparator C _{m + 1} on the output side of the buffer B _m (-) is connected.

With the above configuration, the input analog voltage is
First, the comparator C _1, the center value of the possible values input analog voltage, that is, compared to the weight of the MSB. The result of this comparison, if the input analog voltage is greater than the weight of the MSB, the output voltage of the comparator C ₁ is at a high level, the output of the selector S ₁ is the maximum value of the input analog voltage, resistance R _{(1) The} voltage of (中心) ¹ of the central value of the input analog voltage is added to the voltage applied to the inverting input terminal (−) of the comparator C ₁ by the voltage division of the resistor ₁ and the resistor R _{(1) 2.} Voltage, ie, (M
SB weight) + (2nd MSB weight) is created,
On the other hand, if the input analog voltage is less than the weight of the MSB, the output voltage of the comparator C ₁ is at the low level, the output of the selector S ₁ is the minimum value of the input analog voltage, resistance R _{(1) 1} and the resistor Due to the resistance voltage division with R _{(1) 2} , the voltage applied to the inverting input terminal (−) of the comparator C ₁ is (１ ／) of the center value of the input analog voltage.
A voltage from which the voltage of ¹ is subtracted, that is, a weight of _2nd MSB is created and applied to the inverting input terminal (-) of the comparator C2.

When the input analog voltage is greater than the weight of the MSB, the comparator C ₂ compares the input analog voltage with (weight of MSB) + (weight of _2nd MSB). is greater than the direction of the voltage (weight MSB) + (weight of 2NdMSB), the output voltage of the comparator C ₂ is at a high level, a high level is aligned to the input of the exclusive OR-inverted output gate E ₂ since, the output becomes a high level, the output of the selector S ₁ output from the selector S ₂ is input to the first input terminal I _1, that is, in this case, since the maximum value of the input analog voltage, resistance R the resistor divider _{(2) 1} and the resistance R _{(2) 2,} the inverting input terminal of the comparator C ₂ (-) to the input analog voltage to a voltage applied to the central value (1/2) ² Voltage is added Voltage, ie, (M
SB weight) + (2nd MSB weight) + (3rdMS
B weight), while the input voltage is (MS
Is smaller than the weight of B) + (weight of 2NdMSB), the output voltage of the comparator C ₂ is at a low level, since the input of the exclusive OR-inverted output gate E ₂ not aligned is high level or low level , Its output becomes low level, and the output of the selector S ₂ becomes the second input terminal I ₂
Is input to the inverting input terminal of the comparator C ₁ (-)
Applied voltage, i.e., because the center value of the input analog voltage into, by resistance voltage division between the resistor R _{(2) 1} and a resistor R _{(2) 2,} the inverting input terminal of the comparator C ₂ - applied () (1/1 / the center value of the input analog voltage)
2) ^{voltage 2} of the voltage is subtracted, i.e., (the weight of the MSB) + (weight of 3RdMSB) is created, the inverting input terminal of the comparator C ₃ (- applied to).

In this manner, the voltage applied to the inverting input terminal (-) of the comparator C _k (k is a positive integer satisfying 1 ≦ k ≦ N−1) is set to a value that can be taken by the input analog voltage. The voltage ^obtained by adding or subtracting the voltage of (１ ／) ^k of the center value according to the output of the comparator C _k is the resistance R
_{It is} created by the voltage division of the resistor _{(k) 1} and the resistor R _{(k) 2} and applied to the inverting input terminal (-) of the comparator _{Ck + 1} .

Therefore, first, the input analog voltage is
The magnitude relation with the weight of the MSB is compared. If the magnitude relation is larger than the weight of the MSB, (MSB weight) + (2ndM)
If the weight is smaller than the weight of the MSB, the weight is compared with the weight of the second MSB, and so on. The comparison operation is sequentially performed by changing the comparison voltage according to the previous comparison result. That is, the analog voltage input to the input terminal IN is converted into an N-bit digital voltage, and the output terminals OUT _N , OUT _N−1 ,..., OUT ₁ (the output terminal OUT _N is MSB, the output terminal OUT ₁ is LSB).

For example, if the maximum value of the input analog voltage is 3
[V], when the minimum value is 0 [V] and 2.5 [V] is input to the input terminal IN, the input analog voltage 2.5
[V] is first compared with the center value 1.5 [V] of the input analog voltage as shown in FIG. Since the input analog voltage is larger than the comparison voltage 1.5 [V], MS
B becomes 1 and next, as shown in FIG. 4B, with respect to the previous comparison voltage 1.5 [V], the center value 1.5 [V] of the input analog voltage is (1/1). 2) It is compared with 2.25 [V] to which ¹ = 0.75 [V] is added. Since the input analog voltage is larger than the comparison voltage 2.25 [V], 2ndM
SB becomes 1, and then, as shown in (c) of FIG. 4, the center value of the input analog voltage is 1.5 [V] (1/1) with respect to the previous comparison voltage of 2.25 [V]. 2) ² = 0.375 [V]
Is compared with 2.625 [V] to which is added. Since the input analog voltage is smaller than the comparison voltage 2.625 [V], the 3rd MSB becomes 0, and the next comparison voltage 2.625 [V] as shown in FIG. (1/2) ³ of the center value of the input analog voltage 1.5 [V]
= 0.1875 [V] is compared with 2.4375 [V] obtained by subtraction. The input analog voltage is the comparison voltage 2.4375
Since it is larger than [V], the 4th MSB is 1. Hereinafter, similarly, the input analog voltages are compared while sequentially changing the comparison voltage, and a total of N comparison operations are performed.

As described above, in the A / D conversion circuit of this embodiment, since there is no subtraction circuit and amplification circuit, the resistance value of the ON resistance of the transistor constituting each selector is determined by the resistance R _{(k) for} dividing the resistance. ₁ , the resistance value of R _{(k) 2} is made sufficiently small, the pairing between the resistance R _{(k) 1} and the resistance R _{(k) 2} is made high, and the offset of the buffer B _k is sufficiently reduced. As long as it is kept small, the cause of the error is eliminated, and highly accurate A / D conversion becomes possible.

For the input analog voltage increasing at a constant slope, the 4-bit A /
FIG. 5 shows the transition of the LSB output of the D conversion circuit. From the figure, the LSB changes with a substantially uniform width.
It can be seen that the accuracy of the A / D conversion is high.

[0033]

As described above, according to the present invention,
Since a subtraction circuit and an amplification circuit are not required, an error generation factor can be eliminated. Therefore, a highly accurate multi-bit A / D conversion circuit using a cascade conversion method can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an A / D conversion circuit using a cascade conversion method according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a selector.

FIG. 3 is a diagram showing specific examples of a maximum potential point, a minimum potential point, and a central potential point.

FIG. 4 is a diagram illustrating a comparison operation by the A / D conversion circuit having the configuration illustrated in FIG. 1;

FIG. 5 shows the LSB of the 4-bit A / D conversion circuit according to the configuration of the present embodiment when the input is increased at a constant slope.
It is a figure showing a situation of transition of output.

FIG. 6 is a diagram showing a configuration of a conventional A / D conversion circuit using a cascade conversion method.

FIG. 7 is a diagram showing a transition of an LSB output of a conventional 4-bit A / D conversion circuit when an input is increased at a constant slope.

[Explanation of symbols]

_{C 1, C 2, ...,} C N comparators _{S 1, S 2, ...,} S N selector _{E 2, E 3, ...,} E N-1 exclusive inverted output gate _{R (1) 1, R (} 1 _{) 2} , R _{(2) 1} , R _{(2) 2} , ..., R _{(N-1) 1} , R
_{(N-1) 2} resistor _{B 1, B 2, ...,} MOS -type transistor INV inverting gate R ₁ of B _N-1 buffer Q1, Q3 N channel MOS transistor Q2, Q4 P channel, R _2, R _3, R ₄ resistance B _H , B _M , B _L buffer

Claims (2)

[Claims] An A / D conversion circuit for converting an analog signal into a digital signal by a cascade connection method, wherein an N-stage (N-stage) which compares an input analog voltage with a reference voltage and performs a binary output according to the magnitude relation between the reference voltages. N is a positive integer, a binarization circuit, a circuit for providing a center value of values that can be taken by the input analog voltage to the first-stage binarization circuit as the reference voltage, and a k-th stage (k is 1 ≦ With respect to the reference voltage supplied to the binarization circuit of (k ≦ N−1), a voltage of (１ ／) ^k of a central value of a value that can be taken by the input analog voltage is set to a k-th stage. The voltage added or subtracted according to the binary output of the binarization circuit of (1) is created by resistance division, and (k +
1) a circuit for applying the reference voltage to the binarization circuit of the stage. 2. The binarizing circuit has two input terminals, a non-inverting input terminal and an inverting input terminal, and a voltage applied to the non-inverting input terminal is higher than a voltage applied to the inverting input terminal. Is higher, the comparator outputs a high-level voltage.On the other hand, if the voltage applied to the inverting input terminal is higher than the voltage applied to the non-inverting input terminal, the comparator outputs a low-level voltage. The input analog voltage is applied to the non-inverting input terminal of the comparator.
The center value of the possible value of the input analog voltage is applied to the inverting input terminal of the first-stage comparator, and has two input terminals, a first input terminal and a second input terminal, and a switching terminal. Output the voltage applied to the first input terminal when the input to the switching terminal is at a high level,
When the input to the switching terminal is at a low level, there are (N-1) -stage selectors that output a voltage applied to the second input terminal. The first-stage selector has a value that can be taken by the input analog voltage. A maximum value is applied to the first input terminal, and a minimum value of values that the input analog voltage can take is applied to the second input terminal, and an output side of a first-stage comparator is connected to the switching terminal. Yes,
For the selector at the m-th stage (m is a positive integer satisfying 2 ≦ m ≦ N−1), an exclusive input that inputs the output voltage of the (m−1) -th stage comparator and the output voltage of the m-th stage comparator The output side of the OR gate is connected to the switching terminal, and if the high level or the low level is aligned with the input of the exclusive OR gate, the output voltage of the (m-1) -th stage selector is output. If the input of the exclusive OR gate does not have a high level or a low level,
The output voltage of the (m-1) th stage selector and the inverting input of the (m-1) th stage comparator are output so that the voltage applied to the inverting input terminal of the (m-1) th stage comparator is output. The voltage applied to the terminals is applied to the first input terminal and the second input terminal, and is further connected in series between the inverting input terminal side of the k-th stage comparator and the output side of the k-th stage selector. And a buffer whose input side is connected to a connection point between the two resistors, and an inverting input terminal of the (k + 1) -th stage comparator is provided on the output side of the buffer. 2. The A / D conversion circuit according to claim 1, wherein the A / D conversion circuit is connected.