JPS63236413A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To shorten an A/D conversion time, by executing analog operations in parallel in all of the bits, and deciding a reference voltage to be impressed on each analog voltage comparator in a moment. CONSTITUTION:A/D conversion are executed for bits from a high-order bit to a low-order bit, then, the digital output of an arbitrary bit is decided by the digital outputs of all of the high-order bits higher than the bit and an input voltage. In other words, the reference voltage impressed on the comparator 1 of the arbitrary bit is decided by controlling a current on which weight of 2 is applied by a switch 3 being driven by the digital outputs of all of the high-order bits higher than the bit and which flows from a constant current source 4 to a resistance element 2. Also, since the arithmetic operation of each reference voltage is executed in parallel, the A/D conversion time can be reduced remarkably.

Description

[Detailed description of the invention]

[Summary] The present invention controls interlocking switches using the digital output results of the upper bits, performs analog calculations on the current flowing from the two weighted constant current sources to the passive elements, and calculates the reference voltage applied to the analog voltage comparator for each bit. It is an analog-to-digital converter that determines each signal in parallel. [Industrial Application Field] The present invention relates to an analog-to-digital (hereinafter referred to as AD) converter, and in particular to an analog-to-digital conversion that makes it possible to achieve high speed and miniaturization of the circuit by using addition in an analog manner. Regarding the structure of the vessel. [Prior Art] The successive approximation AD converter (FIG. 2), which is currently most commonly used, has one analog voltage comparator (hereinafter referred to as comparator; Cmp, 2.
1), 1 n-bit serial-to-parallel converter (
Serial ParallelConvert
er, 2.2), one n-1 bit digital-to-analog converter (D1g1talAnalogCo
nverter, 2.3) and one clock generator that controls the timing of the operations of the n-bit serial-to-parallel converter (2, 2) and the n-1 pit digital-to-analog converter (2, 3). vessel (C1ock G
enerator, 2.4), a reference voltage (V=-+,
2.5) With this configuration, the n-bit AD conversion time of the successive approximation type AD converter (FIG. 2), the operation delay time of the comparator (2, 1) and the serial/parallel converter (2, 2), and the digital/analog The establishment time of the converters (2, 3) is T nbl respectively.
When L, T Cap, T sea, and T Dnc, the following relational expression holds true. Tllbmouth≧n ・(Taap+Ts*a+TDac) -Toac
(1) In other words, the AD conversion time is approximately proportional to the number of conversion bits. Furthermore, the input signal V+□ targeted by the successive parallel AD converter is quantized voltage (
1/2 of the reference voltage Vr@r/2'), that is, 1/2LS
When changing by more than B, a circuit for sampling and holding the input signal V + n is required. On the other hand, the parallel comparison type AD converter (the third
(in this case n-bit quantization) consists of 2' series-connected resistive elements (RO~R2', 3.2), 2°-1 comparators (Cm p O~Cm p ;l-1 ,3
, 1), one 2'-ITOnx encoder (E
ncoder, 3. 3), one reference voltage R(V
The n-bit AD conversion time To, 1 of the parallel comparison type AD converter (Fig. 3) is the operating time of the comparator (3, 1) and the encoder (3.4). 3,
3) as T cap and T ECD, respectively, the following relational expression holds true. T nb+t: T o-e+ T ECD
(2) The n-bit AD conversion time almost does not depend on the number of conversion bits, but since the circuit scale of the parallel comparison type AD converter (Fig. 3) increases by 20 dimensions, the number of units that can be integrated is 10. The limit is quantization on the order of bits. [Problems to be Solved by the Present Invention] The present invention eliminates such conventional drawbacks, and when performing n-bit quantization, the increase in AD conversion time is less than or equal to n dimension, and the increase in circuit scale is It remains approximately n-dimensional. [Means for Solving the Problems] According to the present invention, in the case of an AD converter that targets n-bit quantization, the increase in circuit scale is approximately proportional to n. Further, in an AD converter, the increase in AD conversion time is approximately proportional to n or remains less than that. FIG. 1 is a block diagram of the configuration of an analog-to-digital converter according to the present invention. The present invention provides an n1ll comparator (
CP@~CP-+, (1)), n types of 2 weighted n・(n+1) constant current sources (I/2~I/2-
1(4)), n-1 interlocking switches (S W + =
S W −−+, (3)), and n resistance elements (Rs=Rrow 1, (2)) as passive elements.

[Action of the present invention]

The present invention sequentially performs AD conversion from the upper bit to the lower bit, and in this case, the digital output of any bit is determined by the digital outputs of all bits higher than that bit and the input voltage. In other words, the reference voltage applied to the comparator (1) of any bit is derived from a constant current source (4) weighted by 2 by an interlocking switch (3) driven by the digital output of all bits higher than that bit. Resistance element (2)
determined by controlling the current flowing through the Furthermore, since each reference voltage is calculated in parallel, the AD conversion time is very short. [Embodiment] According to the present invention, in the case of an AD converter that targets n-bit quantization, the increase in circuit scale is approximately proportional to n. Further, in an AD converter, the increase in AD conversion time is approximately proportional to n or remains less than that. The configuration of the present invention includes n comparators (CPs-CPn
-+, (1)), n types of 2 weighted n-(n
+1) constant current sources (E/2 to I/2n, (4))
, n-1 interlocking switches (S W + ~S W n
−+, (3)), n resistance elements (R・
~R・-1, (2)). The present invention will be described with reference to FIG. 1, which is a schematic diagram of the configuration of the present invention. The characteristics of the element and the values of variables in this case are determined as follows. ' First, regarding resistance (2), 1) The value of all resistances is R. Regarding comparator (1), 2) (input impedance)〉〉R1 3) When positive phase input terminal voltage ≧ negative phase input terminal voltage, digital output = 1. 4) At other times, digital output = 0° and in the case of interlocking switch (3), 5) When digital power level is 1, close to the right, 6) When digital input is 200, close to the left. The present invention will be explained below with reference to FIG. First, when the input voltage Van≧I/2・R, the comparator CP
The digital output (bitn-+) of --+(1) becomes 1. At that time, 5Wn-+ closes to the right and CP--a
The reference voltage V11-2 is determined. That is, V n-*=
I/2+I/4=0.75・I. Next, C
P o-2 compares vIn and V in-2. On the contrary, V+-
When <I/2・R, the digital output of CP-+ (b i
tn-+) becomes 0, 5W11-1 closes to the left, and V
Let n −e = I / 4 ·R. Therefore, the reference voltage V. -2 is expressed by the following equation. However, when vIIl ≧ - engineering ・R, b itl
l-+= 1, V: When n<-1・R, bit t-+
;O(4) Similarly, the reference voltage Vn-s of CP n-3
, ■@ is expressed by the following formula. However, when v10≧Vn-2, bit-z=1, v
,, when < v *-2, bit 11-2
= 0. (6) When vII and vI, bit+=
o. (8) becomes. Considering bit@, vI
Expressing Il, in the above operation, the reference voltage of the lower bit approaches the input voltage, similar to the operation of a successive approximation type AD converter. At that time, the time required to convert equations (3) to (9), that is, the n-bit AD conversion time 7 nbll
If the operation delay times of the comparator and interlocking switch are Tc1Ip, Tsl, and I, respectively, then Tn1t≦n
・(To++p+ Tsw) -Tsu (10
). Since an AD converter normally quantizes continuous analog signals one after another, the present AD converter operates very effectively for such applications. That is, the operating speed when AD conversion is repeatedly executed many times depends on the position at which the digital output of the comparator changes. For example, the AD conversion speed is the fastest when only the LSB digital output changes, and the slowest when the MSB digital output changes. Therefore, it is suitable for AD conversion when a signal such as an audio signal changes continuously. [Effects of the Invention] The present invention performs analog operations in parallel on all bits and instantaneously determines the reference voltage to be applied to each analog voltage comparator (1). The increase in AD conversion time remains below the n dimension, and the increase in circuit scale is approximately proportional to the n dimension.
The quantization limit of the transform is 10 bits or more.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of the configuration of the present invention. FIG. 2 is a schematic diagram of the configuration of a successive approximation type AD converter. FIG. 3 is a schematic diagram of the configuration of a parallel comparison type AD converter. (1) is a voltage comparator, (2) is a resistor, (3) is an interlocking switch, (4) is a constant current source, vIn is an input voltage, (2,1) is an analog voltage comparator, (2,2) is a serial-parallel converter, (2, 3) is a DA converter, (2, 4) is a clock generator, (2, 5) is a reference voltage, 1. The mouth is the input voltage, (3,1)
is an analog voltage comparator, (3,2) is a resistor, (3,3) is an encoder, (3,4) is a reference voltage, and v and n are input voltages. Special GF Criticism Large Tanaka Shock paper 1 Mikan 2 days

Claims (1)

[Claims] For each arbitrary bit, an input voltage applied to one input side is compared with a reference voltage applied to the other input side,
an analog voltage comparator (1) that generates a digital output signal and simultaneously controls each interlocking switch (3) connected one-to-one to the output line of the digital output signal; and each of the analog voltage comparators (1). An interlocking switch that is controlled by each of the digital outputs of the analog voltage comparator (1) and simultaneously closes and opens the current flowing from each constant current source (4) having the same value to each passive element (2) at a lower level than each of the analog voltage comparators (1). (3), a constant current source (4) connected to the interlocking switch (3) and generating a current weighted by 2 so as to uniquely generate the required reference voltage; a passive device connected at least to the other input of the comparator (1) and the plurality of interlocking switches (3) and generating a reference voltage determined by all the digital output results of the bits higher than the corresponding bit; element (2), performs analog operations in parallel on all bits, and each analog voltage comparator (
1) An analog-to-digital converter that instantly determines a reference voltage to be applied to the converter.