JP2011124747A - Clock phase synchronization circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stabilize a clock phase synchronization circuit over a long period and to reduce input disturbance influence, in relation to a clock phase synchronization circuit for outputting a clock having a phase synchronized with that of a reference clock. <P>SOLUTION: This clock phase synchronization circuit for obtaining an output signal d of a voltage-controlled oscillator 1 synchronized with the phase of reference input (a) includes: a storage means such as a memory inputting phase difference detection signals b obtained by making the frequency of the reference input (a) coincide with that of the output signal d of the voltage-controlled oscillator 1 and by comparing the phases thereof on a predetermined timing basis by a phase comparator 3 and sequentially storing them for a predetermined period; and an arithmetic processing means to obtain differences of the phase difference detection signals on a predetermined period basis as a phase variation, converting the phase variation to a control voltage of the voltage-controlled oscillator 1 corresponding to the phase variation when the phase variation is within an allowable range, and inputting a control voltage c into the voltage-controlled oscillator 1 as a control voltage corresponding to the previous phase variation or a control voltage for bringing the voltage-controlled oscillator into a free-running state when the phase variation is not within the allowable range. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a highly stable clock phase synchronization circuit that generates a clock synchronized with the phase of a reference clock.

  The hierarchical structure of each station in a general synchronous network is, for example, as shown in the explanatory diagram of the clock synchronous hierarchical structure in the synchronous network of FIG. In order of the upper station, the lower station, and the lowest station, the clock from the upper station in the hierarchical structure is used as a reference clock, and the lower station synchronizes with the phase of the reference clock to reproduce and output the clock. The transmission / reception processing is performed in phase synchronization. For example, when data transmission is performed between stations by applying a synchronous transmission method such as SDH or SONET, the lower station extracts a clock from the SDH / SONET signal received from the upper station side, and the internal clock phase The structure which performs the transmission / reception process by synchronizing is applied. Accordingly, each station located in the lower order with respect to the clock of the highest station regenerates the phase-synchronized clock and performs transmission / reception processing based on that clock.

  In this case, a phase locked loop (PLL) that generates a phase synchronized clock includes, for example, a voltage controlled oscillator 71, a filter 72, a phase comparator 73, and a frequency divider, as shown in FIG. The reference input is an upper station clock extracted from the SDH / SONET signal, and a voltage controlled oscillator (VCO; Voltage Controlled Oscillator) is used for the clock frequency of the reference input. ) When the output signal frequency of 71 is N times, the PLL output of the output of the voltage controlled oscillator 71 is divided by 1 / N by the frequency divider 74 to obtain a signal having the same frequency as the clock frequency of the reference input. And the phase of the voltage controlled oscillator output signal are compared by a phase comparator 73. And, an output signal corresponding to the phase difference, a control voltage of the voltage controlled oscillator 71 via a filter 72. The filter 72 generally has a low-pass configuration for suppressing an abrupt change in the output signal from the phase comparator 73, and the time constant that enables the voltage-controlled oscillator 71 to follow the phase comparison result. The configuration is selected. A PLL output synchronized with the reference input phase from the voltage-controlled oscillator 71, that is, a clock extracted from a synchronous transmission signal from a higher station and synchronized with the clock phase can be reproduced and output. When the frequency of the reference input and the PLL output is the same, the frequency divider 74 is omitted.

  FIG. 10 is an explanatory diagram of clock phase synchronization between stations in a conventional example, 75 is an A station, 76 is a B station, 77 and 78 are dedicated clock synchronization devices (devices similar to the above-described clock phase synchronization circuit), A1 to A4 indicate transmission apparatuses under the A station 75, B1 to B4 indicate transmission apparatuses under the B station 76, the transmission apparatuses A2 and B2 and the transmission apparatuses A3 and B3 are connected by a transmission path, and the transmission apparatus A1 , B1 and A4, B4 show the case of a configuration in which each is connected to a transmission device (not shown) of another station via a transmission path. The A station 75 and the B station 76 supply the reference clocks from the dedicated clock synchronizers 77 and 78 to the transmission apparatuses A1 to A4 and B1 to B4 in the station, respectively, and perform synchronous transmission processing. A case is shown in which 75 is the upper station and B station 76 is the lower station. Accordingly, each of the transmission devices A1 to A4 performs data transmission processing based on the in-station reference clock from the dedicated clock synchronization device 77 of the A station 75. For example, the transmission of the A station 75 is performed by the transmission device B2 of the B station 76. Data from the device A2 is received and the clock extracted from the received data is input to the dedicated clock synchronizer 78 as a reference input. The dedicated clock synchronizer 78 generates a clock synchronized with the reference input and supplies it as a reference clock in the station to each of the transmission apparatuses B1 to B4 in the station. In that case, the reference clock in the station A 75 and the station B 76 is set to 64 kHz, for example, and the clock for transmitting from each of the transmission devices A1 to A4 and B1 to B4 is, for example, 2.4 GHz or 10 GHz multiplied by 64 kHz. As described above, data is transmitted at a transmission rate of 2.4 GHz or 10 GHz between transmission apparatuses connected via a transmission path.

  When the dedicated clock synchronizer of each station of the hierarchical structure in the synchronous network as described above is normally performing a synchronous operation, the synchronous transmission process synchronized with the clock phase of the highest station is executed in the synchronous network. be able to. However, if the clock phase from the dedicated clock synchronizer of any of the stations in the synchronization network becomes an abnormal state such as loss of synchronization with the clock phase of the upper station, the station of the lower hierarchy than the station where the abnormality occurred Since a normal clock cannot be received and reproduced, transmission errors frequently occur in data transmission between lower stations with different upper stations. There has been proposed a clock synchronization circuit that generates a clock while maintaining the phase state immediately before the input interruption when the reference clock input is interrupted (see, for example, Patent Document 1). This is because the control signal input to the voltage controlled oscillator from the phase comparator via the filter is stored in the memory and always updated to a new control signal. When a clock input interruption is detected, the control signal stored immediately before is continued. By inputting the voltage into the voltage controlled oscillator, at least the phase state immediately before the clock input is interrupted is maintained and the clock is continuously generated.

JP-A-5-30092

  As shown in FIG. 10 described above, dedicated clock synchronizers 77 and 78 are provided in each station of the hierarchical structure, a reference clock is supplied to a plurality of transmission apparatuses in the station, and dedicated clock synchronization of the lower B station 76 of the hierarchical structure is performed. In the system configuration in which the device 78 is phase-synchronized with the clock from the upper station A 75 and supplied as a reference clock to a plurality of transmission devices B1 to B4 in the station, a clock synchronization device is provided for each transmission device. Cost reduction can be achieved as compared with the provided configuration. However, when a clock abnormality occurs in the upper A station 75, the transmission devices B1 to B4 of the lower B station under the higher A station 75 are synchronized with the abnormal clock of the upper A station 75, respectively. Even if the data transmission between the transmission apparatuses B1 to B4 is normal, a communication error in which transmission errors frequently occur due to a shift in the clock phase between the lower stations under the control of other higher stations. . Therefore, there is a problem that it takes a long time to investigate the cause of the occurrence of a communication abnormality because normal communication is possible depending on the transmission apparatus of the communication partner.

  In the case where the dedicated clock synchronizers 77 and 78 of each station are highly stabilized, the dedicated clock synchronizer 78 of the lower B station 76 when the upper A station 75 fails is the upper clock as described above. Since it is synchronized with the clock phase of the A station 75, the influence of the failure of the upper station in this case does not immediately appear as a transmission error, but the influence of the transmission error appears as time passes. In that case, there is a problem that the recovery process is delayed because it takes a long time to investigate the cause. The clock synchronization circuit has a feedback loop for inputting the phase comparison result between the input clock and the output clock to the voltage controlled oscillator via the filter. By slowing the response characteristic of the feedback loop including the filter, A means to mitigate the effects of temporary disturbances can be considered. However, it is difficult to suppress the influence caused by the occurrence of clock synchronization abnormality in the upper station.

  An object of the present invention is to solve the above-mentioned conventional problems, to stabilize a clock phase for a long period of time, and to reduce the influence of an input disturbance due to an abnormal clock as a reference input. I will provide a.

  The clock phase synchronization circuit of the present invention obtains a phase difference between a reference input as a reference and an output signal of the voltage controlled oscillator or a signal obtained by dividing the output signal by a phase comparator, and obtains a control voltage corresponding to the phase difference. A clock phase synchronization circuit that inputs to the voltage controlled oscillator and outputs a clock that is phase-synchronized with the reference input, and matches a frequency of the reference input and a frequency of an output signal of the voltage controlled oscillator to a predetermined value. A phase difference detection signal that is phase-compared at each timing is inputted and stored sequentially for at least a predetermined period, and a difference between the phase difference detection signals stored in the storage means for each predetermined period is obtained as a phase fluctuation amount, It is determined whether or not the fluctuation amount is an allowable value, and if it is an allowable value, it is converted to the control voltage of the voltage controlled oscillator corresponding to the phase fluctuation amount, There time as a control voltage or control voltage to be free-running state corresponding to the last phase deviation, and a processing means for inputting a control voltage to the voltage controlled oscillator.

  Also, the voltage controlled oscillator, a phase comparator for obtaining a phase difference between the reference input and an output signal of the voltage controlled oscillator or a signal obtained by dividing the output signal by digital processing, and a phase difference detection signal of the phase comparator And a control value calculation unit that outputs a control voltage of the voltage controlled oscillator, and the control value calculation unit includes a memory that sequentially stores phase difference detection signals from the phase comparator over a predetermined period, and a level for the memory. Controls writing and reading of the phase difference detection signal, obtains the phase difference detection signal difference for each predetermined period as the phase fluctuation amount, determines whether this phase fluctuation amount is an allowable value, and if it is an allowable value, the phase fluctuation amount Control voltage input to the voltage controlled oscillator as a control voltage corresponding to the previous phase fluctuation amount or a control voltage to be in a free-running state when it is not an allowable value. And a configuration including a processor for performing.

  Also, the voltage controlled oscillator, a phase comparator for obtaining a phase difference between the reference input and an output signal of the voltage controlled oscillator or a signal obtained by dividing the output signal by digital processing, and a phase difference detection signal of the phase comparator And a control value calculation unit that outputs a control voltage of the voltage controlled oscillator, and the control value calculation unit sequentially shifts and stores the phase difference detection signal of the phase comparator, and the shift register The difference calculation unit that obtains the difference between the phase difference detection signals for each predetermined period sequentially shifted as described above as a phase fluctuation amount, and determines whether or not the phase fluctuation amount by the difference calculation unit is an allowable value. The control voltage of the voltage controlled oscillator corresponding to the phase fluctuation amount is set by the A converter, and when it is not an allowable value, the control voltage by the D / A converter corresponding to the previous phase fluctuation amount or a control state that becomes a free-running state. As a voltage, and a configuration including a control unit for controlling the input to the voltage controlled oscillator.

  By comparing the amount of variation in the phase difference between the reference input and the output signal of the voltage controlled oscillator over a relatively long period of time, a highly accurate phase error can be detected, thus enabling highly stable operation. There are advantages. Thereby, it is possible to avoid or reduce the influence of the input disturbance based on the clock phase fluctuation on the upper side.

It is a principle explanatory view of the present invention. It is explanatory drawing of Example 1 of this invention. It is operation | movement explanatory drawing of Example 1 of this invention. It is operation | movement explanatory drawing of Example 1 of this invention. It is explanatory drawing of the phase difference calculation of Example 1 of this invention. It is a flowchart of the phase difference calculation of Example 1 of this invention. It is explanatory drawing of Example 2 of this invention. It is explanatory drawing of the hierarchical structure of the clock synchronization in a synchronous network. It is explanatory drawing of the phase locked loop of a prior art example. It is explanatory drawing of the clock phase synchronization between the stations of a prior art example.

  Referring to FIG. 1, the clock phase synchronization circuit according to the present invention calculates a phase difference between a reference input “a” as a reference and an output signal “d” of the voltage controlled oscillator 1 or a signal “e” obtained by dividing the output signal “d”. A clock phase synchronization circuit that inputs a control voltage corresponding to this phase difference to the voltage controlled oscillator 1 and outputs a clock d that is phase-synchronized with the reference input a, the frequency of the reference input a and the voltage controlled oscillator A storage means for inputting a phase difference detection signal b that is matched in frequency with a frequency of one output signal d and phase-comparing at every predetermined timing and sequentially storing it for at least a predetermined period; and for every predetermined period stored in the storage means The phase difference detection signal difference is obtained as a phase fluctuation amount, and it is determined whether or not the phase fluctuation amount is an allowable value. If the phase fluctuation amount is an allowable value, the voltage control signal corresponding to the phase fluctuation amount is determined. When the control voltage is converted to the control voltage of the detector, and the control voltage is not an allowable value, the control voltage calculating unit 2 inputs the control voltage c to the voltage controlled oscillator 1 as the control voltage corresponding to the previous phase fluctuation amount or the control voltage to be in a free-running state. Arithmetic processing means.

  FIG. 1 is a diagram for explaining the principle of the present invention, in which 1 is a voltage controlled oscillator, 2 is a control value calculation unit, 3 is a phase comparator, 4 is a 1 / N frequency divider, 5 is a multiplier, The multiplier 5 shown in FIG. 5 has a multiplication ratio according to the relationship between the frequency of the output signal d of the voltage controlled oscillator 1 and the frequency of the clock signal input to the phase comparator 3 and the control calculation unit 2 or is omitted. It is something that can be done. Further, a signal e obtained by dividing the output signal d of the voltage controlled oscillator 1 by the frequency divider 4 and the reference input a are compared by the phase comparator 3, and the comparison output signal b is input to the control value calculation unit 2. The control value calculation unit 2 constitutes calculation processing means including storage means such as a memory. The control value calculation unit 2 calculates a control signal c, inputs the control signal c to the voltage controlled oscillator 1, and outputs an output signal d synchronized with the phase of the reference input a. Is controlled to be output from the voltage controlled oscillator 1. For example, when the output signal d is 5 MHz and the operation speed of the control value calculator 2 and the phase comparator 3 is 100 MHz, the multiplier 5 multiplies the output signal d by 20. When the operation speed of the phase comparator 3 and the operation speed of the control value calculation unit 2 are different from each other, a multiplier corresponding to the difference from the frequency of the output signal d can be provided. The frequency divider 4 is used to match the frequency of the output signal d of the voltage controlled oscillator 1 with the frequency of the reference input a input to the phase comparator 3. The peripheral 4 can be omitted.

  The phase comparator 3 for obtaining the phase difference between the reference input a and the divided output signal e can have a known analog configuration or digital configuration. In the case of a digital configuration, for example, a reference It is possible to apply a configuration that counts between the rising timing of the input a and the rising timing of the signal e and uses the count value as a phase difference signal. The control value calculation unit 2 calculates a phase fluctuation amount or a frequency fluctuation amount at a preset time interval based on the phase comparison output signal from the phase comparator 3, and outputs a control signal c corresponding to the calculated value as a voltage. The signal is input to the controlled oscillator 1 and the phase of the output signal e is synchronized with the phase of the reference input a. The control value calculator 2 includes storage means such as a memory and arithmetic processing means such as a processor. The storage means sequentially stores the phase comparison output signal b for a predetermined period, and the phase comparison output signal for each predetermined period. b is compared by the arithmetic processing means, and if the difference is within the allowable range, the control signal c of the voltage controlled oscillator 1 is generated based on the comparison difference. If the difference is not within the allowable range, the comparison difference is The control signal is left as it is last time, or is set as a control signal for setting the voltage controlled oscillator 1 in a free-running state. In this case, the operation clock signal of the control value calculation unit 2 and the phase comparator 3 is used as the output signal d of the voltage controlled oscillator 1 as it is or the signal of the frequency multiplied by the multiplier 5 is used. It is also possible to form by other independent configurations.

  FIG. 2 is an explanatory diagram of the first embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same names, and the multiplier 5 indicated by a dotted line is connected to the output signal d of the voltage controlled oscillator 1 as described above. In relation to the operation of the control value calculation unit 2 and the phase comparator 3, it can be provided as necessary. The frequency divider 4 also outputs the output signal d of the voltage controlled oscillator 1 as described above. And the frequency of the reference input a input to the phase comparator 3 can be omitted. The control value calculation unit 2 includes a processor (CPU) 11 that constitutes an arithmetic processing unit, a memory (MEM) 12 and holding circuits 13 and 14 that constitute a storage unit, and a D / A converter (D / A) 15. The phase comparator 3 compares the phases of the reference input a and the signal e obtained by frequency-dividing the output signal d of the voltage controlled oscillator 1 by the frequency divider 4, and uses a plurality of digital comparison processes. A bit comparison phase comparison output signal is input to the control value calculator 2. For example, the phase difference is obtained by counting between the rising timing of the reference input a and the rising timing of the signal e by the output signal d of the voltage controlled oscillator 1 or a signal obtained by multiplying the output signal d by the multiplier 5. The data is temporarily held in the holding circuit 13 by control, and sequentially transferred to the memory 12 and held. Then, the difference between the phase difference output signal before the predetermined period held in the memory 12 and the current phase difference output signal held in the holding circuit 13 is obtained by the processor 11, and the difference corresponds to the frequency deviation. Determines whether or not the change in the output frequency of the voltage controlled oscillator 1 is within the allowable value range. If the change is within the allowable value range, the change is held by the holding circuit 14 and converted to the analog control signal c by the D / A converter 15. The voltage is converted and input to the voltage controlled oscillator 1. If the change range of the output frequency is large and exceeds the allowable value range, no input is made to the holding circuit 14. Thereby, since the control signal c maintains the previous value, the frequency of the output signal d of the voltage controlled oscillator 1 continues the previous state. Alternatively, when the allowable value range is exceeded, a control signal c that causes the voltage controlled oscillator 1 to be in a free-running state can be formed and input to the voltage controlled oscillator 1.

  FIG. 3 is a diagram for explaining the operation of the first embodiment of the present invention. FIG. 3A shows the reference input a, the output signal d of the voltage controlled oscillator 1 and the phase difference signal (as a rectangular wave) in FIG. (B) in the figure shows the relationship between the frequency deviation F and the control voltage V of the voltage controlled oscillator 1. In FIG. 9A, when the reference input (a) and the voltage controlled oscillator output (b) are stable, the phase difference signal (c) continues to have a constant time width. Although the phase difference between the reference input and the voltage controlled oscillator output is a phase difference of 180 degrees, which is half of one cycle, as shown in the figure, the case where the phase synchronization state is set is shown. It is also possible to set the phase synchronization state when the output of the controlled oscillator is at the same rising timing. Then, as the phase relationship between the reference input and the voltage controlled oscillator output is shown as the reference input (d) and the voltage controlled oscillator output (e), the voltage controlled oscillator output fluctuates in the direction indicated by the dotted arrow, and the fluctuation amount Is Δ1, the phase difference signal (f) is (Φ0 + Δ1) at the next phase comparison timing and (Φ0 + Δ1 + Δ1) at the next phase comparison timing with respect to the phase difference Φ0 in the stable state. Such a phase fluctuation amount is calculated at a predetermined time interval, and the characteristic of the voltage controlled oscillator 1 has a control characteristic that enables a shift control of a frequency of 0.1 ppm at 1 V as shown in FIG. In this case, the phase of the output signal frequency of the voltage controlled oscillator 1 and the frequency of the reference input can be synchronized by changing the control voltage by 100 mV with respect to the frequency deviation = 0.01 ppm.

  FIG. 4 is a diagram for explaining the operation of the first embodiment of the present invention, showing an example of the operation in time series. (A) is a reference input a, (B) is a divided output signal e, (C ) Shows the output signal d of the voltage controlled oscillator 1, (D) shows the phase difference output signal b, and (E) shows the phase variation calculation process with the time axis shortened. The reference input a and the divided output signal e correspond to the reference input (a) and the voltage controlled oscillator output (b) of FIG. 3, but the output signal before frequency division of the voltage controlled oscillator 1 is (C ) Output signal d. Further, the control value calculation unit 2 counts the phase difference between the reference input a in (A) and the divided output signal e in (B) by the output signal d in (C) or a signal obtained by multiplying by the multiplier 5. Asking. Thereby, the phase difference output signal b from the phase comparator 3 becomes the comparison results M1, M2,. The comparison results M1, M2,... Are sequentially held in the memory 12 of the control value calculation unit 2 for a predetermined period. Therefore, as shown in (E), the memory 12 holds the comparison results shown as M1, M2, M3,. The processor 11 obtains a difference between M1 and M11 as a comparison result of the phase difference for each predetermined period held in the memory 12, for example. In this case, if the reference input a of (A) and the divided output signal e of (B) are 8 kHz, and the signal applied to the control value calculation unit 2 and the phase comparator 3 of (C) is 100 MHz, one cycle of 8 kHz Thus, the phase difference can be obtained with an accuracy of 10 nsec. When the difference for 10 cycles is obtained as in M1-M11 described above, the phase difference can be obtained with an accuracy of 10 times 1 nsec.

FIG. 5 is an explanatory diagram of the phase difference calculation. M1, M2, M3,... MK + 1, MK + 2,... Indicate the phase difference detection results shown in FIG. The difference of the phase difference detection result is obtained. In that case, as shown in the figure, K = 80000, and the frequency deviation is obtained at a time interval of 8 kHz period. That is, the frequency difference can be obtained with an accuracy of 1 × 10 ⁻⁸ by obtaining X1 = M1−M80001, X2 = M2−M80002, X3 = 80003,. Further, if K indicating the time interval is 10 times K = 800000, the accuracy of the frequency deviation by X1 = M1−M800001, X2 = 800002,... Is 1 × 10 ⁻⁹ . Therefore, compared with the case where the voltage controlled oscillator 1 is controlled by the sequentially obtained phase difference, the phase difference obtained sequentially is compared at a predetermined time interval, thereby improving the phase difference detection accuracy and the voltage with high accuracy. It becomes possible to control the output frequency of the controlled oscillator. The phase difference detection result must be sequentially stored in the memory 12 in FIG. 2 over a predetermined period, and the required capacity of the memory 2 and address control, etc. are taken into account to meet the required accuracy. This memory configuration is applied.

  FIG. 6 is a flowchart of the phase difference calculation, showing the main points of the control value calculation unit described above, and will be described with reference to FIGS. The control value calculation unit 2 uses the phase difference between the reference input a by the phase comparator 3 and the output signal d of the voltage controlled oscillator 1 or the signal e divided by the frequency divider 4 as the output signal d of the voltage controlled oscillator 1. Alternatively, the difference between the i-th phase difference signal Mi and the (8000 + i) -th phase difference signal M (8000 + i) is obtained (a1). In this case, it is determined whether or not the frequency deviation Xi = Mi−M (8000 + i) is less than or equal to an allowable value (a2). When the value is less than the allowable value, a control value corresponding to the frequency deviation Xi is obtained and held in the holding circuit 14, and input to the voltage controlled oscillator 1 as an analog control voltage by the D / A converter 15 (a3). In step (a2), if the frequency deviation Xi shows a fluctuation exceeding the allowable value, the self-running control value is input to the voltage controlled oscillator 1 (a4). Alternatively, the control value in the case of the frequency deviation not exceeding the previous allowable value can be continuously input to the voltage controlled oscillator 1.

  FIG. 7 is an explanatory diagram of Embodiment 2 of the present invention, and the same reference numerals as those in FIGS. 1 and 2 denote the same name portions. A case where the control value calculation unit 2 in this embodiment is configured by a control unit 21, a shift register 22, a difference calculation unit 23, and a D / A conversion unit 24 is shown. The control unit 21 of the control value calculation unit 2 is configured to operate using the output signal of the voltage controlled oscillator 1 or the signal multiplied by the multiplier 5 as a clock, and performs shift control of the shift register 22 using the clock as a shift clock. The shift register 22 controls the phase comparison output signal b having a plurality of bits when the phase comparator 3 inputs the comparison output signal b having a plurality of bits to the control value calculation unit 2 as shown in FIG. Since the value is input to the value calculation unit 2, the shift register 22 is also configured to sequentially shift the phase comparison output signal b having a plurality of bits. For example, as shown in FIG. 4E, the shift stage is configured to hold and sequentially shift the phase comparison results M1 to M11 having a plurality of bits when obtaining the difference between the phase comparison results M1 and M11. To do. Then, the difference calculation unit 23 calculates the difference between the phase comparison results M1 and M11, and the control unit 21 performs, for example, a determination process in step (a2) of the flowchart of FIG. If so, it is converted to an analog control voltage by the D / A converter 24 and the output frequency of the voltage controlled oscillator 1 is controlled. If the difference is not less than the allowable value, the difference value of the last stage of the shift register 22 is held, and the control voltage continuously converted by the D / A converter 24 is input to the voltage controlled oscillator 1. As a result, the clock can be kept stable as described above.

DESCRIPTION OF SYMBOLS 1 Voltage controlled oscillator 2 Control value calculating part 3 Phase comparator 4 Divider 5 Multiplier 11 Processor (CPU)
12 Memory (MEM)
13, 14 Holding circuit 15 D / A converter 21 Control unit 22 Shift register 23 Difference calculation unit 24 D / A conversion unit

Claims (3)

A phase difference between a reference input as a reference and an output signal of the voltage controlled oscillator or a signal obtained by dividing the output signal is obtained by a phase comparator, and a control voltage corresponding to the phase difference is input to the voltage controlled oscillator. In a clock phase synchronization circuit that outputs a clock that is phase-synchronized with the reference input,
Storage means for inputting a phase difference detection signal obtained by matching the frequency of the reference input with the frequency of the output signal of the voltage controlled oscillator and comparing the phases at predetermined timings, and sequentially storing the phase difference detection signal for at least a predetermined period;
The difference between the phase difference detection signals stored in the storage means for each predetermined period is obtained as a phase fluctuation amount, and it is determined whether or not the phase fluctuation amount is an allowable value. Arithmetic processing means for converting the voltage-controlled oscillator to a control voltage and inputting the control voltage to the voltage-controlled oscillator as a control voltage corresponding to the previous phase fluctuation amount or a control voltage to be in a free-running state when it is not an allowable value And a clock phase synchronization circuit.   A phase comparator for obtaining a phase difference between the voltage control oscillator, the reference input and an output signal of the voltage control oscillator or a signal obtained by dividing the output signal by digital processing, and a phase difference detection signal of the phase comparator; A control value calculation unit that inputs and outputs a control voltage of the voltage controlled oscillator, the control value calculation unit sequentially storing a phase difference detection signal from the phase comparator over a predetermined period, and the memory Control the writing and reading of the phase difference detection signal with respect to, determine the difference of the phase difference detection signal for each predetermined period as a phase fluctuation amount, determine whether the phase fluctuation amount is an allowable value, The voltage controlled oscillator is a control voltage corresponding to the phase fluctuation amount, and when it is not an allowable value, the voltage controlled oscillation voltage is a control voltage corresponding to the previous phase fluctuation amount or a control voltage that is in a free-running state. Clock phase synchronizing circuit according to claim 1, further comprising a configuration including a processor for controlling input to vessel.   A phase comparator for obtaining a phase difference between the voltage control oscillator, the reference input and an output signal of the voltage control oscillator or a signal obtained by dividing the output signal by digital processing, and a phase difference detection signal of the phase comparator; A control value calculation unit that inputs and outputs a control voltage of the voltage controlled oscillator, the control value calculation unit sequentially shifts and stores the phase difference detection signal of the phase comparator; and A difference calculation unit that obtains a difference between the phase difference detection signals for each predetermined period sequentially shifted by a shift register as a phase fluctuation amount, and determines whether or not the phase fluctuation amount by the difference calculation unit is an allowable value. Is the control voltage of the voltage controlled oscillator corresponding to the phase fluctuation amount by the D / A converter, and when it is not an allowable value, the control voltage or the control voltage by the D / A converter corresponding to the previous phase fluctuation amount. As a control voltage to be free-running state, the clock phase synchronization circuit according to claim 1, characterized in that it comprises a structure including a control unit for controlling input to said voltage controlled oscillator.

Images