JPH11261415A - Method and circuit for phase holding - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily operate a circuit at high speed by making a phase difference from a synchronous clock source smaller and a phase fluctuation smaller at the time of HOLDOVER when a time of HOLDOVER becomes long with respect to digital data sampled at the time of normal state. SOLUTION: In a phase holding method for holding a synchronous source clock of a synchronous digital hierarchy(SDH) device, digital data that sample the synchronous source clock signal at the time of normal state are stored in a storage means, the digital data of the storage means are selected when the clock cutoff is detected, and an oscillation pulse of a voltage control oscillator 11 is generated. Also, in the phase holding method, the digital data of the storage means are added and subtracted by data obtained by phase comparing the synchronous source clock signal with the oscillation pulse of the voltage control oscillator 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a phase holding method for holding a phase of a synchronization source clock signal of an SDH device or the like, and a circuit thereof.

[0002]

2. Description of the Related Art SDH (Synchronous Digital Hierarch)
y: In a transmission device for a synchronization signal such as a device for synchronizing a high-speed relay speed system compiled by the ITU-T, a terminal having a synchronization source clock signal transmits the transmission signal in synchronization with the synchronization source clock signal. In other stations, a transmission signal from a terminal station having a reference clock is used as a synchronous clock source and used to demodulate transmitted data. Operation is performed by synchronizing the transmission network by this method. However, if the transmission signal of the synchronization clock source is interrupted at a station on the way, the synchronization of the transmission network is lost because the synchronization clock source is lost.

[0003] For this reason, ITU-T G. The 813 recommendation is:
Even when the synchronous clock source is lost, an operation of retaining the phase before the loss (this operation is called HOLDOVER) is recommended. MTIE (Maximum Time Interval Error) indicates a phase characteristic between the held phase and the original phase that was synchronized at the time of HOLDOVER of the phase holding. MTIE is based on ITU-TG. 81
0, G. In the definition of 811, if the observation time is S, it is expressed by the following equation.

MTIE (S) = max × (t) −min × (t) Here, x (t) is an expression called Time error function (time error formula), and a certain time t is calculated using an ideal clock. When measured, it is defined by the following equation.

X (t) = T (t) -TREF (t) = (2πν'nomt / 2πνnom)-(2πνnomt / 2πνnom) = (ν'nomt / νnom) -t = ((ν'nom / νnom) -1) t where νnom: ideal clock frequency ν'nom: clock under test From this equation, x (t) is the time T created by the clock under test
A value obtained by subtracting the time TREF (t) generated by the ideal clock from (t), that is, a time difference due to a frequency difference from the ideal clock. Here, as an example, FIG.
TREF (t) is shown, and T (t) is shown by a solid line. In the graph of FIG. 10, the horizontal axis is time t, and the vertical axis is delay time t, indicating the same time. Time TREF created by ideal clock
Since (t) is TREF (t) = t, when the time t on the horizontal axis is the time t on the vertical axis, it is a straight line with a slope of 45 °. On the other hand, the time T (t) generated by the clock to be measured is T (t) = (ν′nom / νnom) t, and when the time t is on the horizontal axis, the time on the vertical axis is (ν′nom / νnom).
t. At this time, if ν'nom> νnom, (ν'nom / νnom)> 1, and a straight line with a slope of 45 ° or more (region above TREF (t))
When ν′nom <νnom, (ν′nom / νnom) <1 and becomes a straight line with a slope of 45 ° or less, that is, (a region below TREF (t)).

The MTIE is a time difference from TREF (t), which is a clock phase difference. Therefore, MT
IE is expressed as the absolute value of | T (t) -TREF (t) |.

Conventionally, using the circuit having the configuration shown in FIG. 11, digitally sampled phase information in a steady state is stored in a phase storage circuit 7, and when the synchronization source clock signal is lost,
The digital data stored in the phase storage circuit 7 is used to perform the phase hold HOLDOVER operation.

[0008] According to FIG. 11, the present phase holding apparatus uses SD.
In order for the H device to synchronize with the synchronization source clock signal transmitted from the terminal having the reference clock of the SDH network, the synchronization source clock signal demodulated from the input signal is synchronized with the synchronization source clock divided signal via the frequency divider N1. Phase comparator 3 for comparing the phase of the oscillation output of the voltage controlled oscillator with the frequency divider M2, and an A / D converter 4 for A / D converting the output of the phase comparator 3
An oscillator 5 for generating a sample signal to be sampled by the A / D conversion circuit 4, a phase storage circuit 7 for storing a digital output of the A / D conversion circuit 4, and a digital output of the A / D conversion circuit 4. And a selection circuit 8 for selecting one of the output data of the phase storage circuit 7, a D / A conversion circuit 8 for D / A conversion of the output of the selection circuit 8, and an output of the D / A conversion circuit 8. Loop filter 10 that passes low frequency
A voltage-controlled oscillator 11 to which an output of the loop filter 10 is supplied; a clock-disconnection detection circuit 12 for detecting a clock-disconnection from the synchronization source clock signal; and a clock-disconnection signal detected by the clock-disconnection detection circuit 12 And a HOLDOVER control circuit 13 for instructing storage readout to the phase storage circuit 7 and for instructing the selection circuit 8 to select output data of the phase storage circuit 7, and the A / A based on the output of the oscillator 5. It includes a D conversion circuit 4, the phase storage circuit 7, the selection circuit 8, and a timing generation circuit 6 for supplying a timing signal to the HOLDOVER control circuit 13.

In the phase holding device having the above configuration, the stationary
By synchronizing the synchronization source clock signal with the voltage controlled oscillator 11 constituting the PLL circuit, a synchronization signal synchronized with the synchronization source clock signal is transmitted to the timing operation section in the SDH device. On the other hand, when the synchronization source clock signal is disconnected, the clock disconnection detection circuit 12 detects the disconnection of the synchronization source clock signal, and receives the disconnected state by the HOLDOVER control circuit 13, and the HOLDOVER control circuit 13 In response to the timing signal of the timing generation circuit, read support for the digital data stored in the phase storage circuit 7 is provided, and an instruction to select digital data from the phase storage circuit 7 is provided to the selection circuit 8. In this way, when the synchronization source clock signal is cut off, an oscillation signal is output to the voltage controlled oscillator based on the previously acquired digital data, and this oscillation signal
It becomes a reference of timing in the DH device.

[0010]

However, this prior art has the following problems.

First, the first problem is that when the HOLDOVER time is long in digital data sampled in a steady state, the phase difference MTIE with the synchronous clock source increases. That is, the frequency of the sampled digital data does not completely match the frequency of the synchronous clock source. When the clock frequency νSAM generated from the sampling data is compared with the clock frequency νORG of the synchronous clock source, there is a frequency deviation ((νSAM / νORG) ≠ 1). Therefore, if HOLDOVER is continued at the frequency νSAM of digital data sampled in the steady state, the phase shifts from the frequency deviation (νSAM / νORG). At this time, if νSAM <νORG, the MTIE (T2 (t)) at the time of HOLDOVER is as shown in FIG.
And the MTIE increases with time.

The second problem is that the circuit becomes complicated and high-speed operation is required to reduce the phase fluctuation at the time of HOLDOVER. That is, in order to reduce the fluctuation of the MTIE, it is necessary to make the frequency deviation (νSAM / νORG) between the clock frequency νSAM generated from the sampling data and the clock frequency νORG of the synchronous clock source close to one. In order to make the frequency deviation close to 1, it is necessary to reduce the quantization error, and it is necessary to increase the number of bits for A / D conversion and D / A conversion and increase the sampling frequency. For this reason, the circuit becomes complicated by increasing the number of bits of the sampling circuit and increasing the speed of the counter circuit.

The present invention provides a phase holding circuit and a phase holding method that solve the above problems.

[0014]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems. In a phase holding method for holding a synchronous source clock signal of an SDH apparatus, the synchronous source clock signal is sampled in a steady state. Digital data is stored in a storage means, and when a clock loss is detected, digital data in the storage means is selected, and an oscillation pulse of a voltage controlled oscillator is generated based on the digital data.

Also, the present invention provides a phase comparison circuit for comparing the phase of the synchronization source clock signal of the SDH device with the output of the voltage controlled oscillator, and an A / D converter for A / D converting the output of the phase comparison circuit.
An A / D conversion circuit, an oscillator that generates a sample signal to be sampled by the A / D conversion circuit, a phase storage circuit that stores a digital output of the A / D conversion circuit,
A selection circuit for selecting a digital output of the D conversion circuit, the pulse and the output data of the phase storage circuit, a D / A conversion circuit for D / A converting the output of the selection circuit, and an output of the D / A conversion circuit A low-pass loop filter, the voltage-controlled oscillator supplied with the output of the loop filter, a clock loss detection circuit for detecting a clock loss from the synchronization source clock signal, and a clock loss detection circuit. A HOLDOVER control circuit that inputs and supplies the clock disconnection signal and instructs storage in the phase storage circuit, and instructs the selection circuit to select and output the output data of the phase storage circuit, based on an output of the oscillator. A phase holding circuit including an A / D conversion circuit, the phase storage circuit, the selection circuit, and a timing generation circuit that supplies a timing signal to a HOLDOVER control circuit; An adding / subtracting circuit for adding / subtracting output data of a storage circuit and supplying the result to the selecting circuit; a comparing circuit for comparing the timing signal with an output of the A / D converter; and a driving circuit based on a result of the comparing circuit. And an addition / subtraction control circuit for controlling the addition / subtraction circuit.

Further, the present invention provides a phase comparison circuit for comparing the phase of a synchronization source clock signal of an SDH device with the output of a voltage controlled oscillator, and an A / D conversion circuit for A / D converting the output of the phase comparison circuit. An oscillator for generating a sample signal to be sampled by the A / D conversion circuit; a phase storage circuit for storing a digital output of the A / D conversion circuit;
A selection circuit for selecting the digital output of the / D conversion circuit, the pulse and the output data of the phase storage circuit, a D / A conversion circuit for D / A conversion of the output of the selection circuit, and a D / A conversion circuit. A loop filter that passes the low frequency of the output, the voltage-controlled oscillator supplied with the output of the loop filter,
A clock loss detection circuit for detecting a clock loss from the synchronization source clock signal; and a selection circuit for inputting and supplying the detected clock loss signal to the clock loss detection circuit and instructing storage in the phase storage circuit. And a timing for supplying a timing signal to the A / D conversion circuit, the phase storage circuit, the selection circuit, and the HOLDOVER control circuit based on the output of the oscillator. A comparator for comparing a digital output of the A / D conversion circuit with the timing signal, and storing the phase according to an output of the comparator and an output of the HOLDOVER control circuit. A sampling control circuit that outputs a sampling signal to the circuit.

Further, in the above phase holding circuit,
When the clock of the synchronization source clock signal is cut off, the digital data holding the phase state before the clock cut off is controlled to reduce MTIE (Maximum Time Interval Error).

[0018]

[First Embodiment] An embodiment of the present invention will be described in detail with reference to the drawings.

(Configuration of the Present Embodiment) FIG. 1 is a block diagram showing the configuration of an apparatus according to an embodiment of the present invention. The embodiment shown in FIG. 1 is a synchronous clock circuit in an SDH (Synchronous Digital Hierarchy) device, and a synchronous source clock signal of an input signal is a synchronous transmission module STM- having a structure of a transmission signal in which various signals are multiplexed. 1 (Synchronous Transport
Module) or a synchronization signal generated by a synchronization signal generator outside the device. The frequency divider N 1 divides the frequency of the synchronization source clock signal by N and sends it to the phase comparison circuit 3.

Similarly, the frequency divider M 2 divides the output clock of the voltage controlled oscillator 11 by M and sends it to the phase comparison circuit 3.
The phase comparison circuit 3 compares the phases of the frequency divider N1 and the frequency divider M2, and sets the “H” level in the rising waveform of the frequency divider M2.
The phase comparison signal 501 which becomes “L” level in the rising waveform of the frequency divider N 1 is sent to the A / D conversion circuit 4.

The A / D conversion circuit 4 samples the phase information by counting up the section in which the phase comparison signal 501 sent from the phase comparison circuit 3 is at “H” level based on the clock 508 of the oscillator 5. To convert to digital data. The count-up result is held at the rising edge of the latch clock 503 from the timing generation circuit 6 described later, and the held data 502 is sent to the phase storage circuit 7, the selection circuit 8, and the comparison circuit 14.

The timing generation circuit 6 generates a latch clock 503 that matches the sampling cycle of the A / D conversion and the phase comparison cycle used for the operation timing of each circuit, based on the clock 508 of the oscillator 5, and performs the A / D conversion. Circuit 4, phase storage circuit 7, selection circuit 8, HOLDOVER control circuit 1
3. Send to the addition / subtraction control circuit 15. Phase storage circuit 7
Stores the data 502 sent from the A / D conversion circuit 4 at the period of the latch clock 503 in a normal state,
In the LDOVER state, an operation of holding the stored data 502 is performed, and the phase storage data 506 held by the addition / subtraction circuit 16 is transmitted.

The selection circuit 8 sends the data 502 sent from the A / D conversion circuit 4 to the D / A conversion circuit 9 in the normal state, and in the HOLDOVER state, stores the phase data sent from the addition / subtraction circuit 16 described later. D / A processing data 507
It is sent to the conversion circuit 9. The D / A conversion circuit 9 converts the digital data sent from the selection circuit 8 into an analog voltage and sends it to the loop filter 10. The loop filter 10 attenuates the high-frequency component of the analog voltage sent from the D / A conversion circuit 9 by a low-pass filter, and sends the result to the voltage-controlled oscillator 11. The voltage controlled oscillator 11
An oscillator capable of varying the oscillation frequency in accordance with the voltage sent from the loop filter 10; and a sending unit for sending the oscillation frequency output to a location related to the synchronization source clock signal of the SDH device or to the next telephone exchange. And the divider M
Send to 2.

On the other hand, the clock loss detection circuit 12 detects the clock loss of the synchronization source clock signal, and
To the HOLDOVER control circuit 13. The HOLDOVER control circuit 13 determines the latch clock 5 based on the synchronization source clock disconnection detection result 504 sent from the clock disconnection detection circuit 12.
The HOLDOVER signal 5 which becomes “H” level indicating the HOLDOVER state or “L” level indicating the normal state in the cycle of 03
05 is a phase storage circuit 7, a selection circuit 8, and an addition / subtraction control circuit 1.
5

The comparison circuit 14 includes an A / D conversion circuit 4
Is held based on the latch clock 503, so that the data 502 one cycle before the latch clock 503 is held. Further, the data 502 is compared with the data held by the comparison circuit 14, and a mismatch signal having an “H” level indicating a mismatch and an “L” level indicating a match according to the comparison result, When the data is larger than the held data, the signal is sent to the addition / subtraction control circuit 15 at a "H" level.

Further, the adder / subtractor control circuit 15 outputs the non-coincidence signal from the comparison circuit 14 in the normal state.
The rising section of the H level is counted based on the latch clock 503, and the value of the counter and the magnitude signal sent from the comparison circuit 14 are stored when the latch clock 503 falls after the rising of the "H" level of the mismatch signal. At the time of HOLDOVER, “H” is generated at the same cycle as the cycle in which the “H” pulse of the mismatch signal is detected based on the stored value obtained by counting the mismatch section by the latch clock 503.
A control signal of a level is generated and sent to the addition / subtraction circuit 16 together with the stored large and small signals. The addition / subtraction circuit 16 stores the phase storage data 50 stored in the phase storage circuit 7 based on the storage value of the magnitude signal sent from the addition / subtraction control circuit 15.
Then, data obtained by performing an addition / subtraction process on 6 is generated.

At this time, if the control signal from the addition / subtraction control circuit 15 is at "L" level, the phase storage data 506 is stored in "
If the level is H ", the data subjected to the addition / subtraction processing is selected, and the phase storage processing data 507 is sent to the selection circuit 8.

FIG. 2 is a circuit added according to the present invention.
FIG. 3 is a detailed diagram of a comparison circuit, an addition / subtraction control circuit, and an addition / subtraction circuit. The comparison circuit 14 holds the data 502 held after sampling by the A / D conversion circuit 4 on the basis of the latch clock 503, so that the data storage circuit 101 holds the held data 502 one cycle before the latch clock. The data held in the storage circuit 101 is compared with the data 502, and when the comparison result is different, the non-coincidence signal “a” of the “H” level, and when the comparison result is the same, the “L” level mismatch signal a is output to the counter 103, the counter storage circuit 104, and the addition / subtraction storage circuit 106. And if the data 502 is larger than the data held in the data storage circuit 101,
An addition / subtraction storage circuit 106 outputs a high / low signal b, which is an H level, a low level when the level is low, and is maintained as it is if the level is the same.
To send to.

The addition / subtraction control circuit 15 includes a comparator 10
2, a counter 103 that detects the rise of the "H" level of the mismatch signal a sent out from the counter 2 and counts the detection period based on the latch clock 503; a counter storage circuit 104 that stores the count-up result of the counter; The control signal generator 105 includes a control signal generator 105 that generates an “H” level pulse at a cycle of “H” level rising, and an addition / subtraction storage circuit 106 that stores a large / small signal b sent from the comparator 102. 105 sends the control signal d to the selector 108, and
6 sends the stored value c to the adder / subtractor 107.

The addition / subtraction circuit 16 includes a phase storage circuit 7
In accordance with the storage value c from the addition / subtraction control circuit 15 to the output phase storage data 506, 1 is added to the phase storage data 506 when the storage value c is at “H” level, and when the storage value c is at “L” level, The adder / subtracter 107 for subtracting 1 from the phase storage data 506, and the phase storage data 506 and the data obtained by the addition / subtraction processing according to the control signal d. When the control signal d is at the “H” level, the data obtained by the addition / subtraction processing is changed to “L”. At the time of the level, the selector 108 selects the phase storage data 506, and the selector 108 sends the selected data to the selection circuit 8 as the phase storage processing data 507.

(Operation of the Present Embodiment) Next, the circuit operation of FIGS. 1 and 2 will be described with reference to the time charts of FIGS. 3, 4 and 5. When the synchronization source clock signal is input and the frequency is constant in a steady state in a normal state, the phase comparison signal 501 of the phase comparison circuit 3 has a constant value corresponding to the frequency of the synchronization source clock signal. FIG. 3 shows an A / D conversion circuit 4
In the operation example of “1”, the “H” level section T of the phase comparison signal 501
At 0 to T1, the counter is counted and sampled based on the clock of the oscillator 5 to convert it into a digital value, and the value of the data 502 becomes "n". Similarly, in the "H" level section T'0 to T2 of the phase comparison signal 501, the phase comparison signal 501 is converted into digital value phase information. At this time, the phase difference signal of the analog value is sampled based on the clock of the oscillator 5 and converted into a digital value, so that the time less than one clock time of the oscillator 5 cannot be counted. Therefore, the time from T'0 to T2 becomes a count up to the time T'1 and the data 502 becomes "n".

Therefore, the time from T'1 to T2 cannot be counted as a quantization error. Similarly, the phase comparison signal 501
In the H "level, in the sections T" 0 to T3, the count up to the time T "1 is counted, and the value of the data 502 is" n ". At this time, the operation of the voltage controlled oscillator 11 includes the phase comparison signal 5
01 “n” of A / D conversion data 502 of T0 to T1
Is returned to an analog voltage by the D / A conversion circuit 9 and is input to the voltage controlled oscillator 11 via the loop filter 10 to control the frequency. The phase comparison signal 501 between the clock of the frequency controlled voltage controlled oscillator 11 and the synchronization source clock is “H”.
Level sections T′0 to T2 are set. Data 50 as before
The value of 2 becomes "n", the output frequency of the voltage controlled oscillator 11 becomes the same, the quantization error is accumulated in the next A / D conversion cycle from time T'1 to T2, and the phase comparison signal 501 becomes "
H level, section T "0 to T3.

That is, when the quantization error becomes a cumulative error for one clock of the oscillator 5 serving as a sampling clock, the A / D conversion circuit 4 counts and corrects the error. A /
Since the value of the data 502 of the D conversion circuit 4 is “n”, the value of the data 502 of the A / D conversion circuit 4 when the quantization error has accumulated for one clock of the oscillator 5 is “n + 1” (or “
n-1 ").

As described above, since the quantization error is the same if the synchronization source clock has a constant frequency, the value of the data 502 of the A / D conversion circuit 4 is "n" at a constant period u as shown in FIG.
+1 "appears.

The operation of the comparison circuit 14 at this time is shown in FIG.
Will be described. Based on the latch clock 503, the data 502 of the A / D conversion circuit 4 is compared with the data stored in the data storage circuit 101 and the data 502 of the A / D conversion circuit 4. Mismatch signal a
Since the data 502 is larger than the data stored in the data storage circuit 101, the large / small signal b is output as the “H” level. FIG. 4B shows a case where the sampling result of the accumulated error is “n−1”.
2 is compared with the data stored in the data storage circuit 101 and the data 502 of the A / D conversion circuit 4 based on the latch clock 503, and when a difference is detected, an "H" level mismatch signal a is sent out. 502 is the data storage circuit 1
01, the large / small signal b
Output as L level.

The addition / subtraction control circuit 15 includes a comparator 10
The counter 103 counts up the “L” level and the section of the non-coincidence signal “a” based on the latch clock 503, and stores the number counted at the falling edge of the latch clock 503 after the “H” level rise of the non-coincidence signal “a”. The information is stored in the circuit 104 and the counter 103 is cleared. At the same timing as above, the large / small signal b of the comparator 102
Is stored in the addition / subtraction storage circuit 106.

On the other hand, when the synchronization source clock signal has lost the clock, the clock loss detecting circuit 12 detects the clock loss, sets the detection result 504 to "H" level, and
It is sent to the OVER control circuit 13. HOLDOVER control circuit 13
When the detection result 504 becomes “H” level, HOLDOVER
The signal 505 is set to “H” level and sent to the phase storage circuit 7, the selection circuit 8, and the addition / subtraction control circuit 15.

Next, when the HOLDOVER signal 505 becomes "H" level, the phase storage circuit 7, the counter storage circuit 104
The addition and subtraction storage circuit 106 performs an operation of holding the value stored in the normal state, and the control signal generator 105 uses the cycle of the latch clock 503 of the value stored in the counter storage circuit 104 to store one clock of the latch clock 503. A control signal d to be an “H” level pulse is sent to the selector 108. The adder / subtractor 107 performs an addition / subtraction process on the phase storage data 506 stored in the phase storage circuit 7 and stores a storage value c
Performs data processing of adding 1 with an "H" level signal and subtracting 1 with an "L" level signal.

The selector 108 is connected to the selection signal generator 10
5 is "L" level and the phase storage data 506
Is sent to the selection circuit 8 as it is, and data obtained by adding / subtracting the phase storage data 506 at the “H” level is sent to the selection circuit 8.

FIG. 5 (a) shows an example of a case where the phase information sampling result in the steady state is as shown in FIG. 4 (a). 5 is a time chart illustrating the operation of each circuit. When HOLDOVER is reached, the phase storage circuit 7 performs an operation of holding the phase information data 502 “n”.
Similarly, the counter storage circuit 104 outputs "
H level, cycle data “6”, addition / subtraction storage circuit 106
Holds an "L" level stored value.

Next, the control signal generator 105 uses the “H” level of the non-coincidence signal “a” held by the counter storage circuit 104 and the periodic data “6” to latch the clock 503.
, A control signal d which goes to the “H” level once every six clocks is generated. The adder / subtractor 107 performs a process of adding 1 to the phase storage data 506 when the storage value c of the addition / subtraction storage circuit 106 is “L” level, and selects “n + 1” data from the selector 108.
To send to. The selector 108 selectively outputs the phase storage data 506 “n” when the control signal d is at “L” level, and the data “n + 1” obtained by adding the phase storage data 506 when the control signal d is at “H” level. "Is selected and output.

As a result, the data of "n + 1" is output from the selection circuit 8 every cycle u which is the same as in the normal state.

FIG. 5 (b) shows an example of the case where the phase information sampling result in the steady state is as shown in FIG. 4 (b).
5 is a time chart illustrating an operation of each circuit that is brought into a HOLDOVER state due to a clock cut of a synchronization source clock, and an operation of each circuit will be described. When HOLDOVER occurs, the phase storage circuit 7
Performs an operation of holding the data 502 “n” of the phase information. Similarly, the counter storage circuit 104 outputs ""
H level, cycle data “6”, addition / subtraction storage circuit 106
Holds an "H" level stored value.

Next, the control signal generator 105 uses the "H" level cycle data "6" of the mismatch signal a held by the counter storage circuit 104 to "H" once every six clocks of the latch clock 503. A control signal d which becomes a level is generated. The adder / subtractor 107 performs a process of reducing the storage value c of the addition / subtraction storage circuit 106 by one from the “H” level to the phase storage data 506, and sends out “n−1” data to the selector 108. The selector 108 selectively outputs the phase storage data 506 “n” when the control signal d is “L” level, and outputs the phase storage data 506 when the control signal d is “H” level.
Is selectively output as data "n-1".

As a result, the data of "n-1" is output from the selection circuit 8 every period u which is the same as in the normal state.

(Second Operation of the Present Embodiment) In FIG. 1, in a normal state (when the clock loss detecting circuit 12 does not detect the clock loss of the synchronization source clock), the phase storage circuit 7 stores the A / A In the D conversion circuit 4, the phase comparison signal 501 is sampled by the output clock 508 of the oscillator 5,
The digital phase information 502 is held by a phase comparison frequency latch clock 503. The comparison circuit 14 compares the output data 502 of the A / D conversion circuit 4 held by the latch clock 503 with the data 502 held by the latch clock 503 one cycle earlier.
The non-coincidence signal at the H level and the magnitude signal at the H level when the data 502 held by the A / D conversion circuit 4 is larger than the held data are sent to the addition / subtraction control circuit 15.

Next, the addition / subtraction control circuit 15 measures the time of the "H" level rising section of the non-coincidence signal from the comparison circuit 14 based on the latch clock 503, and stores the time together with the magnitude signal of the comparison result.

When the disconnection of the synchronization source clock is detected by the clock disconnection detecting circuit 12, the HOLDOVER control circuit 13
Sets the HOLDOVER signal 505 to “H” level,
Is switched to the phase storage processing data 507 via the phase storage circuit 7 and the addition / subtraction circuit 16.

Next, the addition / subtraction control circuit 15 supplies the addition / subtraction circuit 16 with a control signal that becomes an “H” level pulse synchronized with the rising cycle of the “H” level pulse of the non-coincidence signal stored in the steady state, and the storage result of the large / small signal. Send out. The addition / subtraction circuit 16 calculates the phase storage data 50 stored in the phase storage circuit 7 based on the storage result of the magnitude signal from the addition / subtraction control circuit 15.
Then, data obtained by performing an addition / subtraction process on 6 is generated. At the control signal “L” level, data input from the phase storage circuit 7 is selected, and at the “H” level, data subjected to addition / subtraction processing is selected and sent to the selection circuit 8.

Thus, based on the cycle of the mismatch signal stored in the addition / subtraction control circuit 15, the voltage control oscillator 11 is controlled by the data stored in the phase storage circuit 7 and the data subjected to the addition / subtraction processing by the addition / subtraction circuit 16.

The phase holding circuit according to the present invention reduces the MTIE of the output clock by controlling the phase storage data during HOLDOVER when the clock is cut off.

[Second Embodiment] Next, a second embodiment of the present invention will be described in detail with reference to the drawings. 7 and 8 are a block diagram of the phase holding circuit according to the embodiment of the present invention and a block diagram showing details of the difference between FIG. 11 and FIG. 7 of the conventional example. Note that the same parts as those in the configuration of FIG. 1 according to the first embodiment are denoted by the same reference numerals, and redundant description will be omitted.

In FIGS. 7 and 8, the sampling control circuit 17 includes a counter 103 as in the first embodiment.
Then, the counter 103 counts up the "L" level section of the mismatch signal a of the comparator 102 based on the latch clock 503, and counts the number counted at the "H" level of the mismatch signal a and the falling edge of the latch clock 503. The data is stored in the counter storage circuit 104. Counter storage circuit 10
The value e stored at 4 is sent to the storage control circuit 109 of the phase storage circuit 18. Unlike the phase storage circuit 7 of the first embodiment, the phase storage circuit 18 has an X (X ≧ 2) sample storage circuit 110, and can change the number of samples that can be stored by a signal from the storage control circuit 109. Data 502 for X latch clocks can be stored.

Here, in the steady state, the storage value e of the result “6” counted by the counter 103 is sent to the storage control circuit 109 by the counter storage circuit 104 as shown in FIG. Since the storage value e is “6”, the storage control circuit 109 controls the number of samples that can be stored in the X sample storage circuit 110 to be “6”, and the A / D conversion circuit 4 controls the phase comparison signal. As shown in FIG. 9, the data 502 sampled and held is stored as data 502 for six latch clocks. When the synchronization source clock signal is cut off and enters the HOLDOVER state, the counter storage circuit 104 and the X sample storage circuit 110 hold the data stored so far. This example is shown in FIG. Using the storage value “6” of the counter storage circuit 104,
The X sample storage circuit 110 inside the phase storage circuit 18
The stored data for the six latch clocks is repeatedly transmitted as the phase storage data 509 in the storage order. The advantage of this embodiment is that the configuration of the adder / subtractor 107 is not required, so that there is an advantage that the phase holding circuit can be simplified.

[0055]

[Explanation of effect] According to the present invention, even if it is HOLDOVER,
Since the phase is corrected in the same manner as in the normal state, the movement of the MTIE becomes as shown in FIG. 6, which is smaller than in the conventional case.
IE can be suppressed.

Conventionally, in order to suppress the MTIE during HOLDOVER and to reduce the quantization error, it is necessary to increase the number of bits of A / D conversion and D / A conversion and operate the circuit at high speed. However, according to the present invention, A / D conversion, D
Since the number of bits for the / A conversion can be reduced as compared with the conventional case, and the circuit can operate at low speed, the circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of a phase holding circuit according to a first embodiment of the present invention.

FIG. 2 is a detailed block diagram of a phase holding circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart of the phase holding circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart of the phase holding circuit according to the first embodiment of the present invention.

FIG. 5 is a timing chart of the phase holding circuit according to the first embodiment of the present invention.

FIG. 6 is a characteristic diagram of the MTIE according to the first embodiment of the present invention.

FIG. 7 is a block diagram of a phase holding circuit according to a second embodiment of the present invention.

FIG. 8 is a detailed block diagram of a phase holding circuit according to a second embodiment of the present invention.

FIG. 9 is a timing chart of the phase holding circuit according to the second embodiment of the present invention.

FIG. 10 is a characteristic diagram of an MTIE according to a conventional example.

FIG. 11 is a block diagram of a conventional phase holding circuit.

FIG. 12 is a characteristic diagram of MTIE of a conventional phase holding circuit.

[Explanation of symbols]

 1 frequency divider N 2 frequency divider M 3 phase comparison circuit 4 A / D conversion circuit 5 oscillator 6 timing generation circuit 7 phase storage circuit 8 selection circuit 9 D / A conversion circuit 10 loop filter 11 voltage controlled oscillator 12 clock loss detection Circuit 13 HOLDOVER 14 Comparison circuit 15 Addition / subtraction control circuit 16 Addition / subtraction circuit 17 Sampling control circuit 18 Phase storage circuit 101 Data storage circuit 102 Comparator 103 Counter 104 Counter storage circuit 105 Control signal generator 106 Addition / subtraction storage circuit 107 Addition / subtraction unit 108 Selector 109 Storage control circuit 110 X sample storage circuit

Claims (8)

[Claims] 1. A phase holding method for holding a synchronization source clock signal of an SDH device, wherein digital data sampled from the synchronization source clock signal in a steady state is stored in a storage means, and the storage is performed when a clock loss is detected. A phase holding method, wherein the digital data of the means is selected and an oscillation pulse of a voltage controlled oscillator is generated based on the digital data. 2. The phase holding method according to claim 1, wherein the digital data in the storage means is added or subtracted by data obtained by comparing the phase of the synchronization source clock signal with the oscillation pulse of a voltage controlled oscillator. Phase holding method. 3. A phase comparison circuit for comparing a phase of a synchronization source clock signal of an SDH device with an output of a voltage controlled oscillator, an A / D conversion circuit for A / D converting an output of the phase comparison circuit, An oscillator that generates a sample signal to be sampled by the D conversion circuit, a phase storage circuit that stores a digital output of the A / D conversion circuit, and a digital output of the A / D conversion circuit and output data of the phase storage circuit. A selection circuit for selecting any one of them, and an output of the selection circuit D / A
A D / A conversion circuit for conversion, a loop filter that passes a low-pass output of the D / A conversion circuit, the voltage-controlled oscillator supplied with the output of the loop filter, and a clock disconnection from the synchronization source clock signal. And a clock disconnection signal detected by the clock disconnection detection circuit, and supplies the clock disconnection signal to the phase storage circuit to supply the clock disconnection signal to the phase storage circuit, and instructs the selection circuit to output data of the phase storage circuit. And a timing generation circuit that supplies a timing signal to the A / D conversion circuit, the phase storage circuit, the selection circuit, and the HOLDOVER control circuit based on the output of the oscillator. A circuit for adding / subtracting output data of the phase storage circuit and supplying the data to the selection circuit; a timing signal and an output of the A / D converter; Phase hold circuit, characterized in that it comprises a comparator circuit for comparing the door, and a subtraction control circuit for controlling the addition and subtraction circuit is driven based on the result of the comparison circuit. 4. A data storage circuit for storing an output of the A / D converter based on the timing signal, and comparing an output of the data storage circuit with an output of the A / D converter. 4. The phase holding circuit according to claim 3, comprising a comparator that performs the operation. 5. An addition / subtraction control circuit comprising: a counter for counting the timing signal during an output period of the comparator; a counter storage circuit for storing a count value of the counter; and an output of the comparator and the timing signal. The HO
An addition / subtraction storage circuit that stores the output according to the output of the LDOVER control circuit; and a control signal generator that generates a control signal to the addition / subtraction circuit using the output of the counter storage circuit as a trigger in accordance with the output of the HOLDOVER control circuit and the timing signal. 5. The phase holding circuit according to claim 4, comprising: 6. A phase comparison circuit for comparing the phase of a synchronization source clock signal of an SDH device with the output of a voltage controlled oscillator, an A / D conversion circuit for A / D converting the output of the phase comparison circuit, An oscillator that generates a sample signal to be sampled by the D conversion circuit, a phase storage circuit that stores a digital output of the A / D conversion circuit, and a digital output of the A / D conversion circuit and output data of the phase storage circuit. A selection circuit for selecting any one of them, and an output of the selection circuit D / A
A D / A conversion circuit for conversion, a loop filter that passes a low-pass output of the D / A conversion circuit, the voltage-controlled oscillator supplied with the output of the loop filter, and a clock disconnection from the synchronization source clock signal. And a clock disconnection signal detected by the clock disconnection detection circuit, and supplies the clock disconnection signal to the phase storage circuit to supply the clock disconnection signal to the phase storage circuit, and instructs the selection circuit to output data of the phase storage circuit. And a timing generation circuit that supplies a timing signal to the A / D conversion circuit, the phase storage circuit, the selection circuit, and the HOLDOVER control circuit based on the output of the oscillator. A comparison circuit for comparing a digital output of the A / D conversion circuit with the timing signal;
A sampling control circuit for outputting a sampling signal to the phase storage circuit in accordance with an output of the HOLDOVER control circuit. 7. The sampling control circuit stores a counter that counts the timing signal according to an output of the comparison circuit, and stores a count value of the counter according to the timing signal and an output of the HOLDOVER control circuit. 7. The phase holding circuit according to claim 6, comprising a counter storage circuit. 8. The phase holding circuit according to claim 3, wherein when the clock of the synchronization source clock signal is cut off, the digital data holding the phase state before the clock cut-off is controlled to control the MTIE ( Maximum Tim
A phase holding circuit characterized by reducing e Interval Error).